CN102998497A - Production method of skip type probe card - Google Patents
Production method of skip type probe card Download PDFInfo
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- CN102998497A CN102998497A CN2012105298855A CN201210529885A CN102998497A CN 102998497 A CN102998497 A CN 102998497A CN 2012105298855 A CN2012105298855 A CN 2012105298855A CN 201210529885 A CN201210529885 A CN 201210529885A CN 102998497 A CN102998497 A CN 102998497A
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- probe
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- tube core
- tabbing
- probe card
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- Measuring Leads Or Probes (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The invention relates to a production method of a skip type probe card based on a vertical probe card during a wafer multi-die parallel test of a semiconductor radio frequency device. Probes are produced every other die in odd-numbered lines and not produced in even-numbered lines; the step distance during the test of the probe card is the width of one die for the first time and widths of 15 dies for the second time. The production method solves the problem of mutual interference of the multi-die parallel test of the radio frequency device, can improve the testing efficiency and is suitable for mass production tests.
Description
Technical field
The present invention relates to a kind ofly when carrying out the Multi-core concurrent testing in semiconductor devices wafer sort process, a kind of tabbing formula vertical probe card manufacturing method belongs to the semiconductor test technical field.
Background technology
Progress along with semiconductor process techniques, 12 o'clock wafers for the production of, wafer area has increased, can make several thousand or up to ten thousand tube cores on the wafer, in order to improve the throughput of test machine by the quantity that increases tested tube core in the unit interval, reduce the test machine slack resources, improve the utilization factor of testing apparatus, lower testing cost, usually adopt Multi-core concurrent testing technology, Multi-core concurrent testing technology refers to can automatically detect a plurality of semiconductor elements simultaneously on a test machine, the probe of making by specialized designs can be connected on the pin of a plurality of tube cores simultaneously, so that test machine can carry out the test of a plurality of tube cores simultaneously, and record the test result of a plurality of chips;
Probe is the vitals that carries out die testing, fundamental purpose be with the probe on the probe directly with tube core on aluminium pad (pad) or projection (bump) directly contact, draw the tube core signal, cooperate again the control of test macro and testing software to reach the purpose of automatic measurement.
To containing the tube core of radio-frequency module, measuring stability is poor during the Multi-core concurrent testing, and the wafer yield is undesirable, and testing efficiency is low; Therefore, how to solve the device that contains radio-frequency module and realize the Multi-core concurrent testing, become one of key technical problem that those skilled in the art need to be resolved hurrily.
Summary of the invention
The objective of the invention is to solve the device that contains radio-frequency module and realize the Multi-core concurrent testing, found effective, a reliable method;
Technical solution of the present invention is to use vertical probe carb, and vertical probe carb is unstressed probe, and, can realize the various arrangement mode.
On the semiconductor crystal wafer silicon chip, the arrangement of tube core has the aluminium pad that varies in size as gridiron pattern on each tube core;
The present invention is the corresponding probe of each aluminium pad, probe is not to make probe by the gridiron pattern order, but first die making's probe of the first row, next tube core is not made probe, the 3rd die making's probe, the like, until the 15th pipe, the first row is made the probe of 8 tube cores altogether, crosses over 15 tube cores.
Odd-numbered line is every die making's probe, and even number line is not made probe;
It is a die width that step distance in the exploration card test process of the present invention is set to for the first time, is 15 die width for the second time, by that analogy; Step direction without limits.
Radio-frequency antenna pin L1 and the L2 of the tested tube core aluminium of described invention pad are the diagonal line layout, scattered distribution, conventional probe arrange be difficult to increase adjacent with the distance between test tube core antenna.
The present invention can learn that by above-mentioned analysis the source of interference is the antenna pin of chip, must try every possible means adjacently to reduce disturbing effect between the tube core with the distance between test tube core antenna by increasing.
The invention solves and side die test mutual interference problem, tested tube core power pin is on the impact of functional test and the stability problem in the test process.
Description of drawings
Be described further below in conjunction with accompanying drawing and specific embodiments:
Fig. 1 is wafer figure synoptic diagram, and each little lattice represents a tube core.
The conventional probe of Fig. 2 is made mode
Fig. 3 is tabbing probe manufacturing mode
Fig. 4 probe moves order
The aluminium pad position of Fig. 5 tube core
Embodiment
The present invention is further detailed in conjunction with the accompanying drawings below:
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization in the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public implementation.
Secondly, the present invention utilizes synoptic diagram to be described in detail, and when the embodiment of the invention was described in detail in detail, for ease of explanation, the synoptic diagram of expression probe structure amplified, and described synoptic diagram is example, and it should not limit the scope of protection of the invention at this.
Fig. 1 shows the present invention and is used for semiconductor devices crystal circle structure synoptic diagram, and 99 is exactly the shape of probe.Shown in Figure 2 is probe conventional spread mode, have 64 tube cores, quadrate is arranged in order, 5 aluminium pads that vary in size are arranged on the tube core that the present invention relates to, die size 1.77mm X 1.77mm, it is 4 on the left side that the aluminium pad is arranged, following one, the area minimum of aluminium pad is 45um X 80um, maximum area is 86umX 86um, and Fig. 5 has shown the aluminium pad arrangement position of tested tube core of the present invention, and L1, L2 are tube core radiofrequency signal pins; The exploration card area is 14.16mm X 14.16mm under the conventional spread mode;
The invention provides a kind of probe for the semiconductor devices wafer and make arrangement mode, as shown in Figure 3, the tabbing formula is arranged, and the area of probe is 26.55mm X 26.55mm.
Concrete method for making is:
21 do not make probe;
23 make probe, repeat the first row, make altogether the probe of 8 tube cores, cross over equally 15 tube cores;
Fourth line is not made probe;
Fifth line repeats the third line; By that analogy;
Probe manufacturing is up to the 15th row, and 151 make probes, and 1515 make probes;
Odd-numbered line is every die making's probe in other words, and even number line is not made probe, and having 64 tube cores has probe;
Shown in Figure 4 is the track that probe is moved in test process, probe falls once, tests simultaneously 64 tube cores, and mobile 15 die site fall again, test again simultaneously 64 tube cores, arrive successively whole wafer the right to the right, turn to down again, left, until finish, also can use other motion track, but step distance must be first next die width, for the second time 15 die width.
The present invention is not subjected to the restriction of the aluminium pad arrangement mode of tested tube core and aluminium pad number, aluminium pad area;
Compared with prior art, the vertical probe carb tabbing formula arrangement mode that the present invention is used for semiconducter device testing has solved semiconductor devices wafer concurrent testing tube core antenna pin cross-interference issue, the present invention has strengthened the spacing of adjacent tested tube core, so that the spacing minimum of adjacent tested tube core is a chip size.
Arrange by the tabbing form, disturb between the tube core that greatly reduces to cause because of the antenna pin; Improved measuring stability.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (4)
1. a tabbing formula probe making method is characterized in that;
Vertical probe carb can be realized the various arrangement mode;
The corresponding probe of each aluminium pad of tested tube core;
It is characterized in that: probe making mode is that the tabbing formula is arranged, and odd-numbered line is every die making's probe, and even number line is not made probe.
2. tabbing formula probe making method according to claim 1 is characterized in that: it is a die width that the step distance in the exploration card test process is set to for the first time, is 15 die width for the second time, and by that analogy, step direction without limits.
3. tabbing formula probe making method according to claim 2 is characterized in that: there is the radio-frequency antenna pin in tested tube core.
4. tabbing formula probe making method according to claim 3 is characterized in that: tested tube core radio-frequency antenna pin L1 and L2 are diagonal line layout, scattered distribution.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201210529885.5A CN102998497B (en) | 2012-12-11 | 2012-12-11 | A kind of production method of skip type probe card |
Applications Claiming Priority (1)
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CN201210529885.5A CN102998497B (en) | 2012-12-11 | 2012-12-11 | A kind of production method of skip type probe card |
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CN102998497A true CN102998497A (en) | 2013-03-27 |
CN102998497B CN102998497B (en) | 2015-12-02 |
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CN201210529885.5A Expired - Fee Related CN102998497B (en) | 2012-12-11 | 2012-12-11 | A kind of production method of skip type probe card |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104614658A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | Method for testing high-frequency chip wafers through multi-channel probe card |
CN107422242A (en) * | 2016-05-23 | 2017-12-01 | 北大方正集团有限公司 | The test device and method of a kind of VDMOS chip |
US10012676B2 (en) | 2015-10-20 | 2018-07-03 | Global Unichip Corporation | Probe card and testing method |
CN109655737A (en) * | 2018-12-24 | 2019-04-19 | 北京华峰测控技术股份有限公司 | A kind of test method of wafer |
CN115754388A (en) * | 2022-10-19 | 2023-03-07 | 深圳锐盟半导体有限公司 | Probe card, chip testing method, testing machine and storage medium |
CN117538736A (en) * | 2024-01-09 | 2024-02-09 | 杭州芯云半导体技术有限公司 | Method and system for testing radio frequency chip |
CN118553635A (en) * | 2024-07-30 | 2024-08-27 | 杭州长川科技股份有限公司 | Wafer probe station detection path planning method, device and equipment and probe station |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1912636A (en) * | 2005-08-10 | 2007-02-14 | 陈文祺 | Probe structure of preventing noise interference for semiconductor test board |
CN1912633A (en) * | 2005-08-09 | 2007-02-14 | 陈文祺 | Semiconductor test plate structure for preventing noise interference |
CN1979178A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Vertrical probe clasp mfg. method |
WO2008114973A1 (en) * | 2007-03-16 | 2008-09-25 | M2N Inc. | Probe card having planarization means |
CN101949961A (en) * | 2010-08-16 | 2011-01-19 | 中国电子科技集团公司第五十五研究所 | Direct current offset probe card for radio frequency test |
-
2012
- 2012-12-11 CN CN201210529885.5A patent/CN102998497B/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1912633A (en) * | 2005-08-09 | 2007-02-14 | 陈文祺 | Semiconductor test plate structure for preventing noise interference |
CN1912636A (en) * | 2005-08-10 | 2007-02-14 | 陈文祺 | Probe structure of preventing noise interference for semiconductor test board |
CN1979178A (en) * | 2005-12-08 | 2007-06-13 | 上海华虹Nec电子有限公司 | Vertrical probe clasp mfg. method |
WO2008114973A1 (en) * | 2007-03-16 | 2008-09-25 | M2N Inc. | Probe card having planarization means |
CN101949961A (en) * | 2010-08-16 | 2011-01-19 | 中国电子科技集团公司第五十五研究所 | Direct current offset probe card for radio frequency test |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104614658A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | Method for testing high-frequency chip wafers through multi-channel probe card |
CN104614658B (en) * | 2015-01-28 | 2017-04-26 | 山东华翼微电子技术股份有限公司 | Method for testing high-frequency chip wafers through multi-channel probe card |
US10012676B2 (en) | 2015-10-20 | 2018-07-03 | Global Unichip Corporation | Probe card and testing method |
CN107422242A (en) * | 2016-05-23 | 2017-12-01 | 北大方正集团有限公司 | The test device and method of a kind of VDMOS chip |
CN109655737A (en) * | 2018-12-24 | 2019-04-19 | 北京华峰测控技术股份有限公司 | A kind of test method of wafer |
CN109655737B (en) * | 2018-12-24 | 2020-11-27 | 北京华峰测控技术股份有限公司 | Wafer testing method |
CN115754388A (en) * | 2022-10-19 | 2023-03-07 | 深圳锐盟半导体有限公司 | Probe card, chip testing method, testing machine and storage medium |
CN115754388B (en) * | 2022-10-19 | 2023-09-29 | 深圳锐盟半导体有限公司 | Probe card, chip testing method, tester and storage medium |
CN117538736A (en) * | 2024-01-09 | 2024-02-09 | 杭州芯云半导体技术有限公司 | Method and system for testing radio frequency chip |
CN118553635A (en) * | 2024-07-30 | 2024-08-27 | 杭州长川科技股份有限公司 | Wafer probe station detection path planning method, device and equipment and probe station |
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CN102998497B (en) | 2015-12-02 |
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