CN117538736A - Method and system for testing radio frequency chip - Google Patents
Method and system for testing radio frequency chip Download PDFInfo
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- CN117538736A CN117538736A CN202410026408.XA CN202410026408A CN117538736A CN 117538736 A CN117538736 A CN 117538736A CN 202410026408 A CN202410026408 A CN 202410026408A CN 117538736 A CN117538736 A CN 117538736A
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- 238000012360 testing method Methods 0.000 title claims abstract description 288
- 238000000034 method Methods 0.000 title claims abstract description 37
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- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 claims description 5
- 229920002379 silicone rubber Polymers 0.000 claims description 5
- 239000004945 silicone rubber Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 238000010998 test method Methods 0.000 claims 4
- 230000008569 process Effects 0.000 abstract description 14
- 230000035945 sensitivity Effects 0.000 abstract description 8
- 230000000694 effects Effects 0.000 description 7
- 230000005540 biological transmission Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 4
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- 230000004075 alteration Effects 0.000 description 2
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- 230000002093 peripheral effect Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
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- 125000004122 cyclic group Chemical group 0.000 description 1
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- 238000012545 processing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
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Abstract
The invention discloses a method and a system for testing a radio frequency chip, wherein the testing method specifically comprises the following steps: a radio frequency test circuit is built in advance, and a protection assembly is built on a test head; setting at least two radio frequency chip groups to be tested according to the layout positions of the radio frequency chips to be tested and a preset interval distance; acquiring a plurality of radio frequency chip test modes, wherein the number of the radio frequency chip test modes is not less than the number of radio frequency chip groups to be tested; and sequentially completing various radio frequency chip test modes in each radio frequency chip set to be tested, wherein the radio frequency chip test modes of each radio frequency chip set to be tested are different in each time frame. According to the invention, the radio frequency test circuit is optimized, the protection component in the test process is set, and the test sensitivity, the anti-interference capability, the precision and the test efficiency of the radio frequency chip are improved by combining the crossing and parallel test modes of various test modes.
Description
Technical Field
The invention belongs to the technical field of radio frequency chips, and particularly relates to a method and a system for testing a radio frequency chip.
Background
When testing radio frequency products, the high test sensitivity is generally required, and the test frequency and the signal attenuation are controlled in an extremely high precision range. In general, specific improvements and perfects are performed on the current ATE (automatic integrated circuit tester) according to different test scene requirements.
As shown in patent CN115692233a, a method for testing a radio frequency chip is provided, the radio frequency wafer includes a device area and a peripheral area surrounding the device area, the device area has a plurality of radio frequency chips distributed in an array, the peripheral area has a plurality of test pad groups, the test pad groups are in one-to-one correspondence with the radio frequency chips, each test pad group has a plurality of test pads, the test pads in the test pad groups are electrically connected with the leading-out ends of the corresponding radio frequency chips, the wafer level radio frequency probe station is used for electrically testing the radio frequency wafer, and the probes of the wafer level radio frequency probe station are contacted with the test pads in the corresponding test pad groups to obtain qualified radio frequency chips in the radio frequency wafer. During testing, the probe only contacts the testing bonding pad, so that the radio frequency chip is prevented from being damaged due to overlarge pressure between the probe and the leading-out end of the radio frequency chip, and the yield of the radio frequency chip is improved.
As another example, patent CN114325340a provides a system and a method for testing a radio frequency chip, where the system is provided with a radio frequency interface module, at least two first power dividers of the radio frequency interface module are connected to radio frequency input ports of at least two radio frequency chips, and a second power divider and a third power divider of the radio frequency interface module connect radio frequency output ports of at least two radio frequency chips to a signal measurement device, so as to implement testing of at least two radio frequency chips.
The testing device and the testing system of the radio frequency chip are improved and designed from the dimensions of yield, testing efficiency and the like of the radio frequency chip in the prior art.
However, implementation of a single-dimensional effect is often premised on discarding another-dimensional effect, and there is less research on a radio frequency chip test scheme for implementing a multi-dimensional effect.
Therefore, how to improve the testing efficiency and the anti-interference capability in the testing process of the radio frequency chip by the design of the testing system with low cost and the design of the testing method are the problems to be solved by the technicians in the field.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a method and a system for testing a radio frequency chip, wherein the method for testing comprises the following steps: a radio frequency test circuit is built in advance, and a protection assembly is built on a test head; setting at least two radio frequency chip groups to be tested according to the layout positions of the radio frequency chips to be tested and a preset interval distance; acquiring a plurality of radio frequency chip test modes, wherein the number of the radio frequency chip test modes is not less than the number of radio frequency chip groups to be tested; and sequentially completing various radio frequency chip test modes in each radio frequency chip set to be tested, wherein the radio frequency chip test modes of each radio frequency chip set to be tested are different in each time frame.
According to the invention, the radio frequency test circuit is optimized, the protection component in the test process is set, and the test sensitivity, the anti-interference capability, the precision and the test efficiency of the radio frequency chip are improved by combining the crossing and parallel test modes of various test modes.
In a first aspect, the present invention provides a method for testing a radio frequency chip, specifically including the following steps:
a radio frequency test circuit is built in advance, and a protection assembly is built on a test head;
setting at least two radio frequency chip groups to be tested according to the layout positions of the radio frequency chips to be tested and a preset interval distance;
acquiring a plurality of radio frequency chip test modes, wherein the number of the radio frequency chip test modes is not less than the number of radio frequency chip groups to be tested;
and sequentially completing various radio frequency chip test modes in each radio frequency chip set to be tested, wherein the radio frequency chip test modes of each radio frequency chip set to be tested are different in each time frame.
According to the invention, the radio frequency test circuit is optimized, the protection component in the test process is set, and the test sensitivity, the anti-interference capability, the precision and the test efficiency of the radio frequency chip are improved by combining the crossing and parallel test modes of various test modes.
Further, the radio frequency test circuit comprises a radio frequency test loop and a grounding circuit, the radio frequency test loop is connected with the cantilever probe in the test head and the radio frequency tester, and the grounding circuit covers the radio frequency test loop.
Further, the radio frequency test loop comprises a zero ohm resistor, a first capacitor and a second capacitor, one end of a main line of the radio frequency test loop is connected with a cantilever probe in the test head, and after the zero ohm resistor, the other end of the main line is connected with the radio frequency tester;
a first branch line is also connected between the cantilever probe and the zero ohm resistor in the test head, the first capacitor is arranged on the first branch line, and the other end of the first branch line is grounded; and a second branch line is also connected between the zero European resistor and the radio frequency tester, the second capacitor is arranged on the second branch line, and the other end of the second branch line is grounded.
Further, the ground line comprises a grid ground and a ground line group, the grid ground covers the main line of the radio frequency test loop, the ground line group comprises a digital ground line and an analog ground line, and the grid ground is connected with the digital ground line and the analog ground line through at least one magnetic bead.
The radio frequency test loop can adjust the impedance of the cantilever probe loop in the test head, so that the output signal and the impedance of the output loop are consistent, the maximum transmission effect is achieved, and the reflection loss in the output loop is reduced to the minimum. The arrangement of the grid ground in the grounding circuit can reduce high-frequency interference, and the high-frequency interference is reduced by connecting the magnetic beads with the analog ground wire and the digital ground wire respectively.
Further, the protection assembly comprises a protection shell and a wave absorbing plate, the protection shell is arranged on the test head, and the protection shell corresponds to the positions and the numbers of all radio frequency chips to be tested in the radio frequency chip group to be tested;
the wave absorbing plate comprises a first wave absorbing plate and a second wave absorbing plate, the first wave absorbing plate is arranged at the gap position of the adjacent radio frequency chip to be tested, and the second wave absorbing plate is arranged on the test head corresponding to the gap position of the adjacent radio frequency chip to be tested;
when the radio frequency chip is tested, the protective shell and the second wave absorbing plate move along with the test head to the position of the radio frequency chip to be tested, and move to the position of the first wave absorbing plate to form a seal.
Further, the protective housing adopts flexible methyl silicone rubber material, and the appearance of protective housing is square annular, and the upper portion of protective housing is the ring structure, and the lower part is square columnar structure.
The protection component is arranged corresponding to each radio frequency chip to be tested, can form a closed test space with the radio frequency chip set to be tested along with the movement of the test head, shields external interference, and ensures the stability in the test process and the accuracy of the test result.
Further, at least two radio frequency chip sets to be tested are set according to the layout position of the radio frequency chip to be tested and the preset test interval distance, and the method specifically comprises the following steps:
performing position layout on each radio frequency chip to be tested, and giving the position distance between adjacent radio frequency chips to be tested;
providing a corresponding test interval distance by combining the radio frequency chip test mode;
determining the initial position of the radio frequency chip set to be tested based on the position distance between adjacent radio frequency chips to be tested;
and determining the radio frequency chip set to be tested by combining the starting position of the radio frequency chip set to be tested and the corresponding test interval distance.
Further, the position layout directions of the adjacent radio frequency chips to be tested are consistent, and the position distance of the adjacent radio frequency chips to be tested is the straight line distance of the centers of the adjacent radio frequency chips to be tested.
Further, the starting position of the radio frequency chip set to be tested and the corresponding test interval distance are combined to determine the radio frequency chip set to be tested, which is specifically expressed as:
；
wherein i is the number of the radio frequency chip groups to be tested, m is the number of the radio frequency chip groups to be tested, j is the number of a certain radio frequency chip of each radio frequency chip group to be tested,for the coordinate of the jth radio frequency chip to be tested in the ith radio frequency chip set to be tested, < + >>For the coordinates of the j+1th radio frequency chip to be tested in the ith radio frequency chip set to be tested,for the coordinate of the j-1 th radio frequency chip to be tested in the ith radio frequency chip set to be tested,/->The coordinate of the j radio frequency chip to be tested in the i-1 radio frequency chip set to be tested is +.>The coordinate of the j radio frequency chip to be tested in the i+1 radio frequency chip set to be tested is +.>Minimum spacing distance required for various radio frequency chip test modes, +.>Is the linear distance between the centers of adjacent radio frequency chips to be measured.
The radio frequency chip groups to be tested are set according to the layout of the radio frequency chips to be tested, and different radio frequency chip test modes are carried out aiming at each radio frequency chip group to be tested, so that the test efficiency of the radio frequency chips is improved on the basis of meeting test requirements and realizing and testing.
In a second aspect, the present invention further provides a system for testing a radio frequency chip, where the method for testing a radio frequency chip includes: the device comprises a radio frequency test circuit, a test head, a protection component and a control device;
the control device is used for setting at least two radio frequency chip sets to be tested according to the layout position of the radio frequency chips to be tested and a preset interval distance;
acquiring a plurality of radio frequency chip test modes, wherein the number of the radio frequency chip test modes is not less than the number of radio frequency chip groups to be tested;
and sequentially completing various radio frequency chip test modes in each radio frequency chip set to be tested, wherein the radio frequency chip test modes of each radio frequency chip set to be tested are different in each time frame.
The invention provides a method and a system for testing a radio frequency chip, which at least comprise the following beneficial effects:
(1) According to the invention, the radio frequency test circuit is optimized, the protection component in the test process is set, and the test sensitivity, the anti-interference capability, the precision and the test efficiency of the radio frequency chip are improved by combining the crossing and parallel test modes of various test modes.
(2) The radio frequency test loop provided by the invention can adjust the impedance of the cantilever probe loop in the test head, so that the output signal and the impedance of the output loop are consistent, the maximum transmission effect is achieved, and the reflection loss in the output loop is reduced to the minimum. The arrangement of the grid ground in the grounding circuit can reduce high-frequency interference, and the high-frequency interference is reduced by connecting the magnetic beads with the analog ground wire and the digital ground wire respectively.
(3) The protection component provided by the invention is arranged corresponding to each radio frequency chip to be tested, can form a closed test space with the radio frequency chip set to be tested along with the movement of the test head, shields external interference, and ensures the stability in the test process and the accuracy of the test result.
(4) According to the invention, the radio frequency chip sets to be tested are set according to the layout of the radio frequency chips to be tested, and different radio frequency chip test modes are carried out aiming at each radio frequency chip set to be tested, so that the test efficiency of the radio frequency chips is improved on the basis of meeting test requirements and realizing parallel testing.
Drawings
FIG. 1 is a schematic flow chart of a testing method of a radio frequency chip provided by the invention;
FIG. 2 is a schematic diagram of a RF test circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a RF test loop according to an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a protection component according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a protective case according to an embodiment of the present invention;
FIG. 6 is a schematic flow chart of setting up a radio frequency chip set to be tested according to a layout position of the radio frequency chip to be tested and a preset test interval distance according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a layout position of a radio frequency chip to be tested according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of a test system for a radio frequency chip according to the present invention.
Reference numerals illustrate:
the device comprises a 1-protection component, a 11-protection shell, a 12-wave absorbing plate, a 121-first wave absorbing plate, a 122-second wave absorbing plate, a 2-test head, a 21-cantilever probe, a 22-radio frequency tester, a 3-radio frequency test circuit, a 31-radio frequency test circuit, a 311-zero ohm resistor, a 312-first capacitor, a 313-second capacitor, a 32-grounding circuit, a 321-grid ground, a 322-ground wire group, a 3221-digital ground wire, a 3222-analog ground wire, a 323-magnetic bead, a 4-radio frequency chip to be tested and a 5-control device.
Detailed Description
In order to better understand the above technical solutions, the following detailed description will be given with reference to the accompanying drawings and specific embodiments. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such product or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a commodity or device comprising such element.
In general, site test areas of the radio frequency chip are relatively open, in order to avoid the influence of external radio frequency signals and the mutual influence among sites in the test process, a probe adopted in the test is a MEMS needle or a film probe with long processing period and high cost, a test mode is also a serial side mode, and the test efficiency is general and cannot meet the requirements of batch and rapid test.
When testing the type of radio frequency chip (such as the consumer IOT products) applied in some scenes, the testing efficiency and the anti-interference capability in the testing process and the testing cost need to be considered. Therefore, the system structure, the testing process and the layout of the radio frequency chip need to be adjusted and designed based on the existing ATE.
As shown in fig. 1, the invention provides a method for testing a radio frequency chip, which specifically includes the following steps:
a radio frequency test circuit is built in advance, and a protection assembly is built on a test head;
setting at least two radio frequency chip groups to be tested according to the layout positions of the radio frequency chips to be tested and a preset interval distance;
acquiring a plurality of radio frequency chip test modes, wherein the number of the radio frequency chip test modes is not less than the number of radio frequency chip groups to be tested;
and sequentially completing various radio frequency chip test modes in each radio frequency chip set to be tested, wherein the radio frequency chip test modes of each radio frequency chip set to be tested are different in each time frame.
According to the invention, the radio frequency test circuit is optimized, the protection component in the test process is set, and the test sensitivity, the anti-interference capability, the precision and the test efficiency of the radio frequency chip are improved by combining the crossing and parallel test modes of various test modes.
As shown in fig. 2-3, the radio frequency test circuit 3 includes a radio frequency test circuit 31 and a grounding circuit 32, the radio frequency test circuit 31 is connected with the cantilever probe 21 and the radio frequency tester 22 in the test head 2, and the grounding circuit 32 covers the radio frequency test circuit 31.
The radio frequency test loop is arranged between the cantilever probe and the radio frequency tester, so that the impedance of the cantilever probe loop can be adjusted to be consistent with the impedance of the output circuit, the maximum transmission efficiency is achieved, and the reflection loss of the cantilever probe loop is reduced to the minimum.
The radio frequency test loop 3 comprises a zero European resistor 311, a first capacitor 312 and a second capacitor 313, one end of a main line of the radio frequency test loop 3 is connected with the cantilever probe 21 in the test head 2, and after passing through the zero European resistor 311, the other end of the main line is connected with the radio frequency tester 22;
a first branch line is also connected between the cantilever probe 21 and the zero ohm resistor 311 in the test head 2, a first capacitor 312 is arranged on the first branch line, and the other end of the first branch line is grounded; a second branch line is also connected between the zero ohm resistor 311 and the radio frequency tester 22, and a second capacitor 313 is arranged on the second branch line, and the other end of the second branch line is grounded.
The radio frequency test loop is simple in structure, the working efficiency of the radio frequency tester can be improved by adjusting the impedance of the cantilever probe, so that the test requirement of a radio frequency product can be met when the cantilever probe is used for testing, and meanwhile, the purposes of short manufacturing period and low cost are realized based on the characteristics of the radio frequency test loop.
The zero ohm resistance in the main line, the first capacitance and the second capacitance in the first branch line and the second branch line all play a role in matching, and the impedance in the transmission of the cantilever probe and the radio frequency tester is adjusted.
The frequency, the first capacitor and the second capacitor of the radio frequency test loop are all variable, and the impedance of the two ends of the radio frequency test loop can be adjusted by changing the ratio of the first capacitor to the second capacitor.
The frequency of the radio frequency test loop is determined according to the actual application requirement, and the first capacitor and the second capacitor are also adjusted and determined according to the actual application (for example, a welded pad is reserved in the first branch line and the second branch line, and the welded capacitor can be added when the impedance is debugged), so that specific values are not further limited.
The ground line 32 includes a grid ground 321 and a ground line group 322, the grid ground 321 covers a main line of the radio frequency test circuit 31, the ground line group 322 includes a digital ground line (AGND) 3221 and an analog ground line (DGND) 3222, and the grid ground 321 is connected to the digital ground line 3221 and the analog ground line 3222 through at least one magnetic bead 323.
The grid ground is covered on the main line of the radio frequency test loop, so that the high-frequency interference generated by the outside can be reduced. The grid ground is connected to a digital ground (AGND) and an analog ground (DGND) through the magnetic beads, and when a high-frequency signal passes through the magnetic beads, electromagnetic interference is absorbed and converted into heat energy to be dissipated.
The radio frequency test loop provided by the invention can adjust the impedance of the cantilever probe loop in the test head, so that the output signal and the impedance of the output loop are consistent, the maximum transmission effect is achieved, and the reflection loss in the output loop is reduced to the minimum. The arrangement of the grid ground in the grounding circuit can reduce high-frequency interference, and the high-frequency interference is reduced by connecting the magnetic beads with the analog ground wire and the digital ground wire respectively.
For example, in one embodiment, the rf sensitivity is effectively improved by the arrangement of the rf test circuit, with a loss of <5dBm on the cantilever pin card.
As shown in fig. 4-5, the protection component 1 includes a protection shell 11 and a wave absorbing plate 12, the protection shell 11 is disposed on the test head 2, and the protection shell 11 corresponds to the positions and the numbers of the radio frequency chips to be tested in the radio frequency chip set to be tested;
the wave absorbing plate 12 comprises a first wave absorbing plate 121 and a second wave absorbing plate 122, the first wave absorbing plate 121 is arranged at the gap position of the adjacent radio frequency chip to be tested, and the second wave absorbing plate 122 is arranged on the test head 2 corresponding to the gap position of the adjacent radio frequency chip to be tested;
when the radio frequency chip to be tested is tested, the protective shell 11 and the second wave absorbing plate 122 move along with the test head 2 to the position of the radio frequency chip 4 to be tested, and move to the position of the first wave absorbing plate 121 to form a seal.
The absorbing wave plate adopts methyl silicone rubber particles as a medium base, and the material has the advantages of heat resistance, cold resistance, large elasticity, innocuity and the like, has wide applicable temperature range, has better ageing resistance and insulating property, and can play a good interference suppression role in the test of the radio frequency chip.
The protective housing adopts flexible material methyl silicone rubber as raw materials, and the appearance design is square cyclic annular. The cross-sectional structure of the protective shell and side view is shown in fig. 5. The side of protective housing is called "protruding" type, and the protective housing comprises the ring structure on upper portion and the square columnar structure of lower part.
In one embodiment, the upper ring thickness of the protective shell is 0.13 and mm, the ring structure on the top is in contact with the test head, and the test head is inserted into the cavity formed by the square columnar structure from the circular opening of the ring structure. The square columnar structure has the thickness of 2 mm, the height of 20mm and the side length of 24 mm, one side of the square columnar structure is connected with the circular ring structure, and the other side is contacted with the site area.
And a protective shell is arranged on the periphery of the position of the test head, corresponds to the positions and the number of each radio frequency chip to be tested in the radio frequency chip group to be tested, and rises and falls along with the test head in the process of moving up and down, and is matched with the upper part and the lower part of the wave absorbing plate and the site area when the test connection action is completed, so that a closed protective space is formed.
In order to meet the radio frequency test requirement, the wave absorbing capacity can be changed by adjusting the content of the methyl silicone rubber particles, for example, the size, the thickness and the like are adjusted, and the frequency point with the maximum wave absorbing capacity is found.
The protection component provided by the invention is arranged corresponding to each radio frequency chip to be tested, can form a closed test space with the radio frequency chip set to be tested along with the movement of the test head, shields external interference, and ensures the stability in the test process and the accuracy of the test result.
As shown in fig. 6, at least two radio frequency chip sets to be tested are set according to the layout position of the radio frequency chip to be tested and the preset test interval distance, and the method specifically includes the following steps:
performing position layout on each radio frequency chip to be tested, and giving the position distance between adjacent radio frequency chips to be tested;
providing a corresponding test interval distance by combining the radio frequency chip test mode;
determining the initial position of the radio frequency chip set to be tested based on the position distance between adjacent radio frequency chips to be tested;
and determining the radio frequency chip set to be tested by combining the starting position of the radio frequency chip set to be tested and the corresponding test interval distance.
In order to improve the testing efficiency of the radio frequency chip, the test of a plurality of chips is simultaneously carried out by carrying out mass production test, namely a multi-chip multi-site test mode. In addition, the radio frequency chip test mode is divided into a plurality of types, wherein the mutual interference between sites caused in the chip transmitting mode is most obvious. Therefore, the layout position and the test interval distance of the radio frequency chip to be tested need to consider the interference condition of the adjacent chip to be tested in each radio frequency chip test mode.
The position layout directions of the adjacent radio frequency chips to be tested are consistent, and the position distance of the adjacent radio frequency chips to be tested is the straight line distance of the centers of the adjacent radio frequency chips to be tested.
Combining the initial position of the radio frequency chip set to be tested and the corresponding test interval distance, determining the radio frequency chip set to be tested, wherein the specific representation is as follows:
；
wherein i is the number of the radio frequency chip groups to be tested, m is the number of the radio frequency chip groups to be tested, j is the number of a certain radio frequency chip of each radio frequency chip group to be tested,for the coordinate of the jth radio frequency chip to be tested in the ith radio frequency chip set to be tested, < + >>For the coordinates of the j+1th radio frequency chip to be tested in the ith radio frequency chip set to be tested,for the coordinate of the j-1 th radio frequency chip to be tested in the ith radio frequency chip set to be tested,/->The coordinate of the j radio frequency chip to be tested in the i-1 radio frequency chip set to be tested is +.>The coordinate of the j radio frequency chip to be tested in the i+1 radio frequency chip set to be tested is +.>Minimum spacing distance required for various radio frequency chip test modes, +.>Is the linear distance between the centers of adjacent radio frequency chips to be measured.
The radio frequency chip groups to be tested are set according to the layout of the radio frequency chips to be tested, and different radio frequency chip test modes are carried out aiming at each radio frequency chip group to be tested, so that the test efficiency of the radio frequency chips is improved on the basis of meeting test requirements and realizing and testing.
As shown in fig. 7, in a certain embodiment, the layout of the rf chips to be tested is in a 45 ° diagonal direction, and the rf chips to be tested are divided into 2 groups, which are respectively the first rf chip groups S to be tested 1 Second radio frequency chip set S to be tested 2 And each radio frequency chip group to be tested has 2 radio frequency chips to be tested, expressed as in a set way: s is S 1 =[S 1,1 ,S 1,2 ]，S 2 =[S 2,1 ,S 2,2 ]。S 1,1 And S is equal to 1,2 S and S 2,1 And S is equal to 2,2 The intervals between the two are all。
The radio frequency chip to be tested needs to be tested through two test modes of the radio frequency chip to be tested, wherein one is a chip emission mode, and the other is a DFT (reliability design) test mode. And the two radio frequency chip test modes to be tested and the two radio frequency chip groups to be tested are crossed and tested, so that when one group of the two radio frequency chip test modes is in a chip transmitting mode, the other group of the two radio frequency chip test modes is in a DFT test mode, and after one group of the two radio frequency chip test modes is in the chip transmitting mode, the other group of the two radio frequency chip test modes is changed into the DFT test mode, and the other group of the two radio frequency chip test modes is also in the DFT test mode and is changed into the chip transmitting mode.
In addition, the time required for testing the chip emission mode and the DFT (reliability design) test mode is relatively close, and the test is performed by the two radio frequency chip test modes to be tested, because of S 1,1 And S is equal to 1,2 S and S 2,1 And S is equal to 2,2 The interval between the two radio frequency chip sets can reduce the interference between sites to the minimum during testing, and simultaneously, two radio frequency chip sets to be tested simultaneously carry out different radio frequency chip testing modes to be tested, so that the testing efficiency is greatly improved.
As shown in fig. 8, the present invention further provides a system for testing a radio frequency chip, where the method for testing a radio frequency chip includes: the device comprises a radio frequency test circuit 3, a test head 2, a protection component 1 and a control device 5;
the control device 5 is used for setting at least two radio frequency chip sets to be tested according to the layout position and the preset interval distance of the radio frequency chips 4 to be tested;
acquiring a plurality of radio frequency chip test modes, wherein the number of the radio frequency chip test modes is not less than the number of radio frequency chip groups to be tested;
and sequentially completing various radio frequency chip test modes in each radio frequency chip set to be tested, wherein the radio frequency chip test modes of each radio frequency chip set to be tested are different in each time frame.
The invention provides a method and a system for testing a radio frequency chip, which at least comprise the following beneficial effects:
(1) According to the invention, the radio frequency test circuit is optimized, the protection component is arranged, and the test sensitivity, the anti-interference capability, the precision and the test efficiency of the radio frequency chip are improved by combining the test mode crossing and the parallel test mode.
(2) The radio frequency test loop provided by the invention can adjust the impedance of the cantilever probe loop in the test head, so that the output signal and the impedance of the output loop are consistent, the maximum transmission effect is achieved, and the reflection loss in the output loop is reduced to the minimum. The arrangement of the grid ground in the grounding circuit can reduce high-frequency interference, and the high-frequency interference is reduced by connecting the magnetic beads with the analog ground wire and the digital ground wire respectively.
(3) The protection component provided by the invention is arranged corresponding to each radio frequency chip to be tested, can form a closed test space with the radio frequency chip set to be tested along with the movement of the test head, shields external interference, and ensures the stability in the test process and the accuracy of the test result.
(4) According to the invention, the radio frequency chip sets to be tested are set according to the layout of the radio frequency chips to be tested, and different radio frequency chip test modes are carried out aiming at each radio frequency chip set to be tested, so that the test efficiency of the radio frequency chips is improved on the basis of meeting test requirements and realizing parallel testing.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. The test method of the radio frequency chip is characterized by comprising the following steps of:
a radio frequency test circuit is built in advance, and a protection assembly is built on a test head;
setting at least two radio frequency chip groups to be tested according to the layout positions of the radio frequency chips to be tested and a preset interval distance;
acquiring a plurality of radio frequency chip test modes, wherein the number of the radio frequency chip test modes is not less than the number of radio frequency chip groups to be tested;
and sequentially completing various radio frequency chip test modes in each radio frequency chip set to be tested, wherein the radio frequency chip test modes of each radio frequency chip set to be tested are different in each time frame.
2. The method of claim 1, wherein the radio frequency test circuit comprises a radio frequency test loop and a ground line, the radio frequency test loop being connected to the cantilever probe in the test head and the radio frequency tester, the ground line covering the radio frequency test loop.
3. The method of testing a radio frequency chip according to claim 2, wherein the radio frequency test loop comprises a zero ohm resistor, a first capacitor and a second capacitor, wherein one end of a main line of the radio frequency test loop is connected with a cantilever probe in the test head, and after passing through the zero ohm resistor, the other end of the main line is connected with the radio frequency tester;
a first branch line is also connected between the cantilever probe and the zero ohm resistor in the test head, the first capacitor is arranged on the first branch line, and the other end of the first branch line is grounded; and a second branch line is also connected between the zero European resistor and the radio frequency tester, the second capacitor is arranged on the second branch line, and the other end of the second branch line is grounded.
4. The method of testing a radio frequency chip according to claim 3, wherein the ground line comprises a grid ground and a ground line group, the grid ground covers a main line of the radio frequency test circuit, the ground line group comprises a digital ground and an analog ground, and the grid ground is connected with the digital ground and the analog ground through at least one magnetic bead.
5. The method for testing the radio frequency chips according to claim 1, wherein the protective assembly comprises a protective shell and a wave absorbing plate, the protective shell is arranged on the test head, and the protective shell corresponds to the positions and the numbers of the radio frequency chips to be tested in the radio frequency chip set to be tested;
the wave absorbing plate comprises a first wave absorbing plate and a second wave absorbing plate, the first wave absorbing plate is arranged at the gap position of the adjacent radio frequency chip to be tested, and the second wave absorbing plate is arranged on the test head corresponding to the gap position of the adjacent radio frequency chip to be tested;
when the radio frequency chip is tested, the protective shell and the second wave absorbing plate move along with the test head to the position of the radio frequency chip to be tested, and move to the position of the first wave absorbing plate to form a seal.
6. The method of testing a radio frequency chip according to claim 5, wherein the protective housing is made of flexible methyl silicone rubber material, the protective housing is square annular in shape, the upper portion of the protective housing is of a circular ring structure, and the lower portion of the protective housing is of a square columnar structure.
7. The method for testing a radio frequency chip according to claim 1, wherein at least two radio frequency chip sets to be tested are set according to layout positions of the radio frequency chips to be tested and a preset test interval distance, and the method specifically comprises the following steps:
performing position layout on each radio frequency chip to be tested, and giving the position distance between adjacent radio frequency chips to be tested;
providing a corresponding test interval distance by combining the radio frequency chip test mode;
determining the initial position of the radio frequency chip set to be tested based on the position distance between adjacent radio frequency chips to be tested;
and determining the radio frequency chip set to be tested by combining the starting position of the radio frequency chip set to be tested and the corresponding test interval distance.
8. The method for testing a radio frequency chip according to claim 7, wherein the adjacent radio frequency chips to be tested are arranged in a consistent direction, and the distance between the adjacent radio frequency chips to be tested is a straight line distance between centers of the adjacent radio frequency chips to be tested.
9. The method for testing a radio frequency chip according to claim 8, wherein determining the radio frequency chip set to be tested by combining the starting position of the radio frequency chip set to be tested and the corresponding test interval distance is specifically expressed as:
；
wherein i is the number of the radio frequency chip groups to be tested, m is the number of the radio frequency chip groups to be tested, j is the number of a certain radio frequency chip of each radio frequency chip group to be tested,for the coordinate of the jth radio frequency chip to be tested in the ith radio frequency chip set to be tested, < + >>For the coordinates of the (j+1) th radio frequency chip to be tested in the (i) th radio frequency chip set to be tested,/->For the coordinate of the j-1 th radio frequency chip to be tested in the ith radio frequency chip set to be tested,/->The coordinate of the j radio frequency chip to be tested in the i-1 radio frequency chip set to be tested is +.>The coordinate of the j radio frequency chip to be tested in the i+1 radio frequency chip set to be tested is +.>Minimum spacing distance required for various radio frequency chip test modes, +.>Is the linear distance between the centers of adjacent radio frequency chips to be measured.
10. A system for testing a radio frequency chip, wherein a method for testing a radio frequency chip according to any one of claims 1 to 9 is used, comprising: the device comprises a radio frequency test circuit, a test head, a protection component and a control device;
the control device is used for setting at least two radio frequency chip sets to be tested according to the layout position of the radio frequency chips to be tested and a preset interval distance;
acquiring a plurality of radio frequency chip test modes, wherein the number of the radio frequency chip test modes is not less than the number of radio frequency chip groups to be tested;
and sequentially completing various radio frequency chip test modes in each radio frequency chip set to be tested, wherein the radio frequency chip test modes of each radio frequency chip set to be tested are different in each time frame.
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| CN202410026408.XA CN117538736A (en) | 2024-01-09 | 2024-01-09 | Method and system for testing radio frequency chip |
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