CN207834270U - 一种封装结构 - Google Patents

一种封装结构 Download PDF

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Publication number
CN207834270U
CN207834270U CN201721874408.7U CN201721874408U CN207834270U CN 207834270 U CN207834270 U CN 207834270U CN 201721874408 U CN201721874408 U CN 201721874408U CN 207834270 U CN207834270 U CN 207834270U
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encapsulating structure
metallic circuit
superstructure
chip
substructure
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CN201721874408.7U
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张江华
沈锦新
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JCET Group Co Ltd
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Jiangsu Changjiang Electronics Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型涉及的一种封装结构,一种封装结构包括金属线路、芯片、焊线;芯片周围设置有金属线路,所述金属线路包括上部结构和下部结构,所述下部结构呈柱状,所述上部结构呈蘑菇形状。本实用新型利用单次贴膜和电镀形成具有蘑菇形状的线路,缩小半导体封装结构的尺寸,提高线路和塑封料之间的结合性能。

Description

一种封装结构
技术领域
本实用新型涉及半导体封装技术领域,尤其涉及一种封装结构。
背景技术
随着电子产品如手机、笔记本电脑等朝着小型化、便携式、超薄化、多媒体以及满足大众化所需要的低成本方向发展,传统以引线框架作为承载件的半导体的封装的形态种类虽然繁多,但是传统的引线框往往因为厚度的限制,无法进一步的缩小封装件的整体高度。
因此发展出一种无承载板的半导体封装结构,该封装结构首先在一承载板上电镀一层金属形成超薄的线路,然后在线路上设置芯片并进行焊线连接,再进行包封形成封装胶体,最后移除承载板将线路露出,可以在露出表面刷上焊锡材料形成焊锡接点和外界PCB板电性连接。该封装结构较传统框架结构厚度超薄,但是此结构的金属层较薄,焊线的时候焊点处容易对金属层造成损伤,另外金属层没有任何支撑,仅靠塑封料包封,若塑封料和金属层结合不好,金属层容易翘起与塑封料剥离,影响产品良率和可靠性。
实用新型内容
本实用新型的目的在于克服上述不足,提供一种封装结构,缩小半导体封装结构的尺寸,提高线路和塑封料之间的结合性能。
本实用新型的目的是这样实现的:
本实用新型提供一种封装结构,包括金属线路、芯片、焊线;芯片周围设置有金属线路,所述金属线路包括上部结构和下部结构,所述下部结构呈柱状,所述上部结构呈蘑菇形状。
其中,所述芯片通过焊线与金属线路连接。
一种封装结构,所述金属线路的上部结构与下部结构材质相同,材质可以是镍、金、铜、银中的一种。
一种封装结构,所述金属线路的上部结构与下部结构材质不同,两者材质的组合可以是镍与金、镍与铜。
一种封装结构,所述芯片内凹进封装结构,且封装结构底部露出芯片背面。
一种封装结构,所述芯片下方设置基岛。
与现有技术相比,本实用新型的有益效果是:
1、金属线路层电镀形成,金属层的表面形成蘑菇头状,可以在保证降低半导体封装结构的厚度的同时,增加金属线路与塑封料之间的结合性。
2、电镀贴膜仅需一次,不需要常规的电镀研磨平整的工艺步骤,简化工艺以及降低生产成本,且金属线路层可以灵活设计,不限制线路密度,可适合多种类型的封装结构。
附图说明
图1为本实用新型实施例1的结构示意图。
图2为本实用新型实施例2的结构示意图。
图3为本实用新型实施例3的结构示意图。
其中:
下部结构4、上部结构5、芯片6、焊线7、基岛8、金属线路9。
具体实施方式
实施例1:
参见图1,本实用新型涉及的一种封装结构,封装结构包括金属线路9、芯片6、焊线7;芯片6周围设置有金属线路9,所述金属线路9包括上部结构5和下部结构4,所述下部结构4呈柱状,所述上部结构5呈蘑菇形状。
所述金属线路的上部结构与下部结构材质相同,材质可以是镍、金、铜、银中的一种。
所述金属线路的上部结构与下部结构材质不同,两者材质的组合可以是镍与金、镍与铜。
实施例2:
参见图2,本实用新型涉及的一种封装结构,芯片6内凹进封装结构,且封装结构底部露出芯片6背面,其余结构与实施例1相同。
实施例3:
参见图3,本实用新型涉及的一种封装结构,在芯片6下方设置基岛8,其余结构与实施例1相同。
以上仅是本实用新型的具体应用范例,对本实用新型的保护范围不构成任何限制。凡采用等同变换或者等效替换而形成的技术方案,均落在本实用新型权利保护范围之内。

Claims (5)

1.一种封装结构,其特征在于:它包括金属线路、芯片、焊线;芯片周围设置有金属线路,所述金属线路包括上部结构和下部结构,所述下部结构呈柱状,所述上部结构呈蘑菇形状。
2.根据权利要求1所述的一种封装结构,其特征在于:所述金属线路的上部结构与下部结构材质相同,材质可以是镍、金、铜、银中的一种。
3.根据权利要求1所述的一种封装结构,其特征在于:所述金属线路的上部结构与下部结构材质不同,两者材质的组合可以是镍与金、镍与铜。
4.根据权利要求1所述的一种封装结构,其特征在于:所述芯片内凹进封装结构,且封装结构底部露出芯片背面。
5.根据权利要求1所述的一种封装结构,其特征在于:所述芯片下方设置基岛。
CN201721874408.7U 2017-12-28 2017-12-28 一种封装结构 Active CN207834270U (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108183091A (zh) * 2017-12-28 2018-06-19 江苏长电科技股份有限公司 一种封装结构及其工艺方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108183091A (zh) * 2017-12-28 2018-06-19 江苏长电科技股份有限公司 一种封装结构及其工艺方法

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