CN101937886B - 薄型芯片封装结构及方法 - Google Patents

薄型芯片封装结构及方法 Download PDF

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CN101937886B
CN101937886B CN2009101085612A CN200910108561A CN101937886B CN 101937886 B CN101937886 B CN 101937886B CN 2009101085612 A CN2009101085612 A CN 2009101085612A CN 200910108561 A CN200910108561 A CN 200910108561A CN 101937886 B CN101937886 B CN 101937886B
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golden finger
power
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metallic circuit
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CN101937886A (zh
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傅敬尧
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- Core Of Electronic Science And Technology (zhongshan) Co Ltd
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AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
Hon Hai Precision Industry Co Ltd
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Abstract

一种薄型芯片封装结构，包括塑封胶体、金手指、金属线路、芯片及绝缘层。其中，塑封胶体用于封装金手指、金属线路及芯片，覆盖及固定上述元件。金手指封装于塑封胶体中，且其一面暴露于塑封胶体底部，其包括接地端、电源端及至少一个信号端。金属线路封装于塑封胶体中，其包括接地线路及电源线路，分别连接于金手指的接地端及电源端。芯片封装于塑封胶体中，通过金线与所述金手指及金属线路相连，其包括接地引脚、电源引脚及信号引脚。绝缘层，用于覆盖塑封胶体底部除金手指外的其他区域。本发明提出的薄型芯片封装结构及方法，通过电镀金属线路代替基板上的线路，并利用绝缘层代替基板，缩小了芯片封装的体积，降低了成本。

Description

薄型芯片封装结构及方法
技术领域
本发明涉及半导体封装技术，特别涉及一种薄型芯片封装结构及方法。
背景技术
随着便携式电子产品的功能日益丰富，其使用的芯片数量越来越大，而便携式电子产品小型化是主要发展趋势，因此需缩小芯片封装体积，以满足市场需求。
发明内容
有鉴于此，需提供一种薄型芯片封装结构，利用绝缘层代替基板，减少封装体积，并降低成本。
同时，还需提供一种薄型芯片封装方法。
本发明实施方式中的薄型芯片封装结构，包括塑封胶体、金手指、金属线路、芯片及绝缘层。其中，塑封胶体用于封装金手指、金属线路及芯片，覆盖及固定上述元件。金手指封装于塑封胶体中，且其一面暴露于塑封胶体底部，其包括接地端、电源端及至少一个信号端。金属线路封装于塑封胶体中，包括接地线路及电源线路，分别连接于金手指的接地端及电源端。芯片封装于塑封胶体中，通过金线与所述金手指及金属线路相连，所述芯片包括接地引脚、电源引脚及信号引脚。绝缘层，用于覆盖塑封胶体底部除金手指外的其他区域。
本发明实施方式中的薄型芯片封装方法，包括以下步骤：电镀：在载板上电镀金属线路，所述金属线路包括接地线路及电源线路；置晶：将金手指、芯片放置于所述载板上，其中，所述金手指包括接地端、电源端及至少一个信号端，所述芯片包括接地引脚、电源引脚及信号引脚；打线：通过金线将所述芯片与所述金手指及金属线路相连，其中，所述金手指的接地端及电源端分别连接于所述金属线路的接地线路及电源线路；封装：用塑封胶体将所述金手指、金属线路、芯片及金线进行封装以形成封装体；分离：将所述封装体与所述载板分离；及印刷：在所述封装体底部除所述金手指外的区域涂覆绝缘层。
本发明提出的薄型芯片封装结构及方法，通过电镀金属线路代替基板上的线路，并利用绝缘层代替基板，缩小了芯片封装的体积，降低了成本。
附图说明
图1A为本发明提出的薄型芯片封装结构的一种实施方式的示意图；
图1B为本发明提出的图1A中薄型芯片封装结构沿方向A的剖面图；
图2为本发明提出的薄型芯片封装方法的一种实施方式的流程图。
具体实施方式
图1A及图1B分别为本发明提出的薄型芯片封装结构的一种实施方式的平面图及剖面图。本实施方式中，薄型芯片封装结构包括塑封胶体10、金手指20、金属线路30、芯片40及绝缘层60。其中，塑封胶体10用于封装金手指20、金属线路30及芯片40，覆盖及固定上述元件。本实施方式中，塑封胶体10的材质为环氧树脂。金手指20封装于塑封胶体10中，且其一面暴露于塑封胶体10底部。金手指20包括接地端21、电源端22及至少一个信号端23。金属线路30封装于塑封胶体10中，其可由铜、钢及其他导电金属构成。在本实施方式中，金属线路30包括接地线路31及电源线路32，分别连接于金手指20中的接地端21和电源端22。在其他实施方式中，金属线路30还包括至少一条信号线路，与金手指20中的信号端23相连。芯片40封装于塑封胶体10中，其接地引脚41及电源引脚42分别通过金线50与金属线路30接地线路31及电源线路32相连，芯片40的信号引脚43通过金线50与金手指20的信号端23相连。在其他实施方式中，芯片40的信号引脚43也可以通过金线50与金属线路30的信号线路相连，再连接至金手指的信号端23。绝缘层10用于覆盖塑封胶体10底部除金手指20外的区域，其可以由绝缘材料构成，如油墨。
图2为本发明提出的薄型芯片封装方法的一种实施方式的流程图。
步骤210，电镀：在载板上电镀金属线路30。在本实施方式中，金属线路30包括接地线路31及电源线路32。在其他实施方式中，金属线路30还包括至少一条信号线路。其中，金属线路30可以由铜、钢或其他导电金属构成。
步骤220，置晶：将金手指20、芯片40放置于载板上。
步骤230，打线：通过金线50将金手指20、金属线路30、芯片40电性连接。在本实施方式中，金属线路30的接地线路31及电源线路32分别连接于金手指20中的接地端21和电源端22。芯片40的接地引脚41及电源引脚42分别连接于金属线路30的接地线路31及电源线路32，信号引脚43连接于金手指20的信号端23。在其他实施方式中，芯片40的信号引脚43也可以通过金线50与金属30的信号线路相连，再连接至金手指20的信号端。
步骤240，封装：用塑封胶体10将金手指20、金属线路30、芯片40及金线50进行封装以形成封装体。本实施方式，塑封胶体10的材质为环氧树脂。
步骤250，分离：将封装体与载板分离。
步骤260，印刷：在封装体底部除金手指20外的区域涂覆绝缘层60，避免金属线路30及芯片40外露。绝缘层60由绝缘材料构成，如油墨。
本发明提出的薄型芯片封装结构及方法，通过电镀金属线路代替基板上的线路，并利用绝缘层代替基板，缩小了芯片封装的体积，降低了成本。

Claims (10)

1.一种薄型芯片封装结构，其特征在于，包括：
塑封胶体；
金手指，封装于所述塑封胶体中，且其一面暴露于所述塑封胶体底部，其中，所述金手指包括接地端、电源端及至少一个信号端；
金属线路，封装于所述塑封胶体中，其包括接地线路及电源线路，分别连接于所述金手指的接地端及电源端；
芯片，封装于所述塑封胶体中，通过金线与所述金手指及金属线路相连，所述芯片包括接地引脚、电源引脚及信号引脚；及
绝缘层，用于覆盖所述塑封胶体底部除金手指外的其他区域。
2.如权利要求1所述的薄型芯片封装结构，其特征在于，所述绝缘层由油墨构成。
3.如权利要求1所述的薄型芯片封装结构，其特征在于，所述芯片的接地引脚及电源引脚分别与所述金属线路的接地线路及电源线路相连，所述信号引脚与所述金手指的信号端相连。
4.如权利要求1所述的薄型芯片封装结构，其特征在于，所述金属线路还包括至少一条信号线路，与所述金手指的信号端相连。
5.如权利要求4所述的薄型芯片封装结构，其特征在于，所述芯片的接地引脚及电源引脚分别与所述金属线路的接地线路及电源线路相连，所述信号引脚与所述金属线路的信号线路相连。
6.一种薄型芯片封装方法，其特征在于，包括以下步骤：
电镀：在载板上电镀金属线路，所述金属线路包括接地线路及电源线路；
置晶：将金手指、芯片放置于所述载板上，其中，所述金手指包括接地端、电源端及至少一个信号端，所述芯片包括接地引脚、电源引脚及信号引脚；
打线：通过金线将所述芯片与所述金手指及金属线路相连，其中，所述金手指的接地端及电源端分别连接于所述金属线路的接地线路及电源线路；
封装：用塑封胶体将所述金手指、金属线路、芯片及金线进行封装以形成封装体；
分离：将所述封装体与所述载板分离；及
印刷：在所述封装体底部除所述金手指外的区域涂覆绝缘层。
7.如权利要求6所述的薄型芯片封装方法，其特征在于，所述绝缘层由油墨构成。
8.如权利要求6所述的薄型芯片封装方法，其特征在于，所述芯片的接地引脚及电源引脚分别与所述金属线路的接地线路及电源线路相连，所述信号引脚与所述金手指的信号端相连。
9.如权利要求6所述的薄型芯片封装方法，其特征在于，所述金属线路还包括至少一条信号线路，与所述金手指的信号端相连。
10.如权利要求9所述的薄型芯片封装方法，其特征在于，所述芯片的接地引脚及电源引脚分别与所述金属线路的接地线路及电源线路相连，所述信号引脚与所述金属线路的信号线路相连。
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TWI600351B (zh) * 2016-03-18 2017-09-21 慧榮科技股份有限公司 印刷電路板以及元件製造方法
CN108492919B (zh) * 2018-03-01 2020-05-26 海信视像科技股份有限公司 电视机、柔性扁平线缆及其制作方法
CN113471164B (zh) * 2021-06-28 2023-09-08 江西晶浩光学有限公司 芯片封装结构、摄像头模组及电子设备
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6477046B1 (en) * 1997-05-09 2002-11-05 Texas Instruments Incorporated Ball grid array package and method using enhanced power and ground distribution circuitry
US7122406B1 (en) * 2004-01-02 2006-10-17 Gem Services, Inc. Semiconductor device package diepad having features formed by electroplating
CN101192275A (zh) * 2006-11-28 2008-06-04 卓恩民 记忆卡封装结构及其制作方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6084777A (en) * 1997-04-23 2000-07-04 Texas Instruments Incorporated Ball grid array package
US5895967A (en) * 1997-07-07 1999-04-20 Texas Instruments Incorporated Ball grid array package having a deformable metal layer and method
US7129572B2 (en) * 2004-08-18 2006-10-31 Chung-Cheng Wang Submember mounted on a chip of electrical device for electrical connection
TW200814249A (en) * 2006-09-12 2008-03-16 Chipmos Technologies Inc Stacked chip package structure with lead-frame having bus bar
US20080079150A1 (en) * 2006-09-28 2008-04-03 Juergen Simon Die arrangement and method for producing a die arrangement
CN100555592C (zh) * 2007-02-08 2009-10-28 百慕达南茂科技股份有限公司 芯片封装结构及其制作方法
TWI406370B (zh) * 2009-04-06 2013-08-21 Phison Electronics Corp 微型快閃記憶體儲存裝置
US8810015B2 (en) * 2009-06-14 2014-08-19 STAT ChipPAC Ltd. Integrated circuit packaging system with high lead count and method of manufacture thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6477046B1 (en) * 1997-05-09 2002-11-05 Texas Instruments Incorporated Ball grid array package and method using enhanced power and ground distribution circuitry
US7122406B1 (en) * 2004-01-02 2006-10-17 Gem Services, Inc. Semiconductor device package diepad having features formed by electroplating
CN101192275A (zh) * 2006-11-28 2008-06-04 卓恩民 记忆卡封装结构及其制作方法

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