CN207624704U - Insulated gate bipolar transistor - Google Patents
Insulated gate bipolar transistor Download PDFInfo
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- CN207624704U CN207624704U CN201721830403.4U CN201721830403U CN207624704U CN 207624704 U CN207624704 U CN 207624704U CN 201721830403 U CN201721830403 U CN 201721830403U CN 207624704 U CN207624704 U CN 207624704U
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- 230000000694 effects Effects 0.000 abstract description 19
- 238000002347 injection Methods 0.000 abstract description 8
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- 239000004065 semiconductor Substances 0.000 abstract description 8
- 230000000903 blocking effect Effects 0.000 abstract description 2
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- 239000012535 impurity Substances 0.000 description 2
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Abstract
The application provides an insulated gate bipolar transistor, relates to the semiconductor device field, includes: the device comprises an N + emitter and a Pwell region, wherein the Pwell region is positioned below the N + emitter, and a first grooved gate and a second grooved gate are arranged in the Pwell region; an N drift region located below the Pwell region; a carrier storage layer located below the Pwell region, the carrier storage layer being disposed between the first and second trenched gates; a P injection layer located below the first and second trenched gates; and introducing a hole blocking structure of Schottky contact in the region without round cells. The technical problem that after the technical concentration of a current carrier storage layer of the insulated gate bipolar transistor in the prior art is improved, the withstand voltage of the insulated gate bipolar transistor is reduced is solved, the original withstand voltage capability can be maintained while the conduction voltage drop is greatly reduced, and therefore the technical effect of comprehensively improving various parameter capabilities of the device is achieved.
Description
Technical field
The utility model is related to field of semiconductor devices, more particularly to a kind of igbt.
Background technology
Igbt is one of current high pressure, high current field core power semiconductor devices.In order to continuous
Improve device property, realize the optimal parameter performance of device, it is most important optimization effort to reduce break-over of device state saturation voltage drop
One of direction.
But the application utility model people is during the implementation of the utility model technical solution in the embodiments of the present application, in discovery
Technology is stated at least to have the following technical problems：
After igbt carrier accumulation layer technology concentration in the prior art improves, lead to insulated gate bipolar
Transistor reduces pressure.
Utility model content
The embodiment of the present application solves insulated gate bipolar in the prior art by providing a kind of igbt
After transistor carrier accumulation layer technology concentration improves, the technical issues of causing igbt to reduce pressure, reach
Conduction voltage drop is being greatly lowered meanwhile, it is capable to maintain original voltage endurance capability, to the parameters of General Promotion device
The technique effect of ability.
In view of the above problems, it is proposed that the embodiment of the present application is double in order to provide a kind of a kind of insulated gate overcoming the above problem
Gated transistors, including：N+ emitters, the regions Pwell, the regions Pwell are located at the lower section of the N+ emitters, wherein institute
It states and is provided with the first slot grid and the second slot grid in the regions Pwell；The drift regions N, the drift regions N are located at the regions Pwell
Lower section；Carrier accumulation layer, the carrier accumulation layer are located at the lower section in the regions Pwell, and, the carrier accumulation layer
It is arranged between the first slot grid and the second slot grid；P implanted layers, the P implanted layers are located at the first slot grid and institute
State the lower section of the second slot grid, wherein the transistor further includes：In the hole barrier knot for introducing Schottky contacts without circle born of the same parents region
Structure.
Preferably, the transistor further includes：The P implanted layers form ground potential.
Preferably, the transistor further includes：The Schottky contacts are connect with the metal of N+ emitters, form ground connection.
Preferably, the transistor further includes：Described without in N+ emitters corresponding to circle born of the same parents region, the N+ emitters
Including the first oxide layer and the second oxide layer, wherein be and the Schottky between first oxide layer and the second oxide layer
The metal of contact.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages：
1. a kind of igbt provided by the embodiments of the present application, by N+ emitters, the regions Pwell are described
The regions Pwell are located at the lower section of the N+ emitters, wherein being provided with the first slot grid and the second slot grid in the regions Pwell；N
Drift region, the drift regions N are located at the lower section in the regions Pwell；Carrier accumulation layer, the carrier accumulation layer are located at institute
The lower section in the regions Pwell is stated, and, the carrier accumulation layer is arranged between the first slot grid and the second slot grid；P is noted
Enter layer, the P implanted layers are located at the lower section of the first slot grid and the second slot grid, wherein the transistor further includes：
In the hole barrier structure for introducing Schottky contacts without circle born of the same parents region.It solves igbt in the prior art to carry
The technical issues of flowing after sub- accumulation layer technology concentration improves, igbt is caused to reduce pressure, has reached substantially
Degree reduces conduction voltage drop meanwhile, it is capable to maintain original voltage endurance capability, to the skill of the parameters ability of General Promotion device
Art effect.
2. the embodiment of the present application forms ground potential by the P implanted layers, further reach to high concentration N-type current-carrying
Sub- accumulation layer realizes shield effectiveness, therefore need not also select excessively high P injection zone concentration, will not be brought to electron injection
The technique effect of influence.
The above description is merely an outline of the technical solution of the present invention, in order to better understand the skill of the utility model
Art means, and being implemented in accordance with the contents of the specification, and in order to allow above and other purpose, feature of the utility model
It can be clearer and more comprehensible with advantage, it is special below to lift specific embodiment of the present utility model.
Description of the drawings
In order to illustrate the embodiment of the utility model or the technical proposal in the existing technology more clearly, below will be to embodiment
Or attached drawing needed to be used in the description of the prior art is briefly described, it should be apparent that, the accompanying drawings in the following description is
Some embodiments of the utility model, for those of ordinary skill in the art, without creative efforts,
Other drawings may also be obtained based on these drawings.
Fig. 1 is a kind of structural schematic diagram of igbt provided by the embodiments of the present application.
Drawing reference numeral explanation：N+ emitters 1, the first oxide layer 11, the second oxide layer 12, the regions Pwell 2, the first slot grid
21, the second slot grid 22, the drift regions N 3, carrier accumulation layer 4, P implanted layers 5, hole barrier structure 6.
Specific implementation mode
It is brilliant to solve insulated gate bipolar in the prior art for a kind of igbt provided by the embodiments of the present application
After body pipe carrier accumulation layer technology concentration improves, the technical issues of causing igbt to reduce pressure.
Technical solution in the embodiment of the present application, group method are as follows：By N+ emitters, the regions Pwell are described
The regions Pwell are located at the lower section of the N+ emitters, wherein being provided with the first slot grid and the second slot grid in the regions Pwell；N
Drift region, the drift regions N are located at the lower section in the regions Pwell；Carrier accumulation layer, the carrier accumulation layer are located at institute
The lower section in the regions Pwell is stated, and, the carrier accumulation layer is arranged between the first slot grid and the second slot grid；P is noted
Enter layer, the P implanted layers are located at the lower section of the first slot grid and the second slot grid, wherein the transistor further includes：
The hole barrier structure of Schottky contacts is introduced without circle born of the same parents region.Reach and conduction voltage drop is being greatly lowered meanwhile, it is capable to tie up
Original voltage endurance capability is held, to the technique effect of the parameters ability of General Promotion device.
The exemplary embodiment of the disclosure will be described in detail belows.Although this application discloses one or more of exemplary
Embodiment, it being understood, however, that may be realized in various forms the disclosure without should be limited by embodiments set forth here.Phase
Instead, these embodiments are provided to facilitate a more thoroughly understanding of the present invention, and can completely pass the scope of the present disclosure
Up to those skilled in the art.
Embodiment one
A kind of igbt provided by the embodiments of the present application, igbt (Insulate-
Gate Bipolar Transistor-IGBT) abbreviation IGBT, combine power transistor (Giant Transistor-GTR)
The advantages of with electric power field-effect transistor (Power MOSFET), has good characteristic, application field very extensive；IGBT is also
Three terminal device:Grid, collector and emitter.IGBT is MOS structure bipolar device, belongs to the high speed with power MOSFET
The power device of performance and bipolar low resistive energy.The application range of IGBT generally all pressure-resistant 600V or more, electric current 10A with
Upper, frequency is the region of 1kHz or more.It uses in industrial motor, civilian small-capacity motor, converter (inverter), photograph more
The fields such as stroboscope, sensing heating (Induct ionHeating) electric cooker of machine.As shown in Figure 1, the transistor packet
It includes：
N+ emitters 1；
Specifically, N+ emitters 1, the drift region Pwell2, N 3 form field-effect tube (Field Effect
Transistor abridges (FET).IGBT structure increases P+ structures in bottom, realizes hole injection, forms two kinds of polar current-carrying
Son conducting, the i.e. minority carrier (hole) of majority carrier (electronics) and reversed polarity participate in conduction, because of referred to herein as ambipolar crystalline substance
Body pipe, and electronic conduction is controlled by grid, therefore referred to as igbt (Insulate-Gate Bipolar
Transistor-IGBT)。
The regions Pwell 2, the regions Pwell 2 are located at the lower section of the N+ emitters 1, wherein the regions Pwell 2
In be provided with the first slot grid 21 and the second slot grid 22；
Specifically, the regions Pwell 2 are p-well region, semiconductor generally can be divided into intrinsic semiconductor, N-type semiconductor
And P-type semiconductor respectively represents free from admixture doping, doped N-type impurity (P, As) and doped p-type impurity (B, Ga) if is in N
P type island region is spread on type substrate, is just called p-well region；If spreading N-type region in P type substrate, just it is called N well regions；The Pwell
Region 2 is located at the lower section of the N+ emitters 1, wherein is internally provided with 21 He of the first slot grid in the regions Pwell 2
Second slot grid 22, due to igbt provided by the embodiments of the present application be based on using carrier accumulation layer structure and
What the groove gate type igbt of P injecting structures was completed, so, igbt provided by the present application
The first slot grid 21 and the second slot grid 22 are provided in the regions Pwell 2.
The drift regions N 3, the drift regions N 3 are located at the lower section in the regions Pwell 2；
Specifically, the carrier properties and concentration due to p type island region and N-type region both sides are all different, the hole of p type island region is dense
Degree is big, and the electron concentration of N-type region is big, and diffusion motion is then produced at interface.The hole of p type island region is expanded to N-type region
It dissipates, it is negatively charged because losing hole；And the electronics of N-type region is spread to p type island region, it is positively charged because losing electronics, in this way in the areas P and
The intersection in the areas N forms an electric field (being known as internal electric field).Under the action of internal electric field, electronics will drift about from the areas P to the areas N
Movement, drift motion is then made in hole from the areas N to the areas P.The region that drift motion is carried out in electronics is referred to as drift region, the N drifts
Move the lower section that area 3 is located at the regions Pwell 2.The low-doped drift regions N are mainly used for supporting high voltage in IGBT structure,
Conductance modulation effect is formed since carrier largely injects when conducting, so as to reduce conduction voltage drop.
Carrier accumulation layer 4, the carrier accumulation layer 4 are located at the lower section in the regions Pwell 2, and, the carrier
Accumulation layer 4 is arranged between the first slot grid 21 and the second slot grid 22；
Specifically, electrical current carriers, claim carrier.In physics, carrier, which refers to, free-moving to carry charge
Corpuscle, such as electronics and ion.In semiconductor physics, electronics loss causes the vacancy left on covalent bond to be considered as
Carrier.By injecting certain density N-type carrier accumulation layer below the regions Pwell 2, and, the carrier is deposited
Reservoir 4 is arranged between the first slot grid 21 and the second slot grid 22, stops hole flow when conducting state, this side
Method can realize preferable conductance modulation effect, reduce break-over of device state saturation voltage drop.
P implanted layers 5, the P implanted layers 5 are located at the lower section of the first slot grid 21 and the second slot grid 22, the P notes
Enter layer and forms ground potential.
Specifically, being injected separately into P in the lower section of the first slot grid 21 and the second slot grid 22, P implanted layers are formed
5, high concentration N-type carrier accumulation layer is can compensate in the concentration of p-type structure, can reach makes N-type carrier accumulation layer select
Concentration can improve that an order of magnitude is other, while will not bring the degenerate case of voltage endurance capability, while P injection zones are by Schottky
Contact forms ground potential, so as to improve device property.
Wherein, the transistor further includes：In the hole barrier structure 6 for introducing Schottky contacts without circle born of the same parents region；It is described
Schottky contacts are connect with the metal of N+ emitters, form ground connection.
Further, the transistor further includes：Described without in N+ emitters 1 corresponding to circle born of the same parents region, the N+ is sent out
Emitter-base bandgap grading 1 includes the first oxide layer 11 and the second oxide layer 12, wherein is between first oxide layer, 11 and second oxide layer 12
With the metal of the Schottky contacts.
Specifically, the hole barrier structure 6 of Schottky contacts is introduced without circle born of the same parents region in the transistor.Schottky junction
Structure forms blocking effect due to the barrier effect to hole, to hole, and device is in conducting state, the Schottky junction structure in not rounded born of the same parents area
It is connect ground connection with 1 metal of N+ emitters, therefore the ground potential design of P implanted layers 5 may be implemented, at this time due to ground potential
It acting on, two neighboring P implanted layers 5 can be realized easily under lower concentration in device circle born of the same parents' structure mutually exhausts,
Shielding construction effect is formd, 4 concentration of N-type carrier accumulation layer that the transistor design can select can be higher than existing skill
Selection in art, while reaching the technique effect for not influencing voltage endurance capability.
Embodiment two
In order to more clearly illustrate a kind of igbt, the embodiment of the present application also provides a kind of insulated gates
The operation principle of bipolar transistor is below described in detail a kind of operation principle of igbt.
In conducting state, Schottky junction structure and the N+ in not rounded born of the same parents area emit igbt described herein
Pole 1 metal connection ground connection, therefore the ground potential design of P implanted layers 5, at this time since ground potential acts on, device may be implemented
Two neighboring P implanted layers 5 can be realized easily under lower concentration in circle born of the same parents' structure mutually exhausts, and forms shielding
Structure function, 4 concentration of N-type carrier accumulation layer that igbt design can select can be higher than existing
Selection in technology, while reaching the technique effect for not influencing voltage endurance capability；Because the igbt is profit
Shield effectiveness is realized to high concentration N-type carrier accumulation layer 4 with 5 ground potential of P implanted layers, therefore need not also be selected
High 5 concentration of P implanted layers, will not affect electron injection.New structure will not be due to highly concentrated due to earth shield effect
The carrier accumulation layer of degree can not exhaust and the pressure resistance of device is caused to be degenerated, therefore N-type carrier accumulation layer 4 can select to use
Very high concentration, concentration are selected above design in the prior art.Carrier accumulation layer 4 can stop almost all of at this time
Hole flow effectively enhances conductivity modulation effect.In addition, the Schottky contact structure in not rounded born of the same parents region with N+ although emit
The connection of pole 1 ground connection, but in break-over of device state, since Schottky contact barrier is to the effective barrier effect in hole, hole
It is difficult to be flowed out from the contact position.So transistor described herein realizes that most holes are blocked in conducting state,
To help the conducting saturation voltage drop approximation theory limit of device, and the voltage endurance capability of device is unaffected.
One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages：
1. a kind of igbt provided by the embodiments of the present application, by N+ emitters, the regions Pwell are described
The regions Pwell are located at the lower section of the N+ emitters, wherein being provided with the first slot grid and the second slot grid in the regions Pwell；N
Drift region, the drift regions N are located at the lower section in the regions Pwell；Carrier accumulation layer, the carrier accumulation layer are located at institute
The lower section in the regions Pwell is stated, and, the carrier accumulation layer is arranged between the first slot grid and the second slot grid；P is noted
Enter layer, the P implanted layers are located at the lower section of the first slot grid and the second slot grid, wherein the transistor further includes：
In the hole barrier structure for introducing Schottky contacts without circle born of the same parents region.It solves igbt in the prior art to carry
The technical issues of flowing after sub- accumulation layer technology concentration improves, igbt is caused to reduce pressure, has reached substantially
Degree reduces conduction voltage drop meanwhile, it is capable to maintain original voltage endurance capability, to the skill of the parameters ability of General Promotion device
Art effect.
2. the embodiment of the present application forms ground potential by the P implanted layers, further reach to high concentration N-type current-carrying
Sub- accumulation layer realizes shield effectiveness, therefore need not also select excessively high P injection zone concentration, will not be brought to electron injection
The technique effect of influence.
Although the preferred embodiment of the utility model has been described, once a person skilled in the art knows basic
Creative concept, then additional changes and modifications may be made to these embodiments.It is wrapped so the following claims are intended to be interpreted as
It includes preferred embodiment and falls into all change and modification of the scope of the utility model.
Obviously, those skilled in the art can carry out the utility model various modification and variations without departing from this practicality
Novel spirit and scope.If in this way, these modifications and variations of the present invention belong to the utility model claims and
Within the scope of its equivalent technologies, then the utility model is also intended to include these modifications and variations.
It should be noted last that the above specific implementation mode is only to illustrate the technical solution of the utility model rather than limit
System, although the utility model is described in detail with reference to example, it will be understood by those of ordinary skill in the art that, it can be right
The technical solution of the utility model is modified or replaced equivalently, without departing from the spirit and model of technical solutions of the utility model
It encloses, should all cover in the right of the utility model.
A kind of area determination method and device provided by the embodiments of the present application are as a result of by obtaining the first area week
Side, each nearest road with its distance, and according to the mutual limitation of the position relationship of each road, described in obtaining
The specific location of first area, solve in the prior art using the registration of predeterminable area and target area in database and
The problem of caused position inaccurate, and then reached the technique effect that can precisely obtain target specific location.
Claims (4)
1. a kind of igbt, which is characterized in that the transistor includes：
N+ emitters,
The regions Pwell, the regions Pwell are located at the lower section of the N+ emitters, wherein being provided in the regions Pwell
One slot grid and the second slot grid；
The drift regions N, the drift regions N are located at the lower section in the regions Pwell；
Carrier accumulation layer, the carrier accumulation layer are located at the lower section in the regions Pwell, and, the carrier accumulation layer
It is arranged between the first slot grid and the second slot grid；
P implanted layers, the P implanted layers are located at the lower section of the first slot grid and the second slot grid,
Wherein, the transistor further includes：
In the hole barrier structure for introducing Schottky contacts without circle born of the same parents region.
2. igbt as described in claim 1, which is characterized in that the transistor further includes：
The P implanted layers form ground potential.
3. igbt as described in claim 1, which is characterized in that the transistor further includes：
The Schottky contacts are connect with the metal of N+ emitters, form ground connection.
4. igbt as claimed in claim 3, which is characterized in that the transistor further includes：In the nothing
In N+ emitters corresponding to circle born of the same parents region, the N+ emitters include the first oxide layer and the second oxide layer, wherein described first
It is the metal with the Schottky contacts between oxide layer and the second oxide layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721830403.4U CN207624704U (en) | 2017-12-22 | 2017-12-22 | Insulated gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721830403.4U CN207624704U (en) | 2017-12-22 | 2017-12-22 | Insulated gate bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207624704U true CN207624704U (en) | 2018-07-17 |
Family
ID=62829980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721830403.4U Active CN207624704U (en) | 2017-12-22 | 2017-12-22 | Insulated gate bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207624704U (en) |
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2017
- 2017-12-22 CN CN201721830403.4U patent/CN207624704U/en active Active
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