CN206774547U - 薄膜晶体管结构、电路结构、显示基板及显示装置 - Google Patents
薄膜晶体管结构、电路结构、显示基板及显示装置 Download PDFInfo
- Publication number
- CN206774547U CN206774547U CN201720520432.4U CN201720520432U CN206774547U CN 206774547 U CN206774547 U CN 206774547U CN 201720520432 U CN201720520432 U CN 201720520432U CN 206774547 U CN206774547 U CN 206774547U
- Authority
- CN
- China
- Prior art keywords
- film transistor
- thin
- tft
- thin film
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 99
- 239000010408 film Substances 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000009413 insulation Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 35
- 239000002184 metal Substances 0.000 description 5
- 239000013078 crystal Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 210000004556 brain Anatomy 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
本实用新型提供了一种薄膜晶体管结构、电路结构、显示基板及显示装置,属于显示技术领域。其中,薄膜晶体管结构包括:衬底基板;位于所述衬底基板上层叠设置的第一薄膜晶体管和第二薄膜晶体管;所述第一薄膜晶体管和所述第二薄膜晶体管共用一个有源层。本实用新型的技术方案能够缩小薄膜晶体管结构在整个显示面板中所占区域的面积,提高显示面板的开口率。
Description
技术领域
本实用新型涉及显示技术领域,特别是指一种薄膜晶体管结构、电路结构、显示基板及显示装置。
背景技术
显示面板中的薄膜晶体管是关键器件,但是薄膜晶体管所在区域不透光,当显示面板中有多个薄膜晶体管时,多个薄膜晶体管在整个显示面板中所占区域的面积大小会对显示面板的显示有一定的影响。
例如,越来越多的显示面板都利用栅线集成驱动(Gate Driver on Array,简称GOA)技术,将栅极开关电路集成在显示面板中的薄膜晶体管结构上以形成对显示面板的扫描驱动,从而可以从材料成本和制作工艺两方面降低产品成本,这种集成在薄膜晶体管结构上的栅极开关电路称作栅线集成驱动电路,在栅线集成驱动电路中通常形成多个薄膜晶体管,会造成栅线集成驱动电路在整个显示面板中所占区域的面积较大,造成显示面板的边框较宽,不利于窄边框设计。
因此,如何保证在多个薄膜晶体管器件正常工作的前提下,减小薄膜晶体管在整个显示面板中所占区域的面积,是本领域技术人员亟需解决的技术问题。
实用新型内容
本实用新型要解决的技术问题是提供一种薄膜晶体管结构、电路结构、显示基板及显示装置,能够缩小薄膜晶体管结构在整个显示面板中所占区域的面积,提高显示面板的开口率。
为解决上述技术问题,本实用新型的实施例提供技术方案如下:
一方面,提供一种薄膜晶体管结构,包括:
衬底基板;
位于所述衬底基板上层叠设置的第一薄膜晶体管和第二薄膜晶体管;
所述第一薄膜晶体管和所述第二薄膜晶体管共用一个有源层。
进一步地,所述第一薄膜晶体管为底栅型薄膜晶体管,所述第二薄膜晶体管为顶栅型薄膜晶体管。
进一步地,所述有源层包括交叉设置的第一部分和第二部分,所述第一薄膜晶体管的栅极的延伸方向与所述第一部分的延伸方向平行,所述第二薄膜晶体管的栅极的延伸方向与所述第二部分的延伸方向平行,所述第一薄膜晶体管的源极和漏极分别与所述第一部分的两个端部连接,所述第二薄膜晶体管的源极和漏极分别与所述第二部分的两个端部连接。
进一步地,所述第一部分的延伸方向与所述第二部分的延伸方向垂直。
进一步地,还包括:
位于所述第一薄膜晶体管的栅极和所述有源层之间的第一栅绝缘层;
位于所述第二薄膜晶体管的栅极和所述有源层之间的第二栅绝缘层。
进一步地,所述第一薄膜晶体管的源极和漏极与所述第二薄膜晶体管的源极和漏极位于同一层。
本实用新型实施例还提供了一种显示基板,包括如上所述的薄膜晶体管结构。
本实用新型实施例还提供了一种电路结构,包括如上所述的薄膜晶体管结构。
进一步地,所述电路结构包括栅线集成驱动电路或有机电致发光显示器件的像素电路。
本实用新型实施例还提供了一种显示装置,包括如上所述的显示基板或如上所述的电路结构。
本实用新型的实施例具有以下有益效果:
上述方案中,第一薄膜晶体管和第二薄膜晶体管共用一个有源层,由于薄膜晶体管结构采用第一薄膜晶体管和第二薄膜晶体管层叠设置且共用一个有源层的新型结构,可以缩小多个薄膜晶体管结构在整个显示面板中所占区域的面积,提高显示面板的开口率,如果将该薄膜晶体管结构应用在GOA电路中时,可减小GOA电路占用面积,减小显示面板的边框,有利于实现显示面板的窄边框。
附图说明
图1为本实用新型实施例薄膜晶体管结构的立体示意图;
图2为图1中的AA截面示意图;
图3为图1中的BB截面示意图;
图4为本实用新型实施例显示基板的平面示意图;
图5为本实用新型实施例形成第一栅极后的平面示意图;
图6为本实用新型实施例形成有源层后的平面示意图;
图7为本实用新型实施例形成层间绝缘层后的平面示意图;
图8为本实用新型实施例形成源漏金属层后的平面示意图;
图9为本实用新型实施例形成第二栅极后的平面示意图。
附图标记
1第一栅极 2有源层 21有源层的第一部分
22有源层的第二部分 3第二栅极 4衬底基板
5第一栅绝缘层 6第二栅绝缘层 7源漏金属层
8层间绝缘层
具体实施方式
为使本实用新型的实施例要解决的技术问题、技术方案和优点更加清楚,下面将结合附图及具体实施例进行详细描述。
本实用新型的实施例提供一种薄膜晶体管结构、电路结构、显示基板及显示装置,能够缩小薄膜晶体管结构在整个显示面板中所占区域的面积,提高显示面板的开口率。
本实用新型实施例提供了一种薄膜晶体管结构,如图1-图3所示,包括:
衬底基板4;
位于所述衬底基板4上层叠设置的第一薄膜晶体管和第二薄膜晶体管;
其中,所述第一薄膜晶体管和所述第二薄膜晶体管共用一个有源层2。
本实施例中,第一薄膜晶体管和第二薄膜晶体管共用一个有源层,由于薄膜晶体管结构采用第一薄膜晶体管和第二薄膜晶体管层叠设置且共用一个有源层的新型结构,可以缩小多个薄膜晶体管结构在整个显示面板中所占区域的面积,提高显示面板的开口率,如果将该薄膜晶体管结构应用在GOA电路中时,可减小GOA电路占用面积,减小显示面板的边框,有利于实现显示面板的窄边框。
在具体实施时,在本实用新型实施例提供的上述薄膜晶体管结构中,为了能够使层叠设置的第一薄膜晶体管和第二薄膜晶体管共用一个有源层,如图1所示,该第一薄膜晶体管一般设置为底栅型薄膜晶体管,该第二薄膜晶体管一般设置为顶栅型薄膜晶体管,第一薄膜晶体管的栅极和第二薄膜晶体管的栅极分别位于有源层2的上下两侧,可以保证多个薄膜晶体管结构在正常工作的前提下,减小薄膜晶体管结构在显示面板中所占区域的面积。
在具体实施时,在本实用新型实施例提供的上述薄膜晶体管结构中,第一薄膜晶体管和第二薄膜晶体管可以同时设置为P型晶体管或N型晶体管。
具体实施例中,如图1-图3所示,有源层2包括交叉设置的第一部分21和第二部分22,所述第一薄膜晶体管的第一栅极1的延伸方向与所述第一部分21的延伸方向平行,所述第二薄膜晶体管的第二栅极3的延伸方向与所述第二部分22的延伸方向平行,所述第一薄膜晶体管的源极和漏极分别与所述第一部分21的两个端部连接,所述第二薄膜晶体管的源极和漏极分别与所述第二部分22的两个端部连接。
具体地,第一部分21的延伸方向可以与第二部分22的延伸方向垂直,即有源层2呈十字形。
进一步地,薄膜晶体管结构还包括:
位于所述第一薄膜晶体管的第一栅极1和所述有源层2之间的第一栅绝缘层5;
位于所述第二薄膜晶体管的第二栅极3和所述有源层2之间的第二栅绝缘层6。
优选地,第一薄膜晶体管的源极和漏极与第二薄膜晶体管的源极和漏极同层设置,均采用源漏金属层7制作,这样可以简化薄膜晶体管的结构,同时在制作薄膜晶体管结构时,可以通过一次构图工艺同时形成第一薄膜晶体管的源极、漏极、第二薄膜晶体管的源极、漏极,减少构图工艺的次数,简化制作工作,减低生产成本。
本实用新型实施例中,第一薄膜晶体管和第二薄膜晶体管的沟道宽长比是可以调节的,如图1-图3所示,第一薄膜晶体管的沟道宽长比等于W1/L1,第二薄膜晶体管的沟道宽长比等于W2/L2,这样通过调整第一栅极1的线宽和第一部分21的线宽可以调整第一薄膜晶体管的沟道宽长比,通过调整第二栅极3的线宽和第二部分22的线宽可以调整第二薄膜晶体管的沟道宽长比。
在具体实施时,本实用新型实施例提供的薄膜晶体管结构的制作方法,具体包括以下步骤:
S101、在衬底基板4上形成第一薄膜晶体管的第一栅极1,如图5所示;
S102、形成第一栅绝缘层5;
S103、形成十字形的有源层2,如图6所示,有源层2可以采用金属氧化物半导体,比如IGZO,当然,有源层还可以采用非晶硅或多晶硅;
S104、形成层间绝缘层8,对层间绝缘层8进行构图形成暴露出有源层2的过孔,如图7所示,通过过孔对有源层的源极接触区和漏极接触区进行导体化;
S105、形成源漏金属层7的图形,如图8所示,源漏金属层7的图形包括第一薄膜晶体管的源极和漏极、第二薄膜晶体管的源极和漏极,第一薄膜晶体管的源极与第一部分21的源极接触区连接,第一薄膜晶体管的漏极与第一部分21的漏极接触区连接,第二薄膜晶体管的源极与第二部分22的源极接触区连接,第二薄膜晶体管的漏极与第二部分22的漏极接触区连接;
S106、形成第二栅绝缘层6;
S107、形成第二薄膜晶体管的第二栅极3,如图9所示。
至此,经过具体实例提供的上述步骤S101至S107制作出了本实用新型实施例提供的上述薄膜晶体管结构。
基于同一实用新型构思,本实用新型实施例还提供了一种显示基板,包括本实用新型实施例提供的上述薄膜晶体管结构,上述薄膜晶体管结构应用于显示基板中,可以缩小薄膜晶体管结构在整个显示基板中所占区域的面积,有利于提高显示基板的开口率。对于显示基板的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的,在此不做赘述,也不应作为对本实用新型的限制。该显示基板的实施例可以参见上述薄膜晶体管结构的实施例,重复之处不再赘述。
图4为本实用新型实施例显示基板的平面示意图,如图4所示,第一薄膜晶体管和第二薄膜晶体管的栅极可以与不同的信号线连接,比如,第一薄膜晶体管的栅极G1与横向的栅线连接,第一薄膜晶体管的源极T1与纵向的数据线连接,第二薄膜晶体管的栅极G2与纵向的栅线连接,第二薄膜晶体管的源极T2与横向的数据线连接,这样通过对G1和G2、T1和T2的设计,可以达到分别开启第一薄膜晶体管和第二薄膜晶体管、分时复用的效果。
基于同一实用新型构思,本实用新型实施例还提供了一种栅线集成驱动电路,包括本实用新型实施例提供的上述薄膜晶体管结构,上述薄膜晶体管结构应用于栅线集成驱动电路,可以缩小栅线集成驱动电路在整个显示基板中所占区域的面积,从而有利于实现显示基板的窄边框设计。对于该栅线集成驱动电路的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的,在此不做赘述,也不应作为对本实用新型的限制。该栅线集成驱动电路的实施可以参见上述薄膜晶体管结构的实施例,重复之处不再赘述。
基于同一实用新型构思,本实用新型实施例还提供了一种有机电致发光显示器件的像素电路,包括本实用新型实施例提供的上述薄膜晶体管结构,上述薄膜晶体管结构应用于有机电致发光显示器件的像素电路中时,可以缩小像素电路在整个显示基板中所占区域的面积,有利于提高像素电路的开口率。对于该有机电致发光显示器件的像素电路的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的,在此不做赘述,也不应作为对本实用新型的限制。该有机电致发光显示器件的像素电路的实施可以参见上述薄膜晶体管结构的实施例,重复之处不再赘述。
可以理解的是,本实用新型实施例所述的薄膜晶体管结构可以应用于任何一种需要薄膜晶体管结构的电路结构中,并不限于上述的两种电路结构的描述。
基于同一实用新型构思,本实用新型实施例还提供了一种显示装置,包括本实用新型实施例提供的上述薄膜晶体管结构、显示基板或电路结构,所述电路结构可以包括栅线集成驱动电路或有机电致发光显示器件的像素电路,该显示装置可以为:手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的,在此不做赘述,也不应作为对本实用新型的限制。
除非另外定义,本公开使用的技术术语或者科学术语应当为本实用新型所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
可以理解,当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时,该元件可以“直接”位于另一元件“上”或“下”,或者可以存在中间元件。
以上所述是本实用新型的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本实用新型所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本实用新型的保护范围。
Claims (10)
1.一种薄膜晶体管结构,其特征在于,包括:
衬底基板;
位于所述衬底基板上层叠设置的第一薄膜晶体管和第二薄膜晶体管;
所述第一薄膜晶体管和所述第二薄膜晶体管共用一个有源层。
2.根据权利要求1所述的薄膜晶体管结构,其特征在于,所述第一薄膜晶体管为底栅型薄膜晶体管,所述第二薄膜晶体管为顶栅型薄膜晶体管。
3.根据权利要求1所述的薄膜晶体管结构,其特征在于,所述有源层包括交叉设置的第一部分和第二部分,所述第一薄膜晶体管的栅极的延伸方向与所述第一部分的延伸方向平行,所述第二薄膜晶体管的栅极的延伸方向与所述第二部分的延伸方向平行,所述第一薄膜晶体管的源极和漏极分别与所述第一部分的两个端部连接,所述第二薄膜晶体管的源极和漏极分别与所述第二部分的两个端部连接。
4.根据权利要求3所述的薄膜晶体管结构,其特征在于,所述第一部分的延伸方向与所述第二部分的延伸方向垂直。
5.根据权利要求3所述的薄膜晶体管结构,其特征在于,还包括:
位于所述第一薄膜晶体管的栅极和所述有源层之间的第一栅绝缘层;
位于所述第二薄膜晶体管的栅极和所述有源层之间的第二栅绝缘层。
6.根据权利要求3所述的薄膜晶体管结构,其特征在于,所述第一薄膜晶体管的源极和漏极与所述第二薄膜晶体管的源极和漏极位于同一层。
7.一种显示基板,其特征在于,包括如权利要求1-6任一项所述的薄膜晶体管结构。
8.一种电路结构,其特征在于,包括如权利要求1-6任一项所述的薄膜晶体管结构。
9.根据权利要求8所述的电路结构,其特征在于,所述电路结构包括栅线集成驱动电路或有机电致发光显示器件的像素电路。
10.一种显示装置,其特征在于,包括如权利要求7所述的显示基板或如权利要求8所述的电路结构。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201720520432.4U CN206774547U (zh) | 2017-05-11 | 2017-05-11 | 薄膜晶体管结构、电路结构、显示基板及显示装置 |
PCT/CN2018/078963 WO2018205740A1 (zh) | 2017-05-11 | 2018-03-14 | 薄膜晶体管结构及其制作方法、电路结构、显示基板及显示装置 |
US16/097,875 US11315960B2 (en) | 2017-05-11 | 2018-03-14 | Thin film transistor structure and manufacturing method thereof, circuit structure, display substrate and display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201720520432.4U CN206774547U (zh) | 2017-05-11 | 2017-05-11 | 薄膜晶体管结构、电路结构、显示基板及显示装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN206774547U true CN206774547U (zh) | 2017-12-19 |
Family
ID=60650516
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201720520432.4U Active CN206774547U (zh) | 2017-05-11 | 2017-05-11 | 薄膜晶体管结构、电路结构、显示基板及显示装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US11315960B2 (zh) |
CN (1) | CN206774547U (zh) |
WO (1) | WO2018205740A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018205740A1 (zh) * | 2017-05-11 | 2018-11-15 | 京东方科技集团股份有限公司 | 薄膜晶体管结构及其制作方法、电路结构、显示基板及显示装置 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11462282B2 (en) * | 2020-04-01 | 2022-10-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor memory structure |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6982194B2 (en) * | 2001-03-27 | 2006-01-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6740938B2 (en) * | 2001-04-16 | 2004-05-25 | Semiconductor Energy Laboratory Co., Ltd. | Transistor provided with first and second gate electrodes with channel region therebetween |
US6906344B2 (en) * | 2001-05-24 | 2005-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor with plural channels and corresponding plural overlapping electrodes |
US6639246B2 (en) * | 2001-07-27 | 2003-10-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP4275336B2 (ja) * | 2001-11-16 | 2009-06-10 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
JP2009188223A (ja) * | 2008-02-07 | 2009-08-20 | Seiko Instruments Inc | 半導体装置 |
US8390078B2 (en) | 2010-06-10 | 2013-03-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Quadrangle MOS transistors |
CN103268876B (zh) | 2012-09-27 | 2016-03-30 | 厦门天马微电子有限公司 | 静电释放保护电路、显示面板和显示装置 |
CN102969311B (zh) * | 2012-11-27 | 2015-02-11 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法、显示装置 |
CN105742309B (zh) * | 2016-02-29 | 2019-05-03 | 深圳市华星光电技术有限公司 | 互补型薄膜晶体管及其制造方法 |
CN206774547U (zh) * | 2017-05-11 | 2017-12-19 | 合肥鑫晟光电科技有限公司 | 薄膜晶体管结构、电路结构、显示基板及显示装置 |
-
2017
- 2017-05-11 CN CN201720520432.4U patent/CN206774547U/zh active Active
-
2018
- 2018-03-14 WO PCT/CN2018/078963 patent/WO2018205740A1/zh active Application Filing
- 2018-03-14 US US16/097,875 patent/US11315960B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018205740A1 (zh) * | 2017-05-11 | 2018-11-15 | 京东方科技集团股份有限公司 | 薄膜晶体管结构及其制作方法、电路结构、显示基板及显示装置 |
US11315960B2 (en) | 2017-05-11 | 2022-04-26 | Boe Technology Group Co., Ltd. | Thin film transistor structure and manufacturing method thereof, circuit structure, display substrate and display device |
Also Published As
Publication number | Publication date |
---|---|
WO2018205740A1 (zh) | 2018-11-15 |
US11315960B2 (en) | 2022-04-26 |
US20210257393A1 (en) | 2021-08-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10134785B2 (en) | Semiconductor device and method for manufacturing same | |
CN107507841B (zh) | 阵列基板及其制作方法、显示装置 | |
CN106920802B (zh) | 薄膜晶体管基板和使用该薄膜晶体管基板的显示器 | |
TWI226712B (en) | Pixel structure and fabricating method thereof | |
JP3964223B2 (ja) | 薄膜トランジスタ装置 | |
CN106409845A (zh) | 开关元件及其制备方法、阵列基板以及显示装置 | |
CN107482066A (zh) | 薄膜晶体管及其制备方法、阵列基板和显示装置 | |
KR20160039040A (ko) | 박막 트랜지스터 기판과 그 제조방법 및 그를 이용한 디스플레이 장치 | |
CN103499906A (zh) | 一种阵列基板、其制备方法及显示装置 | |
CN203521413U (zh) | 一种阵列基板及显示装置 | |
US20240172477A1 (en) | Display panel and display device | |
CN206774547U (zh) | 薄膜晶体管结构、电路结构、显示基板及显示装置 | |
CN203422543U (zh) | 一种阵列基板和显示装置 | |
JP3287038B2 (ja) | 液晶表示装置 | |
CN114420763A (zh) | 显示基板、显示基板的制造方法及显示装置 | |
JPH0534718A (ja) | 液晶表示装置 | |
KR101431655B1 (ko) | 전자 종이 능동 기판 및 전자 종이 능동 기판을 형성하는 방법 그리고 전자 종이 디스플레이 패널 | |
CN109828395A (zh) | 一种阵列基板及其制造方法 | |
TWI363386B (en) | Semiconductor structure and method for manufacturing the same | |
CN101740524A (zh) | 薄膜晶体管阵列基板的制造方法 | |
CN107112365A (zh) | 半导体装置 | |
US11043599B2 (en) | Semiconductor device and method for producing same | |
JP3105408B2 (ja) | 液晶表示素子 | |
TW396329B (en) | Electric device having non-light emitting type display and method for making the electric device | |
JP2690067B2 (ja) | アクティブマトリクス基板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |