CN206271704U - Realize the wafer-level packaging of ultra-thin ambient light and proximity transducer - Google Patents
Realize the wafer-level packaging of ultra-thin ambient light and proximity transducer Download PDFInfo
- Publication number
- CN206271704U CN206271704U CN201620731706.XU CN201620731706U CN206271704U CN 206271704 U CN206271704 U CN 206271704U CN 201620731706 U CN201620731706 U CN 201620731706U CN 206271704 U CN206271704 U CN 206271704U
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- China
- Prior art keywords
- wafer
- wiring layers
- ambient light
- level packaging
- proximity transducer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 238000007789 sealing Methods 0.000 claims abstract description 16
- 239000004020 conductor Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 16
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 239000002390 adhesive tape Substances 0.000 description 13
- 238000007493 shaping process Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 239000007787 solid Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000012780 transparent material Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000001746 injection moulding Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000035807 sensation Effects 0.000 description 2
- 239000000741 silica gel Substances 0.000 description 2
- 229910002027 silica gel Inorganic materials 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 description 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 description 1
- 239000004831 Hot glue Substances 0.000 description 1
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- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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- 230000001681 protective effect Effects 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- Light Receiving Elements (AREA)
- Led Device Packages (AREA)
Abstract
The utility model provides a kind of wafer-level packaging for realizing ultra-thin ambient light and proximity transducer, with photoinduction chip, luminescent wafer, optics sealing cover and anti-protective hood;Photoinduction chip is located in optics sealing cover, and optics sealing cover is located in anti-protective hood;Characterized in that, the bottom of the encapsulation is RDL wiring layers, the photoinduction chip and the RDL wiring layers are electrically connected by wire.The utility model has these technical characterstics, has reached and has abandoned purpose and effect that PCB substrate realizes slimming and efficient production.
Description
Technical field
The utility model relates to the encapsulation technology of sensor, more particularly to a kind of ultra-thin ambient light and proximity transducer realized
Wafer-level packaging.
Background technology
The miniaturization of smart machine is the miniaturization based on its component parts.Ambient light is combined with light sensation with proximity transducer
Chip and luminescent wafer are answered, in traditional handicraft, this two kinds of chips are respectively adopted different wafer manufactures, recombinant to PCB substrate
Upper encapsulation;Because PCB substrate is difficult to be thinned, the slimming development of this kind of sensor is constrained.
Utility model content
As it was previously stated, how to break through the technique bottleneck of PCB substrate, two kinds of differences are made the photoinduction chip and hair of technique
Light chip realizes that the requirement for minimizing is the utility model problem to be solved again in being combined to an encapsulation;How to be lifted
Packaging efficiency is the utility model first purpose to be reached to reduce production cost.
In order to reach the purpose of the utility model, the technical solution of the utility model is as follows.
The wafer-level packaging of ultra-thin ambient light and proximity transducer is realized, with photoinduction chip, luminescent wafer, optics envelope
Cover and anti-protective hood;Photoinduction chip is located in optics sealing cover, and optics sealing cover is located in anti-protective hood;Characterized in that, described
The bottom of encapsulation is RDL wiring layers, and the photoinduction chip and the RDL wiring layers are electrically connected by wire.
In certain embodiments, the bottom of the luminescent wafer and RDL wiring layers are electrically connected.
In certain embodiments, also it is implanted into or covering conductor in the bottom surface of RDL wiring layers,
In certain embodiments, it is described to be included in bottom surface in the bottom surface implantation of RDL wiring layers or the mode of covering conductor
The one kind in metal pad or au bump or solder bump is generated on salient point bottom metal layer (UBM).
The utility model changes the technique for traditionally relying on PCB substrate, and reality is combined using RDL wiring layers and wire welding tech
The existing wafer-level packaging;Change PCB substrate in technique and chip to be permanently fixed be interim fixation by shaping carrier and adhesive tape,
The RDL wiring layers and chip formed with plating by etching are connected, and excuse me learns sealing cover and anti-protective hood locking chip;Shaping carrier
Multiple chips combinations to be processed can simultaneously be carried, can to the whole chipset contracts on shaping carrier when make optics sealing cover and
Anti- protective hood;Compared with single pcb board structure, quick wire bond (Wire Bonding) is also allowed for;Additionally, on provisional adhesive tape institute
The RDL wiring layers of formation are not only especially advantageous for being processed when slimming design is additionally favorable for multiple chipset contracts, more can basis
Replaced using wire bond (Wire Bonding) or RDL wiring layer process, RDL wiring layers on different propagation of electrical signals feature selecting ground
The connection of the precursor Welding of a generation part can significantly improve packaging efficiency, retain a part of wire bond (Wire Bonding) work
Skill can provide reliable guarantee for the lead of specific current requirement.The utility model has these technical characterstics, has reached and has abandoned
PCB substrate realizes slimming and the efficiently purpose and effect of production.
Additionally, being formed using etching and electroplating technology more than RDL wiring layers, formed easily in the etching and plated edge of adhesive tape
Stress, the Stress superposition that isolated island structure can completely cut off between each group encapsulation, the stress control etching and plating to adhesive tape
System is very helpful to lifting encapsulation precision and raising yield in the range of isolated island.In addition, forming optics envelope using hot melt
Adhesive tape forms isolated island structure in some implementations of cover and anti-protective hood, the heat of each group photoinduction chip and luminescent wafer along into
The surface of type carrier is hindered when being outwards delivered to adjacent isolated island by insulating space, and heat is directed into main to vertical forming load
The direction transmission of tool is simultaneously mainly distributed by shaping carrier, and this kind of feature can eliminate each group by Control Thermal Deformation in single isolated island
The thermal deformation of photoinduction chip and luminescent wafer adds up, also very helpful to lifting encapsulation precision and raising yield.
Above generally describe some feature and advantage of the present utility model;However, the other spy for being given herein
Levy, advantage and embodiment, or those of ordinary skill in the art for having checked the accompanying drawing of this paper, specification and claims
It will be clear that other feature, advantage and embodiment.It should therefore be understood that scope of the present utility model should not be practical by this
It is limitation disclosed in new summarized section.
Brief description of the drawings
Fig. 1 be embodiment encapsulation realize step a schematic diagrames;
Fig. 2 be embodiment encapsulation realize step b schematic diagrames;
Fig. 3 be embodiment encapsulation realize step c schematic diagrames;
Fig. 4 be embodiment encapsulation realize step d schematic diagrames;
Fig. 5 be embodiment encapsulation realize step e schematic diagrames;
Fig. 6 be embodiment encapsulation realize step f schematic diagrames;
Fig. 7 be embodiment encapsulation realize step g schematic diagrames;
Fig. 8 is the schematic diagram of embodiment encapsulation;
Fig. 9 is embodiment adhesive tape insulating space schematic diagram.
Drawing reference numeral explanation:
10 photoinduction chip, 11 wire, 20 luminescent wafer 30 is molded the adhesive tape of carrier 31
The conductor of 311 insulating space, 40 50 anti-protective hood of optics sealing cover 60
Accompanying drawing filling meets explanation:
What thicker solid black patch was represented is optics sealing cover and anti-protective hood;Vertical direction and thinner solid black patch expression
Be silicon perforation;Horizontal direction and the expression of thinner solid black patch are RDL wiring layers;Elliptoid solid black patch expression is
The bottom surface implantation of RDL wiring layers or the conductor of covering.
Specific embodiment
To enable above-mentioned purpose of the present utility model, feature and advantage more obvious understandable, embodiment will be below enumerated
Specific embodiment of the present utility model is elaborated.Elaborate in the following description in order to fully understand this practicality
New specific embodiment, but, the utility model can be implemented with different from mode described below, those skilled in the art
Similar popularization can be done in the case of without prejudice to the utility model intension.Therefore, the utility model is not had by following discloses
The limitation of body embodiment.
The present embodiment realizes ultra-thin ambient light with the wafer-level packaging of proximity transducer using as shown in Fig. 1 to Fig. 7
The step of step completion, Fig. 1 to Fig. 7, is as follows:
A. RDL wiring layers are prepared
B. the bottom of RDL wiring layers is attached on shaping carrier by adhesive tape;
C. photoinduction chip and luminescent wafer are welded on RDL wiring layers by Reflow Soldering or pressure sintering;
D. photoinduction chip and RDL wiring layers are connected using wire welding tech (Wire Bonding);
E. luminescent wafer and photoinduction chip are wrapped up with light transmissive material and is shaped to optics sealing cover;
F. optics sealing cover is wrapped up with alternatively non-transparent material, is formed between luminescent wafer and photoinduction chip every light belt and be molded
It is anti-protective hood;
G. it is to realize the wafer-level packaging to remove shaping carrier and its adhesive tape.
According to above-mentioned steps, the process of specific implementation is as follows.First, photoinduction chip 10, photoinduction chip 10 are got out
It can be environment light sensor (Ambient Light Sensor) or close to inductor (Proximity Sensor) or preceding
A combination of both structure, such as Fig. 1, it is demonstration that the present embodiment uses the structure of both combinations.Secondly, luminescent wafer is got out, this
Embodiment luminescent wafer selects light emitting diode (LED) wafer, the wavelength that the light emitting diode lights to be selected with use requirement
Select, wave-length coverage is not limited;The luminescent wafer that the present embodiment is demonstrated selects the less simple luminescent wafer of number of electrodes, at it
The luminescent wafer with silicon hole can also be selected in his embodiment.
Again, such as Fig. 1, RDL wiring layers are prepared, the present embodiment RDL wiring layers are formed by etching and electroplating technology.
Such as Fig. 2, the shaping carrier 30 (Carrier) with silica gel adhesive tape 31 is got out, shaping carrier 30 elects smooth as
Silicon chip;Adhesive tape 31 is from silica gel adhesive tape and sets insulating space 311, and isolated island is formed between adjacent insulating space 311, and light sensation is brilliant
Piece 10 and luminescent wafer 20 will be placed on the isolated island.
As schemed, 3, by photoinduction chip 10 (Light Sensor Die) and luminescent wafer 20 (LED Die) respectively from it
Each belonging to wafer on capture under, the photosurface of photoinduction chip 10 and the luminous of luminescent wafer 20 face up, another side
Pass down through adhesive tape 31 to be fixed on carrier, another side passes down through scaling powder or fixing glue is fixed on RDL wiring layers, such as scheme
8, be integrally fixed in the present embodiment insulating space 311 around formed isolated island on.
Such as Fig. 4, using wire welding tech (Wire Bonding), with drawing, wire 11 connects photoinduction chip and RDL is connected up
Layer.
Such as Fig. 5, using the moulding process of encapsulating injection molding 44, photoinduction chip 10 and the shape of luminescent wafer 20 are wrapped up with light transmissive material
Into optics sealing cover 40, the present embodiment light transmissive material uses transparent thermosetting epoxy resin (EMC).
Such as Fig. 6, proceed secondary encapsulating injection molding, filled with alternatively non-transparent material and parcel optical lens sealing cover 40 and
20 shaping light extractions form anti-protective hood 50 every band between photoinduction chip 10 and luminescent wafer.The present embodiment alternatively non-transparent material
Can be using materials such as thermoset material EMC, thermoplasticity PCT, MODIFIED PP A and class ceramoplastics.
Such as Fig. 7, remove shaping carrier 30 and its adhesive tape 10 realizes the wafer-level packaging.
As shown in figure 8, after the present embodiment Ultrathin packaging is completed, also can be with the salient point bottom of RDL wiring layers bottom surface gold
The one kind in metal pad or au bump or solder bump is generated on categoryization layer (UBM), is easy to the sensor after cutting to encapsulate
Monomer and outside mainboard welding.
The above, is only preferred embodiment of the present utility model, not makees any formal to the utility model
Limitation.Any those skilled in the art, in the case where technical solutions of the utility model scope is not departed from, all using upper
The technology contents for stating announcement make various possible variations and modification to technical solutions of the utility model, or are revised as equivalent variations
Equivalent embodiments.Therefore, every content for not departing from technical solutions of the utility model, according to essence of the present utility model to
Any simple modification, equivalent variation and modification that upper embodiment is done, belong to the protection domain of technical solutions of the utility model.
Claims (4)
1. the wafer-level packaging of ultra-thin ambient light and proximity transducer is realized, with photoinduction chip, luminescent wafer, optics sealing cover
With anti-protective hood;Photoinduction chip is located in optics sealing cover, and optics sealing cover is located in anti-protective hood;Characterized in that, the envelope
The bottom of dress is RDL wiring layers, and the photoinduction chip and the RDL wiring layers are electrically connected by wire.
2. the wafer-level packaging for realizing ultra-thin ambient light and proximity transducer according to claim 1, it is characterised in that institute
State bottom and the electrical connection of RDL wiring layers of luminescent wafer.
3. the wafer-level packaging for realizing ultra-thin ambient light and proximity transducer according to claim 1, it is characterised in that also
Bottom surface implantation or covering conductor in RDL wiring layers.
4. the wafer-level packaging for realizing ultra-thin ambient light and proximity transducer according to claim 3, it is characterised in that institute
State and be included in life on the salient point bottom metal layer (UBM) of bottom surface in the bottom surface implantation of RDL wiring layers or the mode of covering conductor
One kind into metal pad or au bump or solder bump.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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CN201620731706.XU CN206271704U (en) | 2016-07-12 | 2016-07-12 | Realize the wafer-level packaging of ultra-thin ambient light and proximity transducer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN201620731706.XU CN206271704U (en) | 2016-07-12 | 2016-07-12 | Realize the wafer-level packaging of ultra-thin ambient light and proximity transducer |
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Publication Number | Publication Date |
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CN206271704U true CN206271704U (en) | 2017-06-20 |
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CN201620731706.XU Expired - Fee Related CN206271704U (en) | 2016-07-12 | 2016-07-12 | Realize the wafer-level packaging of ultra-thin ambient light and proximity transducer |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105977249A (en) * | 2016-07-12 | 2016-09-28 | 希睿(厦门)科技有限公司 | Improved method for realizing wafer-grade package of ultrathin environment light and proximity sensor, and package |
-
2016
- 2016-07-12 CN CN201620731706.XU patent/CN206271704U/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105977249A (en) * | 2016-07-12 | 2016-09-28 | 希睿(厦门)科技有限公司 | Improved method for realizing wafer-grade package of ultrathin environment light and proximity sensor, and package |
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Legal Events
Date | Code | Title | Description |
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GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20180816 Address after: 315500 Dongfeng Road, Fenghua District, Ningbo, Zhejiang 80 Patentee after: NINGBO DELTAWAVE TECHNOLOGY CO.,LTD. Address before: 361006 room 107, Xuan Ye Lou, Pioneer Park, torch high tech Zone, Xiamen, Fujian Patentee before: XIRUI (XIAMEN) TECHNOLOGY CO.,LTD. |
|
CF01 | Termination of patent right due to non-payment of annual fee | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170620 |