CN206059390U - A kind of Novel LED chip encapsulating structure - Google Patents
A kind of Novel LED chip encapsulating structure Download PDFInfo
- Publication number
- CN206059390U CN206059390U CN201621092720.6U CN201621092720U CN206059390U CN 206059390 U CN206059390 U CN 206059390U CN 201621092720 U CN201621092720 U CN 201621092720U CN 206059390 U CN206059390 U CN 206059390U
- Authority
- CN
- China
- Prior art keywords
- led chip
- drain pan
- encapsulating structure
- chip
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- Led Device Packages (AREA)
Abstract
This utility model provides a kind of Novel LED chip encapsulating structure, including drain pan, the three LEDs chips on drain pan surface, three LEDs chips are respectively the first LED chip, the second LED chip and the 3rd LED chip,, in parallel to each other on drain pan surface, the 3rd LED chip is in the side of first, second LED chip end for first, second LED chip；First, second LED chip horizontally set, the 3rd LED chip are longitudinally disposed.Using such arrangement mode, principle of the LED chip from bottom-emission is make use of, be conducive to being obviously improved LED chip brightness and solve heat dissipation problem.
Description
Technical field
This utility model is related to technical field of semiconductor encapsulation, specifically refers to a kind of chip row for improving LED light effect
Row mode.
Background technology
With market development demand, user is done in encapsulation semicon industry at present to trimorphism 1W product requirements more and more higher
Trimorphism product is staggered with three LEDs chips, and according to LED chip principle of luminosity, LED chip is issued from bottom-emission,
So when three LEDs chips are put together, mutually blocking between chip and chip so that Intensity LEDs between LED chip
Can not send out, suffer from the drawback that：Brightness cannot be lifted.
Utility model content
In place of solving the deficiencies in the prior art, the purpose of this utility model is to provide a kind of Novel LED chip envelope
Assembling structure.
For achieving the above object, the technical solution adopted in the utility model is：A kind of Novel LED chip encapsulating structure, bag
Include drain pan, the three LEDs chips on drain pan surface, three LEDs chips be respectively the first LED chip, the second LED chip and
3rd LED chip, first, second LED chip in parallel to each other on the drain pan surface, the 3rd LED chip in first,
The side of the second LED chip end；First, second LED chip horizontally set, the 3rd LED chip are longitudinally disposed.
Advantageous Effects：The three LEDs chips on drain pan surface, wherein two LEDs chips are parallel and laterally set
On drain pan surface, the end of the two is staggered, and another LEDs chip is longitudinally disposed, and which is located at two LEDs of two horizontally sets
The end side of chip, using such arrangement mode, make use of principle of the LED chip from bottom-emission, be conducive to significant
Lift LED chip brightness and solve heat dissipation problem.
Description of the drawings
Fig. 1 is negative pole copper sheet front view of the present utility model.
Specific embodiment
In order that those skilled in the art more fully understand this New Scheme, below in conjunction with the accompanying drawings with embodiment to this
Utility model is described in further detail.
As shown in figure 1, a kind of Novel LED chip encapsulating structure, including drain pan 1, the three LEDs cores on drain pan surface
Piece, three LEDs chips are respectively the first LED chip 2, the second LED chip 3 and the 3rd LED chip 4, first, second LED
In parallel to each other on drain pan surface, the 3rd LED chip 4 is located at the side of first, second LED chip end to chip 2,3；The
First, the second LED chip horizontally set, the 3rd LED chip are longitudinally disposed.
The three LEDs chips on drain pan surface, wherein the first LED chip 2, the second LED chip 3 is parallel and laterally sets
On 1 surface of drain pan, the end of the two is staggered, and the 3rd LED chip 4 is longitudinally disposed, and which is located at a LED of two horizontally sets
The end side of chip 2, the second LED chip 3, using such arrangement mode, make use of original of the LED chip from bottom-emission
Reason, is conducive to being obviously improved LED chip brightness and solves heat dissipation problem.
Although depicting this utility model by embodiment, it will be appreciated by the skilled addressee that this utility model has perhaps
Shape changeable and change without deviating from spirit of the present utility model, it is desirable to appended claim include these deformation and change and not
Depart from spirit of the present utility model.
Claims (1)
1. a kind of Novel LED chip encapsulating structure, including drain pan, the three LEDs chips on drain pan surface, its feature exist
In three LEDs chips are respectively the first LED chip, the second LED chip and the 3rd LED chip, first, second LED chip
In parallel to each other on drain pan surface, the 3rd LED chip is in the side of first, second LED chip end；First, second
LED chip horizontally set, the 3rd LED chip are longitudinally disposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621092720.6U CN206059390U (en) | 2016-09-29 | 2016-09-29 | A kind of Novel LED chip encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621092720.6U CN206059390U (en) | 2016-09-29 | 2016-09-29 | A kind of Novel LED chip encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206059390U true CN206059390U (en) | 2017-03-29 |
Family
ID=58366530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621092720.6U Active CN206059390U (en) | 2016-09-29 | 2016-09-29 | A kind of Novel LED chip encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206059390U (en) |
-
2016
- 2016-09-29 CN CN201621092720.6U patent/CN206059390U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 518107 3-4 / F, building a, mingfengda Industrial Park, Baoshan Road, Tianliao community, Yutang street, Guangming District, Shenzhen City, Guangdong Province Patentee after: Guangdong Jingrui Semiconductor Co.,Ltd. Address before: 5th Floor, Building 3, Hongfa Innovation Park, Jiuwei Zhoushi Road, Xixiang Street, Baoan District, Shenzhen, Guangdong 518100 Patentee before: SHENZHEN JINGRUI PHOTOELECTRIC CO.,LTD. |