CN205873893U - 半导体材料的密封器件 - Google Patents

半导体材料的密封器件 Download PDF

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CN205873893U
CN205873893U CN201620241631.7U CN201620241631U CN205873893U CN 205873893 U CN205873893 U CN 205873893U CN 201620241631 U CN201620241631 U CN 201620241631U CN 205873893 U CN205873893 U CN 205873893U
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A·托齐奥
C·瓦尔扎希纳
L·奎利诺尼
G·阿勒加托
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STMicroelectronics SRL
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Abstract

本申请涉及半导体材料的密封器件。提供一种半导体材料的密封器件，其中半导体材料的芯片(56)通过至少一个柱元件(60)固定至封装本体(51)的基础元件(52)，柱元件具有比芯片大的弹性和可变形性，例如低于300MPa的杨氏模量。在一个实例中，四个柱元件(60)固定为与芯片的固定表面(56A)的角部邻近并且操作为非耦合结构，这防止将基础元件的应力和变形传递至芯片。从而提供对热机械应力敏感度降低的半导体材料的密封器件。

Description

半导体材料的密封器件
技术领域
本实用新型涉及对热机械应力敏感度降低的半导体材料的密封器件。具体地，以下描述关于惯性类型的MEMS(微机电系统)器件诸如电容型的加速计或陀螺仪，但本实用新型不限于此。
背景技术
如已知的，诸如MEMS器件的半导体器件通常被密封在封装件中以能够对其进行保护和操控。下文中，参照支持表面安装的封装件，但本实用新型不限于此。
目前，最广泛用于MEMS传感器的表面安装封装件的类型是所谓的LGA(栅格阵列)封装件，其在封装件的底侧上具有正方形栅格的接触件。图1和图2分别以截面和后视图示出了LGA类型的封装件的实例。
具体地，图1示出了密封MEMS器件1的实例，其包括基部2、盖3、接合至基部2的第一芯片4以及接合至第一芯片的第二芯片5。基部2可以通过不同材料(例如，玻璃纤维或陶瓷)的支撑件形成，并且盖可以是金属、聚合材料或陶瓷材料。第一芯片4可以是MEMS部件(例如电容型)并且包括惯性类型的感应结构诸如加速计或陀螺仪，并且第二芯片5可以是包括信号处理电路的集成电路诸如ASIC(专用集成电路)。
通常，第二芯片5电耦合至第一芯片4以接收由第一芯片提供的测量信号并且向外部提供测量量的值和/或与其相关的量。
作为上述的备选，可以利用全铸造技术来得到封装件，并且两个芯片4、5可以被密封物所包围，密封物完全包围它们并且填充封装件的体积。
图2示出了由10表示并且相对于基部2在外围布置的后接触件的布置。接触件10由金属材料诸如铜制成，并且经由接合导线7和通孔8(图1)连接至第二芯片5。导线9将芯片4、5连接到一起。
图3示出了形成加速计或惯性陀螺仪的MEMS部件5的结构实例的示意性顶部平面图。MEMS部件5包括布置在衬底(图3中未示出)上方并且经由弹簧17由固定区域16支撑的悬浮物15。固定区域16在悬浮物15的整个周围延伸，并且相对于衬底固定。固定电极18从固定区域16延伸到悬浮物15，并且与移动电极19(其从悬浮物15延伸到固定区域16)组成梳状。
固定区域16上的接触焊盘22将接合导线7耦合至图1和图2的端子10。
所示封装件结构对热机械应力敏感，该热机械应力例如通过温度跳变、湿度、老化、环境条件以及引起基部2的弯曲或其他变形的其他机械应力所引起。例如，由于第一芯片4和基部2的材料不同，并因此具有不同的热膨胀系数，所以暴露于温度梯度会引起封装件的变形或翘曲。这些变形会引起固定电极18和移动电极19之间的距离的变化，从而影响由第一芯片4生成的信号的输出参数，危害测量的精度，并且确定操作不确定性。
关于这点，现在参照图4A、图4B以及图5A、图5B，它们分别示出了由于温度变化ΔT>0所导致的对MEMS器件的应力影响以及由于温度变化ΔT<0所导致的应力影响。
从图4A、图4B可以看出，温度的增加会引起衬底(这里由25表示)向上的弯曲(面向电极18、19凸起)，这又会引起静止距离g0的增加。相反，温度的降低(图5A、图5B)会引起衬底25向下的弯曲(面向电极18、19凹进)，这又会引起静止距离g0的减小。
例如，当芯片4是加速计时，差别距离的修改会修改直流(d.c.)信号(所谓的“0-g电平漂移”)的值和期望的敏感度漂移。当芯片4是陀螺仪时，电极之间的距离的修改会影响品质因子、谐振频率和正交，引起零电平漂移，并且在这种情况下影响期望的敏感度漂移。
为了消除或至少减小机械应力对MEMS器件的输出参数的影响，提出了架构型和结构型的各种解决方案。
例如，美国专利8,434,364提出了优化抛锚(anchoring)位置，用于在存在芯片的衬底弯曲的情况下减小输出信号的参数值的偏离。
其他解决方案设想使用采用低应力材料和/或具有类似应力特性的材料的封装件。例如，图6示出了密封器件30，其中通过陶瓷本体31和顶盖32形成封装件，该顶盖32通常也由陶瓷材料制成。陶瓷本体31具有容纳两个芯片34、35的腔体33。例如，第一芯片34是MEMS传感器，并且在腔体33内经由第一粘合层371(例如，用于半导体工业中的连续DAF(裸片附接膜)层)接合在陶瓷本体31的底部上。例如，第一粘合层371可以是层压环氧树脂1。例如，第二芯片35通过ASIC形成并且经由第二粘合层372(例如，DAF层)接合在第一芯片34的顶部上。电连接(未示出)将芯片34和35耦合至形成在陶瓷本体31中的端子36。
图6还示意性地示出了利用第一芯片34的衬底39提供刚性的固定电极38以及面对固定电极38的移动电极40。
所使用的陶瓷材料具有以下优势：具有与形成芯片34、35的硅类似的热膨胀系数，因此减小了由于热效应而引起的变形，并且减弱了来自外部的机械应力，但是不足以在所有其他情况下降低参数变化的可靠性。
因此，当前的解决方案不能总是足以消除不期望的效应。
实用新型内容
本实用新型的目的在于提供一种克服现有技术缺陷的密封器件。
根据本实用新型，提供一种半导体材料的密封器件，其特征在于，包括：封装本体(51)，具有基础元件(52)；半导体材料的第一芯片(56)；以及至少一个柱元件(60；60A)，布置在所述第一芯片(56)和所述基础元件(52)之间并且将所述第一芯片(56)和所述基础元件(52)固定到一起，所述柱元件(60；60A)的杨氏模量低于所述第一芯片的杨氏模量。
在一个实施例中，该器件包括位于所述第一芯片(56)和所述封装本体(51)之间的空置空间。
在一个实施例中，所述第一芯片(56)是MEMS。
在一个实施例中，所述第二芯片(57)接合至所述第一芯片(56)。
在一个实施例中，该器件包括多个柱元件(60)，其中所述第一芯片(56)具有包括角部的矩形形状的固定表面(56A)，并且所述柱元件(60)被固定为与所述芯片(56)的所述固定表面(56A)的所述角部邻近。
在一个实施例中，所述第一芯片(56)具有面对所述基础元件(58)的固定表面(56A)，其中所述柱元件被布置在中心(60A)处并且固定至所述第一芯片(56)的所述固定表面(56A)的中心部分。
在一个实施例中，所述至少一个柱元件(60；60A)是有机材料、抗蚀剂或软胶的；例如DAF层。
在一个实施例中，所述封装本体(51)是陶瓷材料的。
在一个实施例中，该器件还包括支撑芯片(59)，所述支撑芯片(59)被布置在所述基础元件(52)与所述至少一个柱元件(60；60A)之间。
在一个实施例中，所述柱元件(60；60A)的杨氏模量低于500MPa，通常低于300MPa。
根据本申请的技术方案，可以提供对热机械应力敏感度降低的半导体材料的密封器件。
附图说明
为了更好地理解本实用新型，现在仅通过非限制实例参照附图描述其优选实施例，其中：
图1是已知密封器件的截面图；
图2是图1的密封器件的底视图；
图3是已知MEMS器件的架构的示意性顶部平面图；
图4A和图4B是在存在由正温度梯度引起的衬底变形的情况下的移动电极和固定电极的相对位置的示意图示；
图5A和图5B是在存在由负温度梯度引起的衬底变形的情况下的移动电极和固定电极的相对位置的示意图示；
图6是已知密封器件的截面图；
图7是本实用新型的密封器件的实施例的截面图；
图8示出了沿着图7的截面VIII-VIII的平面截取的截面图；
图9示出了在存在由外部力引起的应力的情况下图7的器件的行为；
图10是用于本实用新型的密封器件的制造步骤的截面图；
图11是本实用新型的密封器件的不同实施例的截面图；以及
图12示出了沿着图11的截面XII-XII的平面截取的截面图。
具体实施方式
图7示出了密封器件50，其包括通过基础元件52和盖53形成的封装本体51，其中盖53经由固定区域54(例如，树脂膜)接合至基础元件52。基础元件52和盖53例如是陶瓷材料的并且在内部限定容纳两个芯片56、57的腔体55。
例如，第一芯片56可以是包括敏感结构68的MEMS传感器，该敏感结构68例如为惯性类型的感应结构，诸如电容型的加速计或陀螺仪。以与已知密封器件类似的方式，第二芯片57可以是诸如ASIC(包括信号处理电路)的集成电路。
在腔体55内，第一芯片56具有固定至基础元件52的固定表面(这里为底表面56A)。具体地，第一芯片的底表面56A经由支撑件59和柱60固定至基础元件52的底侧58，如以下更详细解释的那样。第二芯片57经由粘合层61(例如，DAF)接合至第一芯片56的顶部(因而接合至其顶侧)。
基础元件52结合有接触端子65，接触端子65在外围布置成面对基础元件52的底表面并且与基础元件52的底表面齐平。接触端子65通常为金属材料例如铜的，并且经由通孔连接66(在图7中仅示出一个)、接合导线67(在图7中仅示出一个)和接触焊盘(未示出，类似于图3的焊盘22)而连接至第二芯片57。接合导线66(仅示出一个)将芯片56、57连接到一起。
以已知方式制造第一芯片56；例如，敏感结构68包括悬浮物(未示出)、移动电极70(仅示出一个)以及与移动电极构成梳状并且利用第一芯片56的衬底72具有刚性的固定电极71。
支撑件59例如通过半导体材料(诸如硅)的裸片来形成，以任何已知方式接合至基础元件52的底侧58，例如经由又一粘合层(未示出，例如DAF)。
柱60是具有低杨氏模量的材料的，其低于第一芯片56的杨氏模量，例如低于500MPa，通常低于300MPa，例如杨氏模量为近似180MPa的干性抗蚀剂。例如，柱60具有包括在50μm和100μm之间的厚度。
如图8所示，在第一芯片56的底表面56A的四个角上，在外围位置中布置柱60，用于为第一芯片56提供良好的支撑并且防止其在组装期间翻转。
作为备选，代替外围柱60，可以如图11和图12所示设置单个中心柱60A。
以这种方式，第一芯片56以可选择的方式，仅在一些点(在柱60；60A处)中而不是贯穿其整个底表面56A，固定至封装本体51(通过支撑件58)。实际上，在第一芯片56和支撑件58之间存在空间(即，物理不连续)，使得封装本体51(和支撑件58)的任何可能变形不会传递至第一芯片56上，至少是由于不存在邻接。例如，柱60、60A的总面积在第一芯片56的固定表面56A的面积的0.5％和20％之间变化。在一个实施例中，对于3mmx2mm的第一芯片56来说，柱60可以具有200μm2的总面积。
由于柱60、60A具有远大于硅的弹性(几百GPa的量级)，并且进一步由于不存在第一芯片56的整个底表面56A和支撑件59之间的物理邻接，所以柱60、60A吸收了引起基础元件52(尤其是底侧58)的变形的可能力(如图9所示)。这里，等效于从外侧作用于底侧58的力的应力引起底侧58和支撑件59朝向密封器件50的内侧的变形。
从而，在存在封装本体的底侧上的应力和变形的情况下，柱60、60A的择优变形以及第一芯片56的衬底72保持刚性且不变形，抑制变形。
以这种方式，在第一芯片56和封装本体51之间创建了非耦合。
芯片56的底表面56A的角部上的柱60的布置保证了封装本体51的变形抑制行为与组装操作之间非常良好的折衷。在任何情况下，中心柱60A的布置保证了非常良好的抑制性能。
例如，在图10中，如图所示，可以使用三晶圆接合工艺在前端制程中制造密封器件50。图10关于外围柱60的形成。以下针对外围柱60的描述在任何情况下也都适用于单个中心柱60A，或者适用于以任何数量无论如何布置的柱。
图10示出了包括三个晶圆80、81和83的复合晶圆85。第一晶圆80经由玻璃熔块层82接合至第二晶圆81。第一晶圆80容纳多个第一芯片56的敏感结构68(包括固定电极71和移动电极70)，并且第二晶圆81操作为包围敏感部分68并将敏感部分与外部绝缘的盖。
柱60形成在第一晶圆80的外(底)表面上，并且第三晶圆83通过柱60接合至第一晶圆80。
图10的复合晶圆85如下所述进行制造。初始地，使用已知的光刻技术在第一晶圆80中形成敏感结构68；第一和第二晶圆80经由玻璃熔块层82接合到一起；经由干性抗蚀剂材料的旋涂或者经由已知光刻技术的限定，将柱60形成在第一晶圆80的外表面上，然后将第三晶圆83接合至第一晶圆80。
接下来，对图10的复合晶圆85进行切割以形成包括第一芯片56和支撑件59的复合芯片，该支撑件59操作为操控支撑件。将第二芯片57经由粘合层61接合至第一芯片56，并且将集合56+57+59固定至基础元件52的底侧58。最后，将顶盖53粘在顶部上。
作为备选，将包括多个ASIC的第四晶圆在切割之前接合至图10的复合晶圆85。
根据不同实施例，通过沉积高弹性材料(例如，干性抗蚀剂)的层(其随后被限定以形成柱)，可以使用光刻技术形成柱60。
在晶圆级形成非耦合结构(柱60、60A)的可能性能够以与已知密封器件的制造成本相当的制造成本实现高制造精度并且使得可以大规模地制造在生产线上稳定的MEMS部件。
最后，应清楚的是，在不背离由所附权利要求限定的本实用新型的范围的情况下，可以对所描述和所图示的器件和工艺进行修改和变化。
例如，密封器件的类型不受限制：具体地，可以设置单个芯片，直接或通过支撑件固定至基础元件52的底侧58。芯片(单个或复合)可以通过任何类型的MEMS或者通过任何其他半导体芯片(与封装件机械分离)来形成。
柱60可以是有机材料、抗蚀剂或者软胶，只要它们与硅相比具有高弹性即可。
此外，柱60的位置和数量可以变化。例如，柱60可以以与固定表面56A的边缘相距一定距离来布置，或者可以以不同的数量(例如，三个或五个)来布置，优选地以相对于芯片56、57的中心的对称位置来布置。

Claims (12)

1.一种半导体材料的密封器件，其特征在于，包括：
封装本体(51)，具有基础元件(52)；
半导体材料的第一芯片(56)；以及
至少一个柱元件(60；60A)，布置在所述第一芯片(56)和所述基础元件(52)之间并且将所述第一芯片(56)和所述基础元件(52)固定到一起，所述柱元件(60；60A)的杨氏模量低于所述第一芯片的杨氏模量。
2.根据权利要求1所述的器件，其特征在于，包括位于所述第一芯片(56)和所述封装本体(51)之间的空置空间。
3.根据权利要求1或2所述的器件，其特征在于，所述第一芯片(56)是MEMS。
4.根据权利要求1或2所述的器件，其特征在于，第二芯片(57)接合至所述第一芯片(56)。
5.根据权利要求1或2所述的器件，其特征在于，包括多个柱元件(60)，其中所述第一芯片(56)具有包括角部的矩形形状的固定表面(56A)，并且所述柱元件(60)被固定为与所述芯片(56)的所述固定表面(56A)的所述角部邻近。
6.根据权利要求1或2所述的器件，其特征在于，所述第一芯片(56)具有面对所述基础元件(58)的固定表面(56A)，其中所述柱元件被布置在中心(60A)处并且固定至所述第一芯片(56)的所述固定表面(56A)的中心部分。
7.根据权利要求1或2所述的器件，其特征在于，所述至少一个柱元件(60；60A)是有机材料、抗蚀剂或软胶的。
8.根据权利要求7所述的器件，其特征在于，所述至少一个柱元件(60；60A)是DAF层。
9.根据权利要求1或2所述的器件，其特征在于，所述封装本体(51)是陶瓷材料的。
10.根据权利要求1或2所述的器件，其特征在于，还包括支撑芯片(59)，所述支撑芯片(59)被布置在所述基础元件(52)与所述至少一个柱元件(60；60A)之间。
11.根据权利要求1或2所述的器件，其特征在于，所述柱元件(60；60A)的杨氏模量低于500MPa。
12.根据权利要求11所述的器件，其特征在于，所述柱元件(60；60A)的杨氏模量低于300MPa。
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