CN204834593U - Packaging mold structure - Google Patents
Packaging mold structure Download PDFInfo
- Publication number
- CN204834593U CN204834593U CN201520186088.0U CN201520186088U CN204834593U CN 204834593 U CN204834593 U CN 204834593U CN 201520186088 U CN201520186088 U CN 201520186088U CN 204834593 U CN204834593 U CN 204834593U
- Authority
- CN
- China
- Prior art keywords
- chip
- chipset
- lead frame
- upper cover
- mould group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004806 packaging method and process Methods 0.000 title description 5
- 239000000463 material Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims description 33
- 239000011248 coating agent Substances 0.000 claims description 18
- 238000000576 coating method Methods 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 239000004568 cement Substances 0.000 claims description 3
- 239000006260 foam Substances 0.000 claims description 3
- 239000004033 plastic Substances 0.000 claims description 3
- 239000000741 silica gel Substances 0.000 claims description 3
- 229910002027 silica gel Inorganic materials 0.000 claims description 3
- 239000002994 raw material Substances 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 abstract description 18
- 238000012858 packaging process Methods 0.000 abstract description 2
- 206010040007 Sense of oppression Diseases 0.000 abstract 1
- 238000000034 method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000010412 perfusion Effects 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 238000012797 qualification Methods 0.000 description 3
- 238000004513 sizing Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The utility model provides an encapsulation mould structure, be applicable to various chip package, mainly utilize the upper cover inner chamber top surface at the encapsulation mould group, utilize non-rigid material to be provided with the one deck buffer layer, when encapsulating after avoiding the chipset equipment to accomplish, can be because of the problem of difference in height between the upper cover inner chamber of chipset and encapsulation mould group, and the chip that causes the chipset leads to the fact the fracture because of receiving the powerful oppression of upper cover in the packaging process, or take place to need through the circumstances such as secondary operation clearance, and can effectively improve the product percent of pass and reduce the encapsulation cost outside, can also improve the thermal diffusivity of the chip module after the encapsulation is accomplished.
Description
Technical field
The utility model relates to a kind of die structure, particularly a kind of encapsulating mould being applicable to various chip package.
Background technology
Refer to shown in Fig. 1 to Fig. 3, chipset 2 mainly includes lead frame 21, chip 22, metal conductive member 23 and metal tie line 26, wherein, can utilize one deck sticker 25 that chip 22 is fixed on the top of lead frame 21 below lead frame 21 and chip 22, then between chip and metal conductive member 23, one deck sticker 24 also can be utilized to be fixed on above chip 22 by metal conductive member 23, and link between each component and sticker 24, the coating of 25 is all utilize machine one-stop operation to complete, no matter but be that machine completes or manually completes, the coating of sticker all can have the little bit different of quantity number, therefore cause whole chipset 2 complete and toast sizing after, the height H of each chipset 2 can have narrow difference, but encapsulating mould group 1 is generally divided into upper cover 11 and lower seat 12, upper cover 11 is in interior empty shape, inside is formed with dies cavity 13, must lead frame 21 part of chipset 2 be positioned over above the lower seat 12 of encapsulating mould group 1 exactly in the encapsulation process of chipset 2, then the upper cover of encapsulating mould group 1 is covered on chipset 2 and carries out perfusion encapsulation, under normal condition, Chip mold group 1 is after assembling fixedly completes, height H after deduction lead frame 21 must be equal to the inner chamber 13 height T of the upper cover 11 of encapsulating mould group 1, like this in perfusion encapsulation process, chip 22 can not because of inner chamber 13 height of the height H of chipset 2 in the upper cover 11 of encapsulating mould group 1, the cracked of chip 22 is caused under pressure compression, also inner chamber 13 height of the upper cover 11 of encapsulating mould group 1 can not be less than because of the height H of chipset 2, and in encapsulation process, allow packing colloid (not showing in figure) overflow be distributed in the upper strata of metal conductive member 23, and need do afterwards clearing up and processing to avoid thermal diffusivity limited, but sticker 24, the coating weight of 25 has the generation of error amount, so there is no way control each chipset 2 assembled after height H be bound to be equal to the upper cover 11 of encapsulating mould group 1 inner chamber 13 height T, and easily cause aforementioned puzzlement structure.
Prior art
Encapsulating mould group 1
Upper cover 11
Lower seat 12
Inner chamber 13
End face 14
Chipset 2
Lead frame 21
Chip 22
Metal conductive member 23
Sticker 24.25
Metal tie line 26
The utility model
Encapsulating mould group 10
Upper cover 101
Lower seat 102
Upper surface 1021
Inner chamber 1011
Inner top surface 1012
Resilient coating 1013
Chipset 20
Lead frame 201
Chip 202
Metal conductive member 203
Lead portion 2031
Sticker 204.205
Metal tie line 206
Utility model content
Technical problem to be solved in the utility model is the problems referred to above for prior art, a kind of die structure is provided, except can effectively solve except the problem of difference in height, chip effectively can also be avoided in encapsulation process also to need clean processing after a packaging process by the cracked or metal conductive member of high pressure compressing, and then improve conforming product rate, encapsulation speed and reduce costs.
To achieve these goals, the utility model provides a kind of die structure, wherein, comprising:
One chipset, is wherein provided with a lead frame, is installed with a chip above this lead frame, and this lead frame and this chip utilize sticker to be set firmly;
Above this chip, be installed with a metal conductive member, and this metal conductive member and this chip chamber utilize sticker to be adhesively fixed, and this metal conductive member has the lead portion making this chip and this lead frame reach electrically connect;
One for the metal tie line of the electrically connect of this chip and this lead frame, and one end links the top of this chip, and the other end links this lead frame;
One encapsulating mould group, includes upper cover and lower seat, and the upper surface of lower seat is placed for the lead frame of this chipset;
This upper cover is interior empty shape, and inside is formed with inner chamber, and is provided with in the inner top surface of this upper cover one deck to be covered in oppressive force when this chipset encapsulates resilient coating for cushioning this upper cover.
Above-mentioned die structure, wherein, this resilient coating is non-rigid material.
Above-mentioned die structure, wherein, this resilient coating is silica gel, foam, plastic cement or the raw material with elastic returning.
Beneficial functional of the present utility model is:
The utility model is applicable to the encapsulating mould of various chip package, main utilization is at the upper cover cavity end face of encapsulating mould group, non-rigid material is utilized to be provided with one deck resilient coating, effective solution chipset in encapsulation process outside the issuable problem such as cracked and dirty, and then improves chip module qualification rate, improve and make speed, reduce packaging cost and improve the advantages such as chip module integral heat sink.
Below in conjunction with the drawings and specific embodiments, the utility model is described in detail, but not as to restriction of the present utility model.
Accompanying drawing explanation
Fig. 1 is the exploded side schematic diagram of chipset together with encapsulating mould group of prior art die structure;
Fig. 2 is the side-looking combination schematic diagram of the encapsulating mould group of prior art die structure;
Fig. 3 is the side-looking combination schematic diagram of the chipset of prior art die structure;
Fig. 4 is the exploded side schematic diagram of chipset together with encapsulating mould group of the utility model die structure;
Fig. 5 is the side-looking combination schematic diagram that the chipset of the utility model die structure is positioned at encapsulating mould group;
Fig. 6 is the side-looking combination schematic diagram that the chipset of die structure of the present utility model has encapsulated.
Wherein, Reference numeral
Embodiment
Below in conjunction with accompanying drawing, structural principle of the present invention and operation principle are described in detail:
Refer to shown in Fig. 4, Fig. 5 and Fig. 6, mainly include a lead frame 201, be installed with a chip 202 above this lead frame 201, this chip 202 utilizes sticker 205 to be fixedly arranged on the top of lead frame 201;
Also a metal conductive member (CLIP) 203 is installed with above this chip 202, also sticker 204 is utilized to be adhesively fixed between this metal conductive member 203 and chip 202, and this metal conductive member 203 has lead portion 2031, utilize this lead portion 2031, chip 202 and lead frame 201 can be impelled to reach electrically connect;
Have a metal tie line 206, one end links chip 202 top, and the other end links lead frame 201, utilizes this metal tie line 206 also can reach the electrically connect of chip 202 and lead frame 201, this kind utilizes metal conductive member 203 mutually to form electrically connect with metal tie line 206 and lead frame simultaneously, be applicable to as insulated gate bipolar transistor (IGBT, or metal-oxide half field effect transistor (MOSFET InsulatedGateBipolarTransistor), etc. Metal-Oxide-SemiconductorField-EffectTransistor) on semiconductor transistor, because these two kinds of transistor modulars have source electrode to follow the design of grid on chip structure, wherein metal conductive member 203 is exactly to link the electrically connect between source electrode and lead frame 201, metal tie line 206 is then the electrically connect in order to link between grid and lead frame 201,
What utilize lead frame 201, chip 202, metal conductive member 203, sticker 204.205 and metal tie line 206 to form is then the chipset 20 of pending encapsulation;
Have an encapsulating mould group 10, include upper cover 101 and lower seat 102, the upper surface 1021 of lower seat 102 can be placed for the lead frame 21 of chipset 20;
Upper cover 101 is in interior empty shape, inside has inner chamber 1011, and being provided with one deck resilient coating 1013 in the inner top surface 1012 of upper cover 101 inner chamber 1011, this resilient coating 1013 utilizes non-rigid material to process, as soft in materials such as silica gel, foam, plastic cement and have the material of spring return characteristic;
After chipset 20 has been assembled, and via just carrying out the canned program of chipset 20 after baking sizing, now just chipset 20 is positioned on the upper surface 1021 of lower seat 102 of encapsulating mould group 10, and then the upper cover 101 of encapsulating mould group 10 is covered on the lower seat 102 of encapsulating mould group 10, and make chipset 20 be sealed in the inner chamber 1011 of the upper cover 101 of encapsulating mould group 10, and lead frame 201 both sides of chipset 20 are exposed, then the perfusion encapsulation of sealing is carried out, sayed just as prior art, the height of the chipset 20 after baking sizing is easily because of sticker 204, the consumption error amount of 205 and have difference slightly, inner chamber 1011 height of the upper cover 101 of encapsulating mould group 10 might not be equal to, now because the utility model is provided with one deck resilient coating 1013 at the end face 1012 of the inner chamber 1011 of the upper cover 101 of encapsulating mould group 10, and the material of this resilient coating 1013 processed by non-rigid material, therefore the shortcoming of the height error value of chipset 20 can be made up, when the upper cover 101 of encapsulating mould group 10 is covered on chipset 20, this resilient coating 1013 just can cover the top layer of the metal conductive member 203 being pressed on chipset 20, to be processed by non-rigid material due to this resilient coating 1013 and there is elastic force, therefore can be closely attached on the surface of metal conductive member 203 completely but can't oppressive force be caused, therefore when when carrying out sealing perfusion encapsulation, sealing can't infiltrate the surface of metal conductive member 203, also the cracked of the chip 202 of chipset 20 can not be caused because of the compressing of brute force, therefore after packaging is accomplished, the top layer of metal conductive member 203 does not have sticking of sealing, and do not need carry out secondary surface cleaning and effectively cut down finished cost, and then raising processing speed, and the excellent radiating effect of the rear chipset 20 of encapsulation can be possessed, simultaneously because there is the protection of resilient coating 1013, also the pressurized of the chip 202 of chipset 20 can not be caused to damage, and then improve the qualification rate of the chipset 20 after encapsulation.
In sum, die structure of the present utility model, compared with the encapsulating mould of prior art, effectively can not only reduce the damage of chipset 20 in encapsulation process and improve outside qualification rate, also chipset 20 can be guaranteed not need after packaging to have secondary surface cleaning again and effectively improve processing speed and reduce packaging cost, can keep the best thermal diffusivity of chipset 20, it has the novelty of structure, the practicality of industry and usability undoubtedly simultaneously.
Certainly; the utility model also can have other various embodiments; when not deviating from the utility model spirit and essence thereof; those of ordinary skill in the art are when making various corresponding change and distortion according to the utility model, but these change accordingly and are out of shape the protection range that all should belong to the claim appended by the utility model.
Claims (3)
1. a die structure, is characterized in that, comprising:
One chipset, is wherein provided with a lead frame, is installed with a chip above this lead frame, and this lead frame and this chip utilize sticker to be set firmly;
Above this chip, be installed with a metal conductive member, and this metal conductive member and this chip chamber utilize sticker to be adhesively fixed, and this metal conductive member has the lead portion making this chip and this lead frame electrically connect;
One for the metal tie line of the electrically connect of this chip and this lead frame, and one end links the top of this chip, and the other end links this lead frame;
One encapsulating mould group, includes upper cover and lower seat, and the upper surface of this lower seat is placed for this lead frame of this chipset;
This upper cover is interior empty shape, and inside is formed with inner chamber, and is provided with in the inner top surface of this upper cover one deck to be covered in oppressive force when this chipset encapsulates resilient coating for cushioning this upper cover.
2. die structure as claimed in claim 1, it is characterized in that, this resilient coating is non-rigid material.
3. die structure as claimed in claim 1, it is characterized in that, this resilient coating is silica gel, foam, plastic cement or the raw material with elastic returning.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103205582U TWM504352U (en) | 2014-03-28 | 2014-03-28 | Improved structure of packaging mold |
| TW103205582 | 2014-03-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204834593U true CN204834593U (en) | 2015-12-02 |
Family
ID=54152214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520186088.0U Expired - Fee Related CN204834593U (en) | 2014-03-28 | 2015-03-30 | Packaging mold structure |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN204834593U (en) |
| TW (1) | TWM504352U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107403760A (en) * | 2017-07-28 | 2017-11-28 | 维沃移动通信有限公司 | A kind of chip protection structure and terminal device |
-
2014
- 2014-03-28 TW TW103205582U patent/TWM504352U/en not_active IP Right Cessation
-
2015
- 2015-03-30 CN CN201520186088.0U patent/CN204834593U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107403760A (en) * | 2017-07-28 | 2017-11-28 | 维沃移动通信有限公司 | A kind of chip protection structure and terminal device |
Also Published As
| Publication number | Publication date |
|---|---|
| TWM504352U (en) | 2015-07-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151202 Termination date: 20160330 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |