JP2006324401A5 - - Google Patents
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- JP2006324401A5 JP2006324401A5 JP2005145355A JP2005145355A JP2006324401A5 JP 2006324401 A5 JP2006324401 A5 JP 2006324401A5 JP 2005145355 A JP2005145355 A JP 2005145355A JP 2005145355 A JP2005145355 A JP 2005145355A JP 2006324401 A5 JP2006324401 A5 JP 2006324401A5
- Authority
- JP
- Japan
- Prior art keywords
- mold resin
- chip
- resin
- semiconductor element
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Claims (6)
前記パワー用半導体素子を制御する制御用ＩＣ（Integrated Circuit）が形成された制御用ＩＣチップと、
前記パワー用半導体素子チップおよび前記制御用ＩＣチップを封止したモールド樹脂パッケージと
を備え、
前記モールド樹脂パッケージには、
前記制御用ＩＣチップを封止する第１のモールド樹脂と、
前記パワー用半導体素子チップを封止する第２のモールド樹脂と
が含まれ、
前記第１のモールド樹脂と、前記第２のモールド樹脂は、同種のエポキシ樹脂で構成されており、
前記第２のモールド樹脂の熱伝導率は、前記第１のモールド樹脂の熱伝導率よりも高い
半導体装置。 A power semiconductor element chip on which a power semiconductor element is formed;
A control IC chip on which a control IC (Integrated Circuit) for controlling the power semiconductor element is formed;
A mold resin package encapsulating the power semiconductor element chip and the control IC chip;
In the mold resin package,
A first mold resin for sealing the control IC chip;
And a second mold resin for sealing the power semiconductor element chip,
The first mold resin and the second mold resin are made of the same kind of epoxy resin,
A semiconductor device in which the thermal conductivity of the second mold resin is higher than the thermal conductivity of the first mold resin.
前記第２のモールド樹脂の前記充填材の充填率が、前記第１のモールド樹脂の前記充填材の充填率よりも大きいことThe filling rate of the filler of the second mold resin is larger than the filling rate of the filler of the first mold resin.
を特徴とする請求項１記載の半導体装置。The semiconductor device according to claim 1.
（ｂ）前記パワー用半導体素子チップと前記リードフレームと、および、前記制御用ＩＣチップと前記リードフレームと、をそれぞれワイヤボンディングする工程と、
（ｃ）ワイヤボンディングされた前記パワー用半導体素子チップ、前記制御用ＩＣチップおよび前記リードフレームを、金型内の樹脂注入空間に配置する工程と、
（ｄ）第１のモールド樹脂を前記樹脂注入空間に注入して、前記制御用ＩＣチップを前記第１のモールド樹脂により封止する工程と、
（ｅ）前記第１のモールド樹脂と同種のエポキシ樹脂で構成される第２のモールド樹脂を前記樹脂注入空間に注入して、前記パワー用半導体素子チップを前記第２のモールド樹脂により封止する工程と
を備え、
工程（ｄ）の注入時における前記第１のモールド樹脂の粘度は、工程（ｅ）の注入時における前記第２のモールド樹脂の粘度よりも低く、
前記第２のモールド樹脂の熱伝導率は、前記第１のモールド樹脂の熱伝導率よりも高い
半導体装置の製造方法。 (A) Die bonding a power semiconductor element chip on which a power semiconductor element is formed and a control IC chip on which a control IC (Integrated Circuit) for controlling the power semiconductor element is formed on a lead frame And a process of
(B) wire bonding the power semiconductor element chip and the lead frame, and the control IC chip and the lead frame;
(C) placing the power-bonded semiconductor element chip, the control IC chip, and the lead frame that are wire-bonded in a resin injection space in a mold;
(D) injecting a first mold resin into the resin injection space and sealing the control IC chip with the first mold resin;
(E) A second mold resin composed of the same type of epoxy resin as the first mold resin is injected into the resin injection space, and the power semiconductor element chip is sealed with the second mold resin. Process and
With
The viscosity of the first mold resin at the time of injection in the step (d) is lower than the viscosity of the second mold resin at the time of injection in the step (e),
The method for manufacturing a semiconductor device , wherein the thermal conductivity of the second mold resin is higher than the thermal conductivity of the first mold resin .
（ｆ）前記樹脂注入空間に注入口を介して連結可能なチャンバ内に、前記第１のモールド樹脂の原料となる第１タブレットと前記第２のモールド樹脂の原料となる第２タブレットとを並べて配置する工程と、 (F) A first tablet that is a raw material of the first mold resin and a second tablet that is a raw material of the second mold resin are arranged in a chamber connectable to the resin injection space via an injection port. Arranging, and
（ｇ）前記チャンバ内を加熱して前記第１及び第２タブレットを溶解させる工程と (G) heating the inside of the chamber to dissolve the first and second tablets;
を備え、With
前記注入口から見た前記第１及び第２タブレットの配置が、前記樹脂注入空間内での前記制御用ＩＣチップおよび前記パワー用半導体素子チップの配置に対応した The arrangement of the first and second tablets viewed from the injection port corresponds to the arrangement of the control IC chip and the power semiconductor element chip in the resin injection space.
半導体装置の製造方法。A method for manufacturing a semiconductor device.
（ｈ）第３のモールド樹脂を前記樹脂注入空間に注入して、樹脂注入空間のうち前記制御用ＩＣチップおよび前記パワー用半導体素子チップ以外の他の部分を前記第３のモールド樹脂により封止する工程
をさらに備え、
工程（ｈ）の注入時における前記第３のモールド樹脂の粘度は、工程（ｅ）の注入時における前記第２のモールド樹脂の粘度よりも低い
半導体装置の製造方法。 A method of manufacturing a semiconductor device according to claim 3,
(H) Injecting the third mold resin into the resin injection space, and sealing the other part of the resin injection space other than the control IC chip and the power semiconductor element chip with the third mold resin. Process
Further comprising
The method of manufacturing a semiconductor device, wherein the viscosity of the third mold resin at the time of injection in the step (h) is lower than the viscosity of the second mold resin at the time of injection in the step (e) .
前記樹脂注入空間のうち前記制御用ＩＣチップの下方には、前記金型の凸部が設けられた A convex portion of the mold is provided below the control IC chip in the resin injection space.
半導体装置の製造方法。A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005145355A JP4463146B2 (en) | 2005-05-18 | 2005-05-18 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005145355A JP4463146B2 (en) | 2005-05-18 | 2005-05-18 | Manufacturing method of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006324401A JP2006324401A (en) | 2006-11-30 |
| JP2006324401A5 true JP2006324401A5 (en) | 2007-11-29 |
| JP4463146B2 JP4463146B2 (en) | 2010-05-12 |
Family
ID=37543865
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005145355A Active JP4463146B2 (en) | 2005-05-18 | 2005-05-18 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4463146B2 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101963271B1 (en) * | 2014-01-28 | 2019-07-31 | 삼성전기주식회사 | Power module package and the method of manufacturing thereof |
| US9716072B2 (en) * | 2014-05-12 | 2017-07-25 | Mitsubishi Electric Corporation | Power semiconductor device and method of manufacturing the same |
| JP6824913B2 (en) * | 2016-02-09 | 2021-02-03 | 三菱電機株式会社 | Power semiconductor devices and their manufacturing methods |
| CN108701661A (en) | 2016-03-07 | 2018-10-23 | 三菱电机株式会社 | The manufacturing method of semiconductor device and semiconductor device |
| JP6667401B2 (en) * | 2016-08-19 | 2020-03-18 | 三菱電機株式会社 | Method for manufacturing power semiconductor device |
| CN109300795B (en) * | 2018-09-27 | 2020-05-19 | 江苏矽智半导体科技有限公司 | Semiconductor power device package and preparation method thereof |
| CN115763381B (en) * | 2022-11-17 | 2024-03-08 | 海信家电集团股份有限公司 | Intelligent power module and equipment |
-
2005
- 2005-05-18 JP JP2005145355A patent/JP4463146B2/en active Active
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