CN203491253U - Plastic packaging structure for semiconductors - Google Patents
Plastic packaging structure for semiconductors Download PDFInfo
- Publication number
- CN203491253U CN203491253U CN201320454363.3U CN201320454363U CN203491253U CN 203491253 U CN203491253 U CN 203491253U CN 201320454363 U CN201320454363 U CN 201320454363U CN 203491253 U CN203491253 U CN 203491253U
- Authority
- CN
- China
- Prior art keywords
- lead frame
- groove
- plastic
- sealed body
- package structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a plastic packaging structure for semiconductors, which comprises a lead frame, a chip arranged on the lead frame, and a plastic-sealed body wrapped on the outside of the lead frame. The contact surface of the lead frame with the plastic-sealed body is provided with a plurality of grooves, wherein the distance between every two adjacent grooves is greater than 0.120 millimeters. The plastic-sealed body is filled in all the grooves. According to the technical scheme of the utility model, due to the adoption of the grooves, the combined area of the lead frame and the plastic-sealed body is increased, so that the combination force between the lead frame and the plastic-sealed body is increased. Meanwhile, the resistant property of a product to the layering phenomenon is improved and the reliability of the product is also increased.
Description
Technical field
The utility model relates to a kind of semiconductor packaging, relates in particular to a kind of semiconductor plastic package structure.
Background technology
Semiconductor plastic package be by epoxy resin under molten condition, chip (Die) and lead frame (Lead Frame) are wrapped up, physics and electic protection are provided, prevent external interference.
The mould of plastic packaging is divided into upper and lower mould, the die cavity that on mould, with good grounds package body sizes is reserved in advance, and its working temperature is conventionally within the scope of 165 ℃～185 ℃.The lead frame 42 of needs encapsulation is placed on mould, then puts into solid epoxy 41 biscuits, then closed die apply clamping pressure (at least more than 30 tons).After matched moulds, give on injection moulding bar and exert pressure, epoxy resin 41 starts to melt under height high pressure, so under the effect of injection moulding bar, epoxy resin 41 is squeezed in die cavity.Because the characteristic of epoxy resin 41 is to solidify after first becoming molten condition again, so after in being squeezed into chamber, it will solidify again, form our needed overall dimension, as shown in Figure 1, be QFN encapsulation sectional structure chart.
In current plastic semiconductor packaging technology, plastic packaging resin 41 and lead frame 42 combinations, form confined space, reduces the impact of external environment condition on chip.The size of plastic packaging resin 41 and lead frame 42 bond strengths, has determined the reliability of product to a great extent.Due to thermal coefficient of expansion impact between material, there is larger internal stress in interiors of products.Externally, under stress (as HTHP) condition, internal stress aggravates, and the junction of different materials is easy to occur crackle (layering).Layering, without any processing, after plastic packaging material is combined with lead frame, is found in conventional lead frame surface in completing encapsulation or reliability test process, has influence on product reliability.
Utility model content
The utility model object is to provide a kind of semiconductor plastic package structure, by the improvement of structure, can improve the reliability of product, reduces defective products rate.
For achieving the above object, the technical solution adopted in the utility model is: a kind of semiconductor plastic package structure, comprise lead frame, be positioned at the chip on lead frame and wrap up the plastic-sealed body in outside, the surface that described lead frame contacts with described plastic-sealed body is provided with several grooves, distance between adjacent described groove sideline is greater than 0.120 millimeter, and described plastic-sealed body is filled described in each in groove.
In an embodiment, described groove is U-shaped groove therein, its degree of depth be place, this groove place leadframe thickness 1/5～2/3.
In an embodiment, described groove is positioned at front or the dorsal part of described lead frame, in display mode, is distributed on described lead frame therein.
Further, rounded, the rectangle in described groove cross section, polygon, Long Circle, strip, one or more in petal.
Because technique scheme is used, the utility model compared with prior art has following advantages:
1. the utility model arranges groove on lead frame and plastic-sealed body contact surface, utilization sink to increase the bonded area between plastic-sealed body and lead frame, thereby improve critical adhesion between the two, strengthen product and under the condition of inside and outside stress, resist the ability of layering, improve product reliability;
2. the shape of groove is determined according to the shape of product lead frame with distribution, can realize by etching, is uniformly distributed, easy to process, is easy to realize.
Accompanying drawing explanation
Fig. 1 is QFN encapsulating structure schematic diagram in the utility model background technology;
Fig. 2 is the structural representation of lead frame in the utility model embodiment mono-;
Fig. 3 is the A-A cross-sectional schematic of Fig. 2;
Fig. 4 is the structural representation of lead frame in the utility model embodiment bis-;
Fig. 5 is the structural representation of lead frame in the utility model embodiment tri-.
Wherein: 11, lead frame; 12, the petal U-shaped groove of pintongs; 13, chip; 14, L-type strip groove; 15, oblong groove; 21, lead frame; 22, strip groove; 23, circle; 24, Long Circle; 31, lead frame; 32, groove; 33, chip; 41, epoxy resin.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further described:
Embodiment mono-: shown in Fig. 2,3, a kind of semiconductor plastic package structure, comprise lead frame 11, be positioned at the chip 13 on lead frame 11 and wrap up the plastic-sealed body in outside, the surface that described lead frame 11 contacts with described plastic-sealed body is provided with several grooves 12, distance between adjacent described groove sideline is greater than 0.120 millimeter, and described plastic-sealed body is filled described in each in groove.
As shown in Figure 2, in the present embodiment, treat that plastic packaging product is QFN3 * 4.Described lead frame 11 fronts, be positioned at described chip 13 clear area around, in display mode, be evenly equipped with the petal U-shaped groove 12 of pintongs and L-type strip groove 14, its degree of depth be groove place place lead frame 11 thickness 1/2(as shown in Figure 3), the degree of depth is 0.101 millimeter, and the distance between the petal U-shaped groove of adjacent described pintongs 12 sidelines is 0.125 millimeter.
Distribution groove as much as possible on lead frame 11, as long as meet the lowest critical value that the distance between adjacent notches sideline is greater than 0.120 millimeter, on the pin place lead frame 21 at chip, also can be provided with oblong groove 15, with this, increase the bonded area between lead frame 11 and plastic-sealed body, effectively improve critical adhesion between the two.Adding man-hour, the groove on lead frame 21 obtains by etch process, and epoxy resin is full of whole mold cavity in molten condition, realizes the filling to each groove.
Embodiment bis-: shown in Figure 4, a kind of semiconductor plastic package structure, comprise lead frame 21, be positioned at the chip on lead frame 21 and wrap up the plastic-sealed body in outside, the surface that described lead frame 21 contacts with described plastic-sealed body is provided with several grooves, distance between adjacent described groove sideline is greater than 0.120 millimeter, and described plastic-sealed body is filled described in each in groove.
In the present embodiment, described lead frame 21 dorsal parts, opposite side with respect to described chip, be distributed with U-shaped strip groove 22, groove width is 5mils(0.127 millimeter), the degree of depth be place, this groove place lead frame 21 thickness 1/3, surround one group of diagonal angle, the zone line of strip groove 22 is evenly equipped with circular groove 23, and the distance between adjacent described groove sideline is 0.150 millimeter.On the pin place lead frame 21 of chip, be provided with Long Circle groove 24, groove width is 5mils(0.127 millimeter), the degree of depth be place, this groove place lead frame 21 thickness 1/3, as shown in Figure 4.
Embodiment tri-, shown in Figure 4, a kind of semiconductor plastic package structure, its structure and embodiment mono-are similar, difference is: described groove 32 is that hexagon and foursquare groove 32 constitute by cross section, intersect and be distributed in chip 33 idle region around, 0.130 millimeter of the distance between adjacent described groove 32 sidelines.
Embodiment has only expressed concentrated execution mode of the present utility model in sum, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the utility model the scope of the claims.It should be noted that for the person of ordinary skill of the art, not tying down under the prerequisite of the utility model design, can also make some distortion and improvement, these are all to belong to protection range of the present utility model.Therefore, the protection range of the utility model patent should be as the criterion with claim.
Claims (5)
1. a semiconductor plastic package structure, comprise lead frame, be positioned at the chip on lead frame and wrap up the plastic-sealed body in outside, it is characterized in that: the surface that described lead frame contacts with described plastic-sealed body is provided with several grooves, distance between adjacent described groove sideline is greater than 0.120 millimeter, and described plastic-sealed body is filled described in each in groove.
2. semiconductor plastic package structure according to claim 1, is characterized in that: described groove is U-shaped groove, its degree of depth be place, this groove place leadframe thickness 1/5～2/3.
3. semiconductor plastic package structure according to claim 2, is characterized in that: described groove is positioned at front or the dorsal part of described lead frame, in display mode, is distributed on described lead frame.
4. semiconductor plastic package structure according to claim 1, is characterized in that: described groove is positioned at front or the dorsal part of described lead frame, in display mode, is distributed on described lead frame.
5. according to the semiconductor plastic package structure described in any one in claim 1～4, it is characterized in that: described groove cross section is rounded, one or more in rectangle, polygon, Long Circle, strip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320454363.3U CN203491253U (en) | 2013-07-26 | 2013-07-26 | Plastic packaging structure for semiconductors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320454363.3U CN203491253U (en) | 2013-07-26 | 2013-07-26 | Plastic packaging structure for semiconductors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203491253U true CN203491253U (en) | 2014-03-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320454363.3U Expired - Lifetime CN203491253U (en) | 2013-07-26 | 2013-07-26 | Plastic packaging structure for semiconductors |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203491253U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105938826A (en) * | 2016-06-14 | 2016-09-14 | 上海凯虹科技电子有限公司 | Lead frame for improving layering of frame surface and plastic package body and package body |
| CN111370384A (en) * | 2020-05-09 | 2020-07-03 | 天水华洋电子科技股份有限公司 | Anti-layering lead frame structure design |
| CN114864533A (en) * | 2022-04-29 | 2022-08-05 | 武汉新芯集成电路制造有限公司 | Lead frame and semiconductor device |
-
2013
- 2013-07-26 CN CN201320454363.3U patent/CN203491253U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105938826A (en) * | 2016-06-14 | 2016-09-14 | 上海凯虹科技电子有限公司 | Lead frame for improving layering of frame surface and plastic package body and package body |
| CN111370384A (en) * | 2020-05-09 | 2020-07-03 | 天水华洋电子科技股份有限公司 | Anti-layering lead frame structure design |
| CN114864533A (en) * | 2022-04-29 | 2022-08-05 | 武汉新芯集成电路制造有限公司 | Lead frame and semiconductor device |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140319 |
|
| CX01 | Expiry of patent term |