CN104465417A - Method for encapsulating semiconductor structure through encapsulating module - Google Patents
Method for encapsulating semiconductor structure through encapsulating module Download PDFInfo
- Publication number
- CN104465417A CN104465417A CN201410780793.3A CN201410780793A CN104465417A CN 104465417 A CN104465417 A CN 104465417A CN 201410780793 A CN201410780793 A CN 201410780793A CN 104465417 A CN104465417 A CN 104465417A
- Authority
- CN
- China
- Prior art keywords
- even surface
- substrate
- package module
- encapsulating
- die cavity
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a method for encapsulating a semiconductor structure through an encapsulating module and belongs to the technical field of encapsulating chips on substrates to form semiconductors. An upper encapsulating module body and a lower encapsulating module body are adopted in the method for encapsulating the semiconductor structure through the encapsulating module, and the encapsulating module is provided with a joint face, a smooth face and a cavity. The smooth face is a curved surface tangent to the joint face and is arranged at an opening of the cavity, and when the encapsulating module is connected with a complete substrate carrying a chip, the joint face is in contact with and presses the substrate. The smooth face and the joint face are connected to form a tangent line, and the distance, in tangent between 0.78 mm and 1.85 mm, of the section of the connection part of the smooth face and the joint face is partitioned. The cavity is filled with sealing glue for encapsulating the chip on the substrate. When the surface of the substrate is pressurized by the encapsulating module through the joint face, the surface in contact with the substrate is the smooth joint face, so that the pressure borne by the substrate is lowered, and the semiconductor encapsulating structure cannot be damaged.
Description
Technical field
The present invention relates to a kind of method of package module encapsulated semiconductor structure, belong to technical field chip package being formed on substrate semiconductor device.
Background technology
Package module is used in normal enclosed chip process, and package module has a die cavity and a land area.Pressurize after land area contacts with substrate, die cavity is full of fluid sealant.Fluid sealant is cooled and solidifies, and is fixed on substrate.
In the process of the module package substrate of usual encapsulating mould, the module of encapsulating mould exerts oneself the surface of compacting substrate, after fully contacting with substrate surface, in module, to inject fluid sealant.Fluid sealant, cool and solidify and be fixed on substrate.But, if there is the module of mould to run into the substrate surface having moderate finite deformation, module more firmly compacting substrate will there will be many problems.Such as, the shape of contact is an acute angle, will occur many shortcomings:
The first, when encapsulating mould module firmly lower press contacts substrate, serious substrate surface has been out of shape in contact.Modular surface land area part descends compressive strain substrate fast, if the die cavity limit of module is an acute angle.The position that sharp acute angle contacts with substrate produces huge pressure, compresses into the deformation position of substrate.This pressure can cause the packed chip of substrate surface, gold thread and substrate tie point to be subject to larger damage.
If the second contact portion substrate has a larger distortion, contact with sharp die cavity acute angle, soft substrate surface treatment layer is by under crunch effect, and inner wire layer may expand and stripper surface processing layer.
The fluid sealant of three, filling in die module aspect die cavity is in cooling and process of setting, and fluid sealant causes larger impact to the acute angle moulding section that mold cavity is sharp, therefore may shorten the life-span of mould.
If the 4th die module acute angle forming area is damaged, the quality of semiconductor package will be had a strong impact on.
Summary of the invention
In order to overcome problems of the prior art, the invention provides a kind of method of package module encapsulated semiconductor structure, this package module to be pressurizeed substrate surface by land area, and die cavity has even surface and is connected with its matched moulds surface.When module land area contact substrate pressurization, what substrate touched is smooth land area, thus reduces substrate bearing pressure, can not cause harmful effect to semiconductor package.
The technical solution used in the present invention is: a kind of method of package module encapsulated semiconductor structure, package module chip package at substrate, form a complete semiconductor device, described package module comprises package module and lower package module, package module has land area, even surface and a die cavity, even surface is a curved surface tangent with land area and is placed in the opening part of die cavity, and when package module is connected with the full substrate carrying chip, land area contacts and presses substrate; The wall end face of described die cavity inside is connected with wall side, the wall end face of die cavity (110) inside is on substrate opposite, the wall side of die cavity inside is connected with even surface, wall end face and the wall side of die cavity inside are interconnected to form an angle, even surface is connected with a point of contact with land area, and the distance of interconnective point of contact between 0.78-1.85 millimeter is separated; One is filled chip package at on-chip fluid sealant in described die cavity.
Described even surface adopts the first even surface, or adopts the combining structure of the first even surface, the second even surface and the 3rd even surface continuous transition.
When described first even surface adopts circular surfaces a part of, a part for the second even surface and the 3rd even surface-also adopt circular surfaces, the range of curvature radius of circular surfaces is from 0.1-2.0 millimeter.
When described first even surface adopts oval surface a part of, the second even surface and the 3rd even surface also adopt a part for oval surface, and oval main shaft scope is from 0.1-1.17 millimeter, and cotta scope is from 0.1-1.0 millimeter.
The invention has the beneficial effects as follows: the method for this package module encapsulated semiconductor structure adopts upper package module and lower package module, and package module has land area, even surface and a die cavity.Even surface is a curved surface tangent with land area and is placed in the opening part of die cavity, and when package module is connected with the full substrate carrying chip, land area contacts and presses substrate.Even surface is connected with a point of contact with land area, and interconnective distance of cutting between 0.78-1.85 millimeter is separated.One is filled chip package at on-chip fluid sealant in die cavity.When this package module is by land area pressurization substrate surface, what substrate touched is smooth land area, thus reduces substrate bearing pressure, can not cause harmful effect to semiconductor package.
accompanying drawing explanation:
Fig. 1 is usually the package module of the known sharp acute angle of band.
Fig. 2 is a kind of structure of package module encapsulated semiconductor.
Fig. 3 is a shaping figure of encapsulated semiconductor.
Fig. 4 is the A enlarged drawing (first scheme) in Fig. 2.
Fig. 5 is the A enlarged drawing (alternative plan) in Fig. 2.
Fig. 6 is the B enlarged drawing in Fig. 3.
In figure: 100, upper package module, 102, chip, 104, substrate, 108, land area, 110, die cavity, 112, fluid sealant, the 114, first even surface, 116, fluid sealant side, 118, the second even surface, 120, packing space, 122, lower package module, 124, gold thread, 126, semiconductor package bottom surface, 132, the 3rd even surface, 134, wall end face, 136, wall side, 138, angle, 140, fluid sealant end face, 142, fluid sealant angle, T1, T2, T3, T4, T5, T6, point of contact.
Embodiment
Fig. 1 is usually the package module of the known sharp acute angle of band.General semiconductor package module has an acute angle P1 in cavity side, acute angle P1 contacts with the substrate surface of distortion, substrate structure bears larger pressure, the chip causing substrate surface packed, gold thread are connected with substrate and are subject to larger damage, as chip and gold thread solder joint come off, or damage from substrate or peel off.
Fig. 2 is a kind of structure of package module encapsulated semiconductor.Fig. 3 is a shaping figure of encapsulated semiconductor.Package module comprises a upper package module 100 and lower package module 122.Lower package module 122 is for carrying substrates 104.Upper package module 100 has a land area 108 and a die cavity 110.Upper package module 100 and lower package module 122 can keep substrate 104 to be fixed between package module 100 and lower package module 122.In addition, when upper package module 100 and lower package module 122 are connected, land area 108 contacts and the substrate 104 that pressurizes, so that substrate 104 is compacted between upper package module 100 and lower package module 122.Die cavity 110 for filling a kind of fluid sealant 112 (as shown in Figure 3) so that fluid sealant 112 is arranged on substrate 104, for the protection of packaged chip 102 and gold thread 124.
Fig. 4 is the A enlarged drawing (first scheme) in Fig. 2.As shown in Fig. 4, upper package module 100 has the first even surface 114 of contact die cavity 110.First even surface 114 is tangent planes of land area 108.When the first even surface 114 is tangent with land area 108, upper package module 100 contacts and the substrate 104 that pressurizes, contact substrate 104 be the border of the first even surface 114, it is the tangent plane of land area 108 instead of the sharp shape (acute angle P1 as shown in Figure 1) at usual known technology.First even surface 114 does not damage surface-treated layer (pad of gold thread 124) and is placed in the metal structure (chip 102) on substrate 104.First even surface 114 has a level and smooth appearance, avoids surface-treated layer to be damaged and peels off.
When die cavity 110 (as shown in Figure 2) is full of the fluid sealant 112 of fusing, the fluid sealant of fusing is filled between substrate 104 and the first even surface 114, packing space 120 also contacts the first even surface 114, so that the contact area between the fluid sealant and upper package module 100 of fusing is increased.Thus, the fluid sealant of packing space 120 is extended on substrate 104 by upper package module 100, reduce substrate 104 and bear pressure, and pressure extend to be placed in surface-treated layer and packed substrate 104 metal structure on so that surface-treated layer and metal structure by not damage by too much pressure.
The wall end face 134 of die cavity 110 inside is connected with the wall side 136 of die cavity 110 inside.Inner wall end face 134 is on substrate 104 opposite.Inner wall side 136 is the tangent plane of the first even surface 114.Have a preset distance D1 between angle 138 summit be interconnected to form between the wall end face 134 and the wall side 136 of inside of inside and the first even surface 114 and the tangent tangent line (being point of contact T1 in figure) of land area 108, D1 scope is 0.78-1.85 millimeter.
Fig. 5 is the A enlarged drawing (alternative plan) in Fig. 2.When upper package module 100 and lower encapsulating mould block 122 are connected, the first even surface 114 is also by the part contact substrate 104 of the first even surface 114.With the first even surface 114 in Fig. 5 for a scope at point of contact T3 and point of contact T4.When upper package module 100 and lower package module 122 (as shown in Figure 2) are connected, the pressure that upper package module 100 extends is excessive, and substrate surface 124 may be pressed into zigzag a little.When the first even surface 114 contact substrate surface 124 is by the 3rd even surface 132 instead of by an acute angle, substrate 104 can not be born a too large pressure and become further zigzag.In addition, fluid sealant packing space 120 (as shown in Figure 4), it is small that upper package module 100 extends the pressure produced, and this contributes to maintaining surface-treated layer complete on substrate 104 and metal structure.
When substrate 104 has once level and smooth appearance, it is corresponding with the 3rd even surface 132, and the pressure concentration phenomenon of the acute angle P1 of usual known technology Fig. 1 seldom can occur.
When the first long even surface 114 is level and smooth, the first even surface 114 is continuous and differentiable with the intersecting lens of a part.Such as, the first even surface 114 can become the part on the surface of a circle, and its range of curvature radius, from 0.1-2.0 millimeter, is preferably 0.6 millimeter.First even surface 114 can become the part of its main shaft scope from an ellipsoid of 0.1-1.17 millimeter, and cotta scope is from 0.1-1.0 millimeter.
Fig. 6 is the B enlarged drawing in Fig. 3.Fluid sealant 112 is arranged on the substrate 104 of semiconductor device, and the first even surface 114 is connected with fluid sealant 112, substrate surface 124 and fluid sealant side 116.Wherein second even surface 118 is corresponding to the first even surface 114 and for the scope between point of contact T2 and point of contact T6.
After fluid sealant 112 is formed, the side 116 of the outside of fluid sealant 112 is connected with a fluid sealant end face 140 of fluid sealant 112.Point of contact T2 between second even surface 118 and substrate surface 124 and the fluid sealant angle 142 that is interconnected between fluid sealant end face 140 and fluid sealant side 116 are separated by a preset distance D2, and wherein preset distance D2 is the same from 0.78-1.85 millimeter to preset distance D1 scope.
In addition, if the first even surface 114 is the parts on the surface of a circle, then second even surface 118 is corresponding round surfaces, if the first even surface 114 is parts of an ellipsoid, then second even surface 118 is also a corresponding ellipsoid.The size of second even surface 118 correspondingly corresponds to the first even surface 114.
The semiconductor package referred in an embodiment of the present invention can become ball array encapsulation (BGA) encapsulating structure, and it has some soldered balls (not illustrating) to be placed in the bottom surface 126 of the semiconductor device of Fig. 3.But, the above example is not limit for the present invention, is suitable for and manufactures any encapsulating structure.It refers to semiconductor package in embodiments of the present invention, is to be used in the above package module come forth in embodiment.
Semiconductor package, package module is used for identical shaping, and the package module come forth at the above in embodiment, many advantages will be verified proof.
The first, during encapsulation process, when land area contact and pressurization substrate, the tangent line substrate of the first even surface contact substrate or the contact of part first even surface land area, to reduce the pressure that substrate bears, makes surface-treated layer and metal structure remain complete.
The second, the tangent line of the level and smooth or part first even surface land area contact of the first even surface, it is the surface-treated layer of the softness being placed in substrate, make the surface-treated layer of on-chip softness will not by overvoltage, and then the surface-treated layer of softness will be peeled off not by stress injury.
Three, die cavity is by a part of first even surface contact land area, and it has a level and smooth appearance, is tangent line instead of an acute angle of part first even surface and land area.Thus, encapsulating mould has better heat conductivity during fluid sealant cooling curing process, and this contributes to ensureing and the life-saving encapsulating mould life-span.
Four, between the land area of package module and die cavity are interconnected, form re-entrant portion, this position does not leave too much pressure in manufacturing and encapsulation structure, thus better ensure that the quality of semiconductor package.
The present invention is simultaneously for example bright according to describing an embodiment, can illustrate that the present invention is not limited to there.Otherwise its purpose is that the present invention can cover different package modules and similar encapsulating structure, and the scope of appended claim should give to explain widely and comprise all package modules and similar encapsulating structure.
Claims (4)
1. the method by package module encapsulated semiconductor structure, with package module, chip (102) is encapsulated on substrate (104), form a complete semiconductor device, it is characterized in that: described package module comprises package module (100) and lower package module (122), package module has a land area (108), even surface and die cavity (110), even surface is a curved surface tangent with land area (108) and is placed in the opening part of die cavity (110), when package module is connected with the full substrate (104) carrying chip (102), land area (108) contacts and presses substrate (104), the wall end face (134) of described die cavity (110) inside is connected with wall side (136), the wall end face (134) of die cavity (110) inside is on substrate (104) opposite, the wall side (136) of die cavity (110) inside is connected with even surface, the wall end face (134) that die cavity (110) is inner and wall side (136) are interconnected to form an angle (138), even surface is connected with a point of contact (T1) with land area (108), and interconnective point of contact (T1) distance between 0.78-1.85 millimeter is separated, a kind of fluid sealant chip (102) is encapsulated on substrate (104) is filled in described die cavity (110).
2. according to the method for a kind of package module encapsulated semiconductor structure described in claim 1, it is characterized in that: described even surface adopts the first even surface (114) or adopts the combining structure of the first even surface (114), the second even surface (118) and the 3rd even surface (132) continuous transition.
3. according to the method for a kind of package module encapsulated semiconductor structure described in claim 2, it is characterized in that: when described first even surface (114) adopts circular surfaces a part of, second even surface (118) and the 3rd even surface (132) also adopt a part for circular surfaces, and the range of curvature radius of circular surfaces is from 0.1-2.0 millimeter.
4. according to the method for a kind of package module encapsulated semiconductor structure described in claim 2, it is characterized in that: when described first even surface (114) adopts oval surface a part of, second even surface (118) and the 3rd even surface (132) also adopt a part for oval surface, oval main shaft scope is from 0.1-1.17 millimeter, and cotta scope is from 0.1-1.0 millimeter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410780793.3A CN104465417A (en) | 2014-12-17 | 2014-12-17 | Method for encapsulating semiconductor structure through encapsulating module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410780793.3A CN104465417A (en) | 2014-12-17 | 2014-12-17 | Method for encapsulating semiconductor structure through encapsulating module |
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| Publication Number | Publication Date |
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| CN104465417A true CN104465417A (en) | 2015-03-25 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201410780793.3A Pending CN104465417A (en) | 2014-12-17 | 2014-12-17 | Method for encapsulating semiconductor structure through encapsulating module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111009481A (en) * | 2019-12-19 | 2020-04-14 | 西北电子装备技术研究所(中国电子科技集团公司第二研究所) | Chip substrate high-pressure flip-chip bonding flexible pressurization method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050186711A1 (en) * | 2004-02-20 | 2005-08-25 | Yee Richard M.L. | Mould for encapsulating a leadframe package and method of making the same |
| US20100044883A1 (en) * | 2005-07-27 | 2010-02-25 | Texas Instruments Incorporated | Plastic Semiconductor Package Having Improved Control of Dimensions |
| CN101859690A (en) * | 2009-04-10 | 2010-10-13 | 日月光半导体制造股份有限公司 | Packaging structure, sealing compound module and sealing compound mold for packaging same |
-
2014
- 2014-12-17 CN CN201410780793.3A patent/CN104465417A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050186711A1 (en) * | 2004-02-20 | 2005-08-25 | Yee Richard M.L. | Mould for encapsulating a leadframe package and method of making the same |
| US20100044883A1 (en) * | 2005-07-27 | 2010-02-25 | Texas Instruments Incorporated | Plastic Semiconductor Package Having Improved Control of Dimensions |
| CN101859690A (en) * | 2009-04-10 | 2010-10-13 | 日月光半导体制造股份有限公司 | Packaging structure, sealing compound module and sealing compound mold for packaging same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111009481A (en) * | 2019-12-19 | 2020-04-14 | 西北电子装备技术研究所(中国电子科技集团公司第二研究所) | Chip substrate high-pressure flip-chip bonding flexible pressurization method |
| CN111009481B (en) * | 2019-12-19 | 2023-04-18 | 西北电子装备技术研究所(中国电子科技集团公司第二研究所) | Chip substrate high-pressure flip-chip bonding flexible pressurization method |
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Application publication date: 20150325 |
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