CN204331828U - Hardware binarization image processing circuit structure and adopt the image processing module of this circuit structure - Google Patents
Hardware binarization image processing circuit structure and adopt the image processing module of this circuit structure Download PDFInfo
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- CN204331828U CN204331828U CN201520037140.6U CN201520037140U CN204331828U CN 204331828 U CN204331828 U CN 204331828U CN 201520037140 U CN201520037140 U CN 201520037140U CN 204331828 U CN204331828 U CN 204331828U
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Abstract
The utility model discloses a kind of hardware binarization image processing circuit structure and adopt the image processing module of this circuit structure; Belong to technical field of image processing; Its technical essential comprises threshold set circuit, signal shift circuit, clock division circuits and signal latch circuit; The signal input part of described threshold set circuit is connected with the signal output part of outside image acquisition circuit, and the signal output part of described threshold set circuit is connected with the signal input part of signal shift circuit; The signal output part of described clock division circuits allows to control pin with the clock signal input pin of signal shift circuit and the latch of signal latch circuit respectively and is connected; The utility model aims to provide a kind of easy to use, respond well hardware binarization image processing circuit structure and adopts the image processing module of this circuit structure; For image procossing.
Description
Technical field
The utility model relates to a kind of circuit structure and adopts the image processing module of this circuit structure, more particularly, particularly relates to a kind of hardware binarization image processing circuit structure and adopts the image processing module of this circuit structure.
Background technology
The binaryzation of image is the important step of computer vision field pattern-recognition, and the quality of binaryzation effect directly has influence on follow-up image recognition.Existing binary conversion treatment mode is mainly: one, gather original image signal and later stage software algorithm process, after gathering image, need the later stage to carry out software algorithm process, this processing mode Processing Algorithm is complicated, processing time is longer, higher to the requirement of processor.Two is the Edge check binaryzations adopting simulation camera, although directly can export binary image, easily occurs noise, and the difficulty of debugging pressure reduction is comparatively large, is not suitable for producing in enormous quantities, there will be unstable phenomenon simultaneously when gathering horizontal black line.
Utility model content
The purpose of this utility model is for above-mentioned the deficiencies in the prior art, provides a kind of easy to use, respond well hardware binarization image processing circuit structure and adopts the image processing module of this circuit structure.
The technical solution of the utility model is achieved in that a kind of hardware binarization image processing circuit structure, and this circuit structure mainly comprises threshold set circuit, signal shift circuit, clock division circuits and signal latch circuit; The signal input part of described threshold set circuit is connected with the signal output part of outside image acquisition circuit, and the signal output part of described threshold set circuit is connected with the signal input part of signal shift circuit; The signal output part of described clock division circuits allows to control pin with the clock signal input pin of signal shift circuit and the latch of signal latch circuit respectively and is connected.
In above-mentioned a kind of hardware binarization image processing circuit structure, described signal shift circuit is made up of at least one shift register, and described shift register is 74HC164 chip.
In above-mentioned a kind of hardware binarization image processing circuit structure, described clock division circuits is made up of at least one counting chip, and described counting chip is the two D flip-flop of 74LVC161 chip or 74LVC163 chip or 74LVC74.
In above-mentioned a kind of hardware binarization image processing circuit structure, described signal latch circuit is made up of at least one data storage circuitry, and described data storage circuitry is mainly SN74LVC573 chip.
In above-mentioned a kind of hardware binarization image processing circuit structure, described circuit structure also comprises buffer circuit.
Based on an image processing module for hardware binarization image processing circuit structure, comprise circuit board, be provided with camera image Acquisition Circuit on circuit boards, described camera image Acquisition Circuit is connected with camera, and described camera is arranged on circuit boards; The signal output part of described camera image Acquisition Circuit is connected with image processing circuit, and this image processing circuit mainly comprises threshold set circuit, signal shift circuit, clock division circuits and signal latch circuit; The signal input part of described threshold set circuit is connected with the signal output part of outside image acquisition circuit, and the signal output part of described threshold set circuit is connected with the signal input part of signal shift circuit; The signal output part of described clock division circuits allows to control pin with the clock signal input pin of signal shift circuit and the latch of signal latch circuit respectively and is connected; Described signal latch circuit is connected with output unit, and output unit is connected with external unit.
In the above-mentioned image processing module based on hardware binarization image processing circuit structure, described output unit is arranged needle interface by the soft arranging wire interface arranged on circuit boards and straight cutting and is formed; Soft arranging wire interface is connected with signal latch circuit respectively with straight cutting row needle interface.
In the above-mentioned image processing module based on hardware binarization image processing circuit structure, described camera image Acquisition Circuit forms primarily of sensitive chip, the filtering circuit be connected with sensitive chip respectively, reset circuit, crystal oscillating circuit, protection circuit.
The above-mentioned image processing module based on hardware binarization image processing circuit structure, is characterized in that, described signal shift circuit is made up of at least one shift register, and described shift register is 74HC164 chip; Described clock division circuits is made up of at least one counting chip, and described counting chip is the two D flip-flop of 74LVC161 chip or 74LVC163 chip or 74LVC74; Described signal latch circuit is made up of at least one data storage circuitry, and described data storage circuitry is mainly SN74LVC573 chip; Described circuit structure also comprises buffer circuit.
The utility model utilizes the characteristic that camera carries, combining image camera image Acquisition Circuit and image processing circuit after adopting said structure, directly omits software Processing Algorithm process, exports ideal binary image from hardware.Hardware directly exports binary image, eliminates the image processing process in later stage, reduces the performance requirement of processor, saves the performance history of image algorithm design.Due to the characteristic utilizing camera itself to carry, there is dynamic gain control function, thus the image noise exported is few, threshold value setting is simple, can easily produce in enormous quantities, there will not be the wild effect of horizontal black line, and easily can obtain satisfied binary image effect in the occasion that aberration is larger.
Accompanying drawing explanation
Below in conjunction with the embodiment in accompanying drawing, the utility model is described in further detail, but do not form any restriction of the present utility model.
Fig. 1 is electrical block diagram of the present utility model;
Fig. 2 is structural representation of the present utility model;
Fig. 3 is the structural representation after Fig. 2 removes camera;
Fig. 4 is the backsight structural representation of Fig. 2.
In figure: threshold set circuit 1, signal shift circuit 2, clock division circuits 3, signal latch circuit 4, buffer circuit 5, circuit board 6, camera image Acquisition Circuit 7, sensitive chip 7a, filtering circuit 7b, reset circuit 7c, crystal oscillating circuit 7d, protection circuit 7e, camera 8, output unit 9, soft arranging wire interface 9a, straight cutting row needle interface 9b.
Embodiment
Consult shown in Fig. 1 to Fig. 4, a kind of hardware binarization image processing circuit structure of the present utility model, this circuit structure mainly comprises threshold set circuit 1, signal shift circuit 2, clock division circuits 3 and signal latch circuit 4.In the present embodiment, threshold set circuit 1 is that the highest 2 bit data of the data output of external image Acquisition Circuit set threshold value by NAND gate circuit, and preferably, the chip that NAND gate circuit adopts is SN74LVC1G00; Certainly, also other figure place of the optional delivery outlet that fetches data, sets threshold value by digital comparator; Or directly choose most significant digit data to be connected with the signal input part of signal shift circuit 2, as long as meet the requirement of threshold value setting.Described signal shift circuit 2 is made up of at least one shift register, and preferably, described shift register is 74HC164 chip, and two-value signal seals in and goes out by signal shift circuit 2, so that processor more easily gathers.In the present embodiment, signal shift circuit 2 is only provided with a shift register, is applicable to 4 and exports or 8 outputs; Certainly, export or the output of more seniority to be applicable to 16, then 1 an or more shift register on needing to connect on the basis of a shift register.Described clock division circuits 3 is made up of at least one counting chip, and preferably, described counting chip is the two D flip-flop of 74LVC161 chip or 74LVC163 chip or 74LVC74.In the present embodiment, clock division circuits 3 is only provided with a counting chip, is applicable to 4 and exports or 8 outputs; Certainly, export or the output of more seniority to be applicable to 16, then 1 an or more counting chip on needing to connect on the basis of a counting chip.Described signal latch circuit 4 is made up of at least one data storage circuitry, and preferably, described data storage circuitry is mainly SN74LVC573 chip, signal shift circuit 2 is outputed signal more stable.In the present embodiment, signal latch circuit 4 is only provided with a data storage circuitry, is applicable to 4 and exports or 8 outputs; Certainly, export or the output of more seniority to be applicable to 16, then 1 an or more data storage circuitry on needing to connect on the basis of a data storage circuitry.In the present embodiment, signal shift circuit 2 and signal latch circuit 4 are the displacement, the latch that adopt different chip difference settling signals, and certainly, what band also can be used to latch seals in and go out chip, as 74 serial 595 chips.The signal input part of described threshold set circuit 1 is connected with the signal output part of outside image acquisition circuit, and the signal output part of described threshold set circuit 1 is connected with the signal input part of signal shift circuit 2.The signal output part of described clock division circuits 3 allows to control pin with the clock signal input pin of signal shift circuit 2 and the latch of signal latch circuit 4 respectively and is connected.Clock division circuits 3 is signal shift circuit 2, the processor of signal latch circuit 4 and outside provides different clock signals, and in the present embodiment, clock division circuits 3 provides two divided-frequency signal, for giving the collection of shift circuit dot interlace for signal shift circuit 2; Clock division circuits 3 provides 16 frequency division single pulse signals for signal latch circuit 4, for providing latch pulse to latch cicuit, stablizing and exporting data; The processor that clock division circuits 3 is outside provides 16 fractional frequency signals, provides a Dot Clock to ppu collection signal by external interface.Meanwhile, in order to this image processing circuit structure has more stability, described circuit structure also comprises buffer circuit 5, preferably, adopts the buffer circuit 5 of first in first out, can adopt AL422B chip.
A kind of image processing module based on hardware binarization image processing circuit structure; comprise circuit board 6; circuit board 6 is provided with camera image Acquisition Circuit 7, and described camera image Acquisition Circuit 7 forms primarily of sensitive chip 7a, the filtering circuit 7b be connected with sensitive chip 7a respectively, reset circuit 7c, crystal oscillating circuit 7d, protection circuit 7e.In the present embodiment, the chip that sensitive chip 7a adopts is OV7725, certainly, also can use the sensitive chip 7a that other band contrast is focused, as OV7670, OV7620 etc.; Filtering circuit 7b is made up of resistance and some electric capacity, for filtering, isolation interference; Reset circuit 7c is made up of resistance and electric capacity, plays reset role during for powering on; Crystal oscillating circuit 7d is made up of, for providing clock source to Acquisition Circuit the active crystal oscillator of 12M; Protection circuit 7e is made up of two resistance, prevents electric current excessive and burns out camera; Also be provided with pull-up resistor at power input, when guaranteeing that bus is unsettled, signal keeps high level.Pull-up resistor can be located in camera image Acquisition Circuit 7, also can be located in external circuit.Described camera image Acquisition Circuit 7 is connected with camera 8, and described camera 8 is arranged on circuit board 6, and circuit board 6 is provided with lens mount, facilitates the installation of camera 8; Utilize the contrast adjustment function that camera 8 carries, gain control capability, configuration contrast register can obtain comparatively close to the gray level image of binaryzation effect; The signal output part of described camera image Acquisition Circuit 7 is connected with image processing circuit, and this image processing circuit mainly comprises threshold set circuit 1, signal shift circuit 2, clock division circuits 3 and signal latch circuit 4.Described signal shift circuit 2 is made up of at least one shift register, and described shift register is 74HC164 chip; Described clock division circuits 3 is made up of at least one counting chip, and described counting chip is the two D flip-flop of 74LVC161 chip or 74LVC163 chip or 74LVC74; Described signal latch circuit 4 is made up of at least one data storage circuitry, and described data storage circuitry is mainly SN74LVC573 chip; Described circuit structure also comprises buffer circuit 5.The signal input part of described threshold set circuit 1 is connected with the signal output part of outside image acquisition circuit, and the signal output part of described threshold set circuit 1 is connected with the signal input part of signal shift circuit 2; The signal output part of described clock division circuits 3 allows to control pin with the clock signal input pin of signal shift circuit 2 and the latch of signal latch circuit 4 respectively and is connected; Described signal latch circuit 4 is connected with output unit 9, and in the present embodiment, described output unit 9 is arranged needle interface 9b by the soft arranging wire interface 9a be arranged on circuit board 6 and straight cutting and formed; Soft arranging wire interface 9a is connected with signal latch circuit 4 respectively with straight cutting row needle interface 9b.Output unit 9 is connected with external unit, from external unit, output unit 9 is carried out to the read work of signal.
During use, crystal oscillating circuit 7d works as sensitive chip 7a provides crystal oscillation signal, sensitive chip 7a provides clock signal by output pin to clock division circuits 3, and clock division circuits 3 is respectively signal shift circuit 2, signal latch circuit 4 and ppu and provides fractional frequency signal; By camera 8, image is gathered, utilize the contrast adjustment function that camera 8 carries, obtain comparatively close to the gray level image of binaryzation effect, greyscale image data is sent in camera image Acquisition Circuit 7; Then, image is gathered by sensitive chip 7a, after having gathered image, signal is input in threshold set circuit 1 from the signal output port sensitive chip 7a, logical circuit is utilized to set threshold value, export the binaryzation pixel of 1 to signal shift circuit 2, the signal sealed in carries out and goes out by signal shift circuit 2, then by signal latch circuit 4 make signal shift circuit 2 and go out data and export more stable.Utilize logical circuit to be shifted to signal, latch process, make the image of output more easily by the stable collection of processor.
Above illustrated embodiment is better embodiment of the present utility model, only be used for conveniently the utility model being described, not any pro forma restriction is done to the utility model, have in any art and usually know the knowledgeable, if do not depart from the utility model carry in the scope of technical characteristic, utilize the utility model disclose the Equivalent embodiments changing or modify in the done local of technology contents, and do not depart from technical characteristic content of the present utility model, all still belong in the scope of the utility model technical characteristic.
Claims (9)
1. a hardware binarization image processing circuit structure, it is characterized in that, this circuit structure mainly comprises threshold set circuit (1), signal shift circuit (2), clock division circuits (3) and signal latch circuit (4); The signal input part of described threshold set circuit (1) is connected with the signal output part of outside image acquisition circuit, and the signal output part of described threshold set circuit (1) is connected with the signal input part of signal shift circuit (2); The signal output part of described clock division circuits (3) allows to control pin with the clock signal input pin of signal shift circuit (2) and the latch of signal latch circuit (4) respectively and is connected.
2. a kind of hardware binarization image processing circuit structure according to claim 1, is characterized in that, described signal shift circuit (2) is made up of at least one shift register, and described shift register is 74HC164 chip.
3. a kind of hardware binarization image processing circuit structure according to claim 1, it is characterized in that, described clock division circuits (3) is made up of at least one counting chip, and described counting chip is the two D flip-flop of 74LVC161 chip or 74LVC163 chip or 74LVC74.
4. a kind of hardware binarization image processing circuit structure according to claim 1, it is characterized in that, described signal latch circuit (4) is made up of at least one data storage circuitry, and described data storage circuitry is mainly SN74LVC573 chip.
5. a kind of hardware binarization image processing circuit structure according to claim 1, it is characterized in that, described circuit structure also comprises buffer circuit (5).
6. the image processing module based on hardware binarization image processing circuit structure, comprise circuit board (6), it is characterized in that, circuit board (6) is provided with camera image Acquisition Circuit (7), described camera image Acquisition Circuit (7) is connected with camera (8), and described camera (8) is arranged on circuit board (6); The signal output part of described camera image Acquisition Circuit (7) is connected with image processing circuit, and this image processing circuit mainly comprises threshold set circuit (1), signal shift circuit (2), clock division circuits (3) and signal latch circuit (4); The signal input part of described threshold set circuit (1) is connected with the signal output part of outside image acquisition circuit, and the signal output part of described threshold set circuit (1) is connected with the signal input part of signal shift circuit (2); The signal output part of described clock division circuits (3) allows to control pin with the clock signal input pin of signal shift circuit (2) and the latch of signal latch circuit (4) respectively and is connected; Described signal latch circuit (4) is connected with output unit (9), and output unit (9) is connected with external unit.
7. the image processing module based on hardware binarization image processing circuit structure according to claim 6, it is characterized in that, described output unit (9) is arranged needle interface (9b) by the soft arranging wire interface (9a) be arranged on circuit board (6) and straight cutting and is formed; Soft arranging wire interface (9a) is connected with signal latch circuit (4) respectively with straight cutting row's needle interface (9b).
8. the image processing module based on hardware binarization image processing circuit structure according to claim 6; it is characterized in that, described camera image Acquisition Circuit (7) forms primarily of sensitive chip (7a), the filtering circuit (7b) be connected with sensitive chip (7a) respectively, reset circuit (7c), crystal oscillating circuit (7d), protection circuit (7e).
9. the image processing module based on hardware binarization image processing circuit structure according to claim 6, is characterized in that, described signal shift circuit (2) is made up of at least one shift register, and described shift register is 74HC164 chip; Described clock division circuits (3) is made up of at least one counting chip, and described counting chip is the two D flip-flop of 74LVC161 chip or 74LVC163 chip or 74LVC74; Described signal latch circuit (4) is made up of at least one data storage circuitry, and described data storage circuitry is mainly SN74LVC573 chip; Described circuit structure also comprises buffer circuit (5).
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| CN201520037140.6U CN204331828U (en) | 2015-01-19 | 2015-01-19 | Hardware binarization image processing circuit structure and adopt the image processing module of this circuit structure |
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| CN201520037140.6U CN204331828U (en) | 2015-01-19 | 2015-01-19 | Hardware binarization image processing circuit structure and adopt the image processing module of this circuit structure |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108805846A (en) * | 2017-05-03 | 2018-11-13 | 深圳市傲睿智存科技有限公司 | The method and its system of binary Images Processing optimization |
| CN111464750A (en) * | 2020-05-14 | 2020-07-28 | 中央民族大学 | Image processing device and intelligent vehicle |
| US11157769B2 (en) * | 2018-09-25 | 2021-10-26 | Realtek Semiconductor Corp. | Image processing circuit and associated image processing method |
-
2015
- 2015-01-19 CN CN201520037140.6U patent/CN204331828U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108805846A (en) * | 2017-05-03 | 2018-11-13 | 深圳市傲睿智存科技有限公司 | The method and its system of binary Images Processing optimization |
| US11157769B2 (en) * | 2018-09-25 | 2021-10-26 | Realtek Semiconductor Corp. | Image processing circuit and associated image processing method |
| CN111464750A (en) * | 2020-05-14 | 2020-07-28 | 中央民族大学 | Image processing device and intelligent vehicle |
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Granted publication date: 20150513 Termination date: 20210119 |