CN212163819U

CN212163819U - PCB wiring structure for improving signal quality of multi-particle DDR system

Info

Publication number: CN212163819U
Application number: CN202020929857.2U
Authority: CN
Inventors: 黄刚; 吴均
Original assignee: Edadoc Co ltd
Current assignee: Edadoc Co ltd
Priority date: 2020-05-28
Filing date: 2020-05-28
Publication date: 2020-12-15
Anticipated expiration: 2030-05-28

Abstract

The utility model discloses an improve PCB of many granule DDR system signal quality and walk line structure, including the PCB board, be provided with main chip and a plurality of DDR granule on the PCB board, a plurality of DDR granule pass through the signal and walk the line series connection on main chip, be provided with continuous first line and the second of walking between the DDR granule of main chip and first being connected and walk the line, the first other end of walking the line is connected with main chip, the second walks the other end of line and is connected with first DDR granule, the first impedance of walking the line is greater than the signal and walks the impedance of line, the second is walked the impedance of line and is less than the signal and walks the impedance of line. The utility model discloses a walk the line to signal between the DDR granule that main chip and first connection and carry out the combination back that specific length walked line impedance change, slowed down the main chip and forced drive and risen the edge to reach the mesh of optimizing DDR system signal quality.

Description

PCB wiring structure for improving signal quality of multi-particle DDR system

Technical Field

The utility model relates to a circuit board field, specific theory relates to an improve PCB of many granule DDR system signal quality and walk line structure.

Background

A Printed Circuit Board (PCB) is also called a PCB, which is an important component of physical support and signal transmission of electronic products. In the field of PCB design, DDR (Double Data Rate SDRAM) design occupies the vast majority. The DDR memory is widely applied at present, in order to expand the capacity, the number of DDR particles carried by a DDR system is increased at present, so that the one-to-many signal topology becomes more and more difficult to design, especially when the driving capability of a chip cannot be adjusted too much, a stronger drive often causes reflection of the signal quality of the DDR system to increase, especially a first DDR particle closest to a main chip often causes a larger reflection of a signal due to back-and-forth reflection of a signal of a following DDR particle, so that the signal quality of the DDR memory is seriously affected, and meanwhile, the signal quality of the DDR memory is often the worst.

The above disadvantages need to be improved.

Disclosure of Invention

In order to overcome the not enough of current technique, the utility model provides an improve PCB of many granule DDR system signal quality and walk line structure.

The utility model discloses technical scheme as follows:

a PCB wiring structure for improving signal quality of a multi-particle DDR system comprises a PCB, wherein a main chip and a plurality of DDR particles are arranged on the PCB, and the DDR particles are connected in series on the main chip through signal wiring.

According to the above scheme the utility model discloses, its characterized in that, first walk the line with the second is walked the length of line and is equal.

Further, the lengths of the first wire and the second wire are both proportional to the signal rate of the DDR particles.

Further, a proportional relationship between the lengths of the first trace and the second trace and the signal rate of the DDR particle is as follows: 1mil =10 Mbps.

According to above-mentioned scheme the utility model discloses, the first impedance of walking the line does 1.1 times ~ 1.3 times of the impedance of the line is walked to the signal, the second is walked the impedance of line and is done 0.7 times ~ 0.9 times of the impedance of the line is walked to the signal.

Further, the impedance of the first wire is 1.2 times that of the signal wire, and the impedance of the second wire is 0.8 times that of the signal wire.

Further, the impedance of the first wire is 1.3 times that of the signal wire, and the impedance of the second wire is 0.7 times that of the signal wire.

Further, the impedance of the first wire is 1.1 times that of the signal wire, and the impedance of the second wire is 0.9 times that of the signal wire.

According to the above scheme the utility model discloses, the beneficial effects of the utility model reside in that:

the utility model slows down the strong driving rising edge of the main chip after the signal routing between the main chip and the first connected DDR particles is combined with the routing impedance change with a specific length, thereby achieving the purpose of optimizing the signal quality of the DDR system; the utility model discloses a simple mode removes the influence that improves main chip strong drive's rising edge and bring, and processing is simple convenient, and is with low costs, can promote on a large scale.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of the present invention;

FIG. 2 is a schematic diagram of a prior art structure;

fig. 3 is a comparison graph of the rising edge of the output signal of the first DDR particle in the conventional PCB trace structure shown in fig. 2 according to the present invention;

in the figures, the reference numerals are as follows:

1. a main chip; 2. DDR particles; 3. signal routing; 4. a first wire; 5. and a second trace.

Detailed Description

In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention more clearly understood, the following description is given in conjunction with the accompanying drawings and embodiments to illustrate the present invention in further detail.

As shown in fig. 1, a PCB routing structure for improving signal quality of a multi-particle DDR system includes a PCB (not shown, the same below), a main chip 1 and a plurality of DDR particles 2 are disposed on the PCB, the plurality of DDR particles 2 are connected in series on the main chip 1 through signal routing 3, a first routing 4 and a second routing 5 connected to each other are disposed between the main chip 1 and the first DDR particle 2, the other end of the first routing 4 is connected to the main chip 1, the other end of the second routing 5 is connected to the first DDR particle 2, impedance of the first routing 4 is 1.1-1.3 times impedance of the signal routing 3, impedance of the second routing 5 is 0.7-0.9 times impedance of the signal routing 3, and lengths of the first routing 4 and the second routing 5 are equal. The utility model discloses a change the signal between DDR granule 2 that main chip 1 and first are connected and walk the impedance of line 3, slowed down the ascending edge of main chip 1 strong drive to reach the purpose of optimizing DDR system signal quality.

In this embodiment, the lengths of the first trace 4 and the second trace 5 are both proportional to the signal rate of the DDR particle 2, i.e. the faster the signal rate of the DDR particle 2 is, the longer the length of the first trace 4 and the second trace 5 are designed to be. Preferably, the proportional relationship between the lengths of the first trace 4 and the second trace 5 and the signal rate of the DDR particle 2 is as follows: 1mil =10 Mbps. By setting the lengths of the first wire 4 and the second wire 5 according to the above proportional relationship, the signal quality of the DDR system can be improved to the best.

In this embodiment, the impedance of the first trace 4 is 1.2 times that of the signal trace 3, and the impedance of the second trace 5 is 0.8 times that of the signal trace 3. The impedance of the first wire 4 and the second wire 5 is set to make the signal quality of the DDR system better.

In another embodiment, the impedance of the first trace 4 is 1.3 times the impedance of the signal trace 3, and the impedance of the second trace 5 is 0.7 times the impedance of the signal trace 3. The impedance of the first wire 4 and the second wire 5 is set to make the signal quality of the DDR system better.

In another embodiment, the impedance of the first trace 4 is 1.1 times the impedance of the signal trace 3, and the impedance of the second trace 5 is 0.9 times the impedance of the signal trace 3. The impedance of the first wire 4 and the second wire 5 is set to make the signal quality of the DDR system better.

In the specific PCB design, the impedance of the first wire 4 and the second wire 5 between the main chip 1 and the first connected DDR particle 2 reaches 1.2 times and 0.8 times of the original impedance only by changing the wire width, and then the length is adjusted according to the signal rate of the DDR particle 2.

As shown in fig. 2, in the conventional PCB routing structure of the multi-particle DDR system, a plurality of DDR particles 2 are simply connected in series on a main chip 1, and the DDR particle 2 closest to the main chip 1 (i.e. the first DDR particle 2 connected to the main chip 1) is usually reflected back and forth by a signal of the following DDR particle 2, so that the signal is reflected more greatly, and the signal quality is seriously affected. The source of signal reflection is caused by the fact that the main chip 1 is driven too strongly, which shows that the rising edge of the output signal is too steep, and has many high-frequency components, and the high-frequency components are more sensitive to reflection of a multi-load structure, so that fluctuation of a DDR particle signal is caused, and the signal quality of a DDR system is deteriorated.

Fig. 3 is a line structure is walked to the PCB of current many granules DDR system and the utility model discloses a PCB walks the rising edge contrast picture of worst first DDR granule output signal among the line structure. Can see from the figure, walk the line structure for the PCB of current many granules DDR system, the utility model discloses a walk the line 3 to the signal between the DDR granule 2 that main chip 1 and first connection and carry out the combination back that specific length walked the line impedance change, be equivalent to for main chip 1 driven rising edge to make an adjustment, the high impedance brings the perception, the low impedance brings the compatibility, and this just can effectively slow down main chip 1 driven rising edge. Therefore, adopt the utility model discloses DDR system signal quality can obviously be improved to the PCB of this kind of mode and walks the line structure.

It will be understood that modifications and variations can be effected by a person skilled in the art in light of the above teachings, and all such modifications and variations are intended to be included within the scope of the appended claims.

The above exemplary description of the present invention is made in conjunction with the accompanying drawings, and it is obvious that the present invention is not limited by the above manner, and various improvements made by the method concept and technical solution of the present invention or by directly applying the concept and technical solution of the present invention to other occasions without improvement are all within the protection scope of the present invention.

Claims

1. A PCB wiring structure for improving signal quality of a multi-particle DDR system comprises a PCB, wherein a main chip and a plurality of DDR particles are arranged on the PCB, and the DDR particles are connected in series on the main chip through signal wiring.

2. The PCB trace structure for improving signal quality of a multi-granular DDR system of claim 1, wherein the first trace and the second trace are equal in length.

3. The PCB trace structure for improving signal quality of a multi-particle DDR system of claim 2, wherein the lengths of the first trace and the second trace are both proportional to the signal rate of the DDR particle.

4. The PCB trace structure for improving signal quality of a multi-granular DDR system of claim 3, wherein a proportional relationship between the length of the first trace and the second trace and the signal rate of the DDR granule is as follows: 1mil =10 Mbps.

5. The PCB trace structure for improving signal quality of a multi-particle DDR system of claim 1, wherein the impedance of the first trace is 1.1 to 1.3 times the impedance of the signal trace, and the impedance of the second trace is 0.7 to 0.9 times the impedance of the signal trace.

6. The PCB trace structure for improving signal quality of a multi-particle DDR system of claim 5, wherein the impedance of the first trace is 1.2 times the impedance of the signal trace, and the impedance of the second trace is 0.8 times the impedance of the signal trace.

7. The PCB trace structure for improving signal quality of a multi-particle DDR system of claim 5, wherein the impedance of the first trace is 1.3 times the impedance of the signal trace, and the impedance of the second trace is 0.7 times the impedance of the signal trace.

8. The PCB trace structure for improving signal quality of a multi-particle DDR system of claim 5, wherein the impedance of the first trace is 1.1 times the impedance of the signal trace, and the impedance of the second trace is 0.9 times the impedance of the signal trace.