CN204202643U - A kind of multichannel undesired signal Acquisition Circuit - Google Patents
A kind of multichannel undesired signal Acquisition Circuit Download PDFInfo
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- CN204202643U CN204202643U CN201420723525.3U CN201420723525U CN204202643U CN 204202643 U CN204202643 U CN 204202643U CN 201420723525 U CN201420723525 U CN 201420723525U CN 204202643 U CN204202643 U CN 204202643U
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- multichannel
- undesired signal
- acquisition circuit
- collector
- signal acquisition
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Abstract
The utility model discloses a kind of multichannel undesired signal Acquisition Circuit, it comprises multi-channel A/D collector, fpga chip, dsp processor, ethernet PHY chip, timer manager and crystal oscillator, described multi-channel A/D collector receives the undesired signal from outside, the output of AD collector is connected with fpga chip, fpga chip is connected with external bus by GTX interface, and fpga chip is also connected with dsp processor by DSP data bus; Described timer manager one road input end receives the reference signal from crystal oscillator, and the output terminal of timer manager is connected with multi-channel A/D collector, timer manager to multi-channel A/D collector each road PCB track lengths isometric.The utility model provides a kind of clock source of homology homophase that adopts as undesired signal Acquisition Circuit sampling clock, easy to use, the much higher passage of accuracy.
Description
Technical field
The utility model relates to a kind of signal acquisition circuit, particularly relates to a kind of multichannel undesired signal Acquisition Circuit.
Background technology
Data acquisition system (DAS) is the bridge that computer intelligence instrument and extraneous physical world contact, and is the important channel of obtaining information.Data acquisition technology mainly refers to the ultra-weak electronic signal exported from sensor, through signal condition, analog to digital conversion to the technology storing, record involved by this process.Along with the develop rapidly of computing machine and infotech, Signal transmissions occupies more and more consequence in production and the life of people, but has a factor affecting laser propagation effect in the transmitting procedure of signal, and that is exactly undesired signal.Therefore, Acquire and process carries out to undesired signal just extremely important.
And multichannel collecting is applied widely in data Collection & Processing System, hyperchannel most importantly will accomplish synchronous acquisition exactly in collection, Complete Synchronization is optimal, but Complete Synchronization is all in theory, can not accomplish in actual acquisition process.So the lock in time how reducing multichannel collecting is just very important, this is also that a difficult point facing of present multichannel collecting technology is with not enough.
Utility model content
The utility model object is to overcome the deficiencies in the prior art, provides a kind of clock source of homology homophase that adopts as undesired signal Acquisition Circuit sampling clock, easy to use, the much higher passage of accuracy.
The technical solution of the utility model is achieved in that a kind of multichannel undesired signal Acquisition Circuit, it comprises multi-channel A/D collector, fpga chip, dsp processor, ethernet PHY chip, timer manager and crystal oscillator, described multi-channel A/D collector receives the undesired signal from outside, the output of AD collector is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is also connected with dsp processor by DSP data bus, dsp processor one end is connected with the pci interface preset, the other end is connected with gigabit Ethernet by ethernet PHY chip, described timer manager one road input end receives the reference signal from crystal oscillator, and the output terminal of timer manager is connected with multi-channel A/D collector, timer manager to multi-channel A/D collector each road PCB track lengths isometric.
The multichannel undesired signal Acquisition Circuit of described one, also comprise a Low Voltage Differential Signal LVDS circuit, the input end of LVDS circuit is connected with external signal, and the output terminal of LVDS circuit is connected with fpga chip.
Another road input end of described timer manager receives the control from external trigger source.
Described fpga chip also comprises the interface of a synchronously triggering and pulse per second (PPS) input.
Described multi-channel A/D collector way is 8 tunnels.
The multichannel undesired signal Acquisition Circuit of described one also comprises a DDR2, and described DDR2 is connected with fpga chip.
The multichannel undesired signal Acquisition Circuit of described one also comprises a FLASH, and described FLASH is connected with dsp processor.
The multichannel undesired signal Acquisition Circuit of described one also comprises a CAN interface.
The multichannel undesired signal Acquisition Circuit of described one, also comprises a PCIe interface.
Described fpga chip receives the signal from outside by PPS.
Actual gain effect of the present utility model is: the sampling clock of hyperchannel AD comes all from same clock source, and ensure that the same frequency homology of sampling clock, clock source can use outer confession or local clock as sampling clock; Clock signal is strictly isometric to the PCB track lengths of each AD device, ensure that the strict homophase of sampling clock; Adopt same external trigger source to start the trigger pip of sampling as signal, ensure that the synchronism of data acquisition; Synchronized sampling clock and synchronous triggering signal have also given fpga chip, and fpga chip is to the synchronous reception of multi-channel A/D image data; <0.1ns lock in time of multi-channel sampling, this time can be made can to think system inherent error through these guarantees, can by after system electrification, adopting software to carry out calibration must in correction, makes to gather to have very high accuracy.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present utility model.
Embodiment
The technical solution of the utility model is further described below in conjunction with accompanying drawing, as shown in Figure 1: a kind of multichannel undesired signal Acquisition Circuit, it comprises multi-channel A/D collector, fpga chip, dsp processor, ethernet PHY chip, timer manager and crystal oscillator, described multi-channel A/D collector receives the undesired signal from outside, the output of AD collector is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is also connected with dsp processor by DSP data bus, dsp processor one end is connected with the pci interface preset, the other end is connected with gigabit Ethernet by ethernet PHY chip, described timer manager one road input end receives the reference signal from crystal oscillator, and the output terminal of timer manager is connected with multi-channel A/D collector, timer manager to multi-channel A/D collector each road PCB track lengths isometric.
The multichannel undesired signal Acquisition Circuit of described one, also comprise a Low Voltage Differential Signal LVDS circuit, the input end of LVDS circuit is connected with external signal, and the output terminal of LVDS circuit is connected with fpga chip.
Another road input end of described timer manager receives the control from external trigger source.
Described fpga chip also comprises the interface of a synchronously triggering and pulse per second (PPS) input.
Described multi-channel A/D collector way is 8 tunnels.
The multichannel undesired signal Acquisition Circuit of described one also comprises a DDR2, and described DDR2 is connected with fpga chip.
The multichannel undesired signal Acquisition Circuit of described one also comprises a FLASH, and described FLASH is connected with dsp processor.
The multichannel undesired signal Acquisition Circuit of described one also comprises a CAN interface.
The multichannel undesired signal Acquisition Circuit of described one, also comprises a PCIe interface.
Described fpga chip receives the signal from outside by PPS.
AD collector 8 tunnel of the present utility model simulating signal synchronized sampling, in acquisition module, the sampling clock of hyperchannel AD comes all from the synchronized sampling clock in same clock source, ensure that the same frequency homology of sampling clock, clock signal is strictly isometric to the PCB track lengths of each AD device, ensure that the strict homophase of sampling clock, adopt same external trigger source to start the trigger pip of sampling as signal, ensure that the synchronism of data acquisition.
Described synchronized sampling clock and synchronous triggering signal have also given fpga chip, ensure that fpga chip work also has identical clock reference, utilize synchronous trigger input signal in fpga chip, realize the synchronous reception to multi-channel A/D image data.
Can ensure <0.1ns lock in time of multi-channel sampling through above synchronous clock and synchronous triggering signal, this time can think system inherent error, can by after system electrification, and adopting software to carry out calibration must in correction.
Technical indicator of the present utility model:
The LVDS difference of data output interface: DDR;
Rf input port: SMA connector;
Sampling rate: 250MHz;
A/D bit wide: 16bit;
Clock Tree: internal clocking or external clock;
Full scale inputs: 2.0VPP or 2.5VPP difference;
ENOB：10bits～11bits (fs=250Msps,fin=170MHz)；
Analog input bandwidth: 900MHz;
Typical case's power consumption: single channel 820mW;
Radiating mode: conduction cooling/air-cooled;
Working temperature :-40 DEG C ~+70 DEG C.
Claims (9)
1. a multichannel undesired signal Acquisition Circuit, it is characterized in that: it comprises multi-channel A/D collector, fpga chip, dsp processor, ethernet PHY chip, timer manager and crystal oscillator, described multi-channel A/D collector receives the undesired signal from outside, the output of AD collector is connected with fpga chip, fpga chip is connected with external bus by GTX interface, fpga chip is also connected with dsp processor by DSP data bus, dsp processor one end is connected with the pci interface preset, and the other end is connected with gigabit Ethernet by ethernet PHY chip; One road input end of described timer manager receives the reference signal from crystal oscillator, and the output terminal of timer manager is connected with multi-channel A/D collector, timer manager to multi-channel A/D collector each road PCB track lengths isometric.
2. the multichannel undesired signal Acquisition Circuit of one according to claim 1, is characterized in that: it also comprises a Low Voltage Differential Signal LVDS circuit, and the input end of LVDS circuit is connected with external signal, and the output terminal of LVDS circuit is connected with fpga chip.
3. the multichannel undesired signal Acquisition Circuit of one according to claim 1, is characterized in that: another road input end of described timer manager receives the control from external trigger source.
4. the multichannel undesired signal Acquisition Circuit of one according to claim 1, is characterized in that: described fpga chip also comprises the interface of a synchronously triggering and pulse per second (PPS) input.
5. the multichannel undesired signal Acquisition Circuit of one according to claim 1, is characterized in that: described multi-channel A/D collector way is 8 tunnels.
6. the multichannel undesired signal Acquisition Circuit of one according to claim 1, is characterized in that: it also comprises a DDR2, and described DDR2 is connected with fpga chip.
7. the multichannel undesired signal Acquisition Circuit of one according to claim 1, is characterized in that: it also comprises a FLASH, and described FLASH is connected with dsp processor.
8. the multichannel undesired signal Acquisition Circuit of one according to claim 1, is characterized in that: it also comprises a CAN interface.
9. the multichannel undesired signal Acquisition Circuit of one according to claim 1, is characterized in that: it also comprises a PCIe interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420723525.3U CN204202643U (en) | 2014-11-27 | 2014-11-27 | A kind of multichannel undesired signal Acquisition Circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420723525.3U CN204202643U (en) | 2014-11-27 | 2014-11-27 | A kind of multichannel undesired signal Acquisition Circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204202643U true CN204202643U (en) | 2015-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420723525.3U Expired - Fee Related CN204202643U (en) | 2014-11-27 | 2014-11-27 | A kind of multichannel undesired signal Acquisition Circuit |
Country Status (1)
| Country | Link |
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| CN (1) | CN204202643U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107153372A (en) * | 2017-04-05 | 2017-09-12 | 中北大学 | A kind of miniature data collecting system of the expansible stack of passage |
-
2014
- 2014-11-27 CN CN201420723525.3U patent/CN204202643U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107153372A (en) * | 2017-04-05 | 2017-09-12 | 中北大学 | A kind of miniature data collecting system of the expansible stack of passage |
| CN107153372B (en) * | 2017-04-05 | 2018-07-31 | 中北大学 | A kind of miniature data collecting system of the stack that channel is expansible |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150311 Termination date: 20151127 |