CN204257636U - A kind of internal memory - Google Patents

A kind of internal memory Download PDF

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Publication number
CN204257636U
CN204257636U CN201420823427.7U CN201420823427U CN204257636U CN 204257636 U CN204257636 U CN 204257636U CN 201420823427 U CN201420823427 U CN 201420823427U CN 204257636 U CN204257636 U CN 204257636U
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CN
China
Prior art keywords
chip
tape
substrate
internal memory
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201420823427.7U
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Chinese (zh)
Inventor
张伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitech Semiconductor Wuxi Co Ltd
Original Assignee
Hitech Semiconductor Wuxi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to CN201420823427.7U priority Critical patent/CN204257636U/en
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Publication of CN204257636U publication Critical patent/CN204257636U/en
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Die Bonding (AREA)

Abstract

The utility model belongs to integrated circuit board technical field, is specifically related to a kind of internal memory.The utility model adopts spatial tape to separate two chips, and four memory chips are stacked on substrate between two, and golden finger is to the chip encapsulation technology of parallel position being positioned at chip welding spot; Improve utilization rate of equipment and installations; Solve prior art and can only carry out one single chip encapsulation, the problem that equipment needed thereby, material and manpower are very expensive; Reduce chip package volume, decrease production cost.

Description

A kind of internal memory
Technical field
The utility model belongs to integrated circuit board technical field, is specifically related to a kind of internal memory.
Background technology
Chip package is the most frequently used operation in integrated circuit board field.Prior art is that one single chip carries out packaging and testing, and then carries out paster; Prior art can only carry out one single chip encapsulation, and equipment needed thereby, material and manpower are very expensive.
Summary of the invention
The purpose of this utility model is exactly the deficiency in order to overcome existing chip encapsulation technology, provides a kind of internal memory, solves owing to can only carry out one single chip encapsulation, the problem of wasting manpower and material resources.
In order to solve the problems of the technologies described above, the utility model is solved by following technical proposals:
A kind of internal memory, is characterized in that, comprise substrate, chip, paster adhesive tape, gold thread, spatial tape, epoxy-plastic packaging material, solder ball; Described chip is placed on paster adhesive tape, and four chips two two are stacked on substrate, are separated between two groups of chip by spatial tape; Described chip is connected by gold thread with substrate; Described chip, paster adhesive tape, gold thread and spatial tape are all in epoxy-plastic packaging material; Affiliated solder ball is placed in below substrate.
As preferably, described chip thickness is 70 μm.
As preferably, described Heraeus tape thickness is 100 μm.
As preferably, four chips two two are stacked on substrate.
As preferably, separated by spatial tape between two groups of chip.
Compared with prior art, the Advantageous Effects that brings of the utility model is as follows:
1. chip thickness little (70 μm), making the volume of encapsulation less, is the key of multi-chip package;
2. substrate thickness little (100 μm), the height of encapsulation is less;
3. the use of spatial tape, makes chip can be stacking, the size of the encapsulation of reduction;
4. upper and lower 2 chips use same golden finger to carry out bonding, and use different bonding radians, the size of the encapsulation of reduction;
5. use two chips paster and bonding techniques simultaneously, improve the utilization rate of equipment, decrease human cost.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
description of reference numerals:
1-substrate, 2-chip, 3-paster adhesive tape, 4-gold thread, 5-spatial tape, 6-epoxy-plastic packaging material, 7-solder ball.
Embodiment
Be further elaborated below in conjunction with accompanying drawing 1 pair of the utility model, but these embodiments do not form any restriction to the utility model.
A kind of internal memory, is characterized in that, comprise substrate, chip, paster adhesive tape, gold thread, spatial tape, epoxy-plastic packaging material, solder ball; Described chip is placed on paster adhesive tape, and four chips two two are stacked on substrate, are separated between two groups of chip by spatial tape; Described chip is connected by gold thread with substrate; Described chip, paster adhesive tape, gold thread and spatial tape are all in epoxy-plastic packaging material; Affiliated solder ball is placed in below substrate.
Preferably, described chip thickness is 70 μm; The little volume making to encapsulate of chip thickness is less, is the key of multi-chip package.
Preferably, described Heraeus tape thickness is 100 μm; The little height making to encapsulate of Heraeus tape thickness is less.
Preferably, four chips two two are stacked on substrate; Two chips paster and bonding techniques simultaneously, improves the utilization rate of equipment, decreases human cost.
Preferably, separated by spatial tape between two groups of chip; The use of spatial tape, makes chip can be stacking, the size of the encapsulation of reduction.
Those skilled in the art do not depart from essence of the present utility model and spirit, various deformation scheme can be had to realize the utility model, the foregoing is only the better feasible embodiment of the utility model, not thereby interest field of the present utility model is limited to, the equivalent structure change that all utilization the utility model specifications and accompanying drawing content are done, is all contained within interest field of the present utility model.

Claims (5)

1. an internal memory, is characterized in that, comprises substrate, chip, paster adhesive tape, gold thread, spatial tape, epoxy-plastic packaging material, solder ball; Described chip is placed on paster adhesive tape, and four chips two two are stacked on substrate, are separated between two groups of chip by spatial tape; Described chip is connected by gold thread with substrate; Described chip, paster adhesive tape, gold thread and spatial tape are all in epoxy-plastic packaging material; Affiliated solder ball is placed in below substrate.
2. internal memory according to claim 1, is characterized in that, described chip thickness is 70 μm.
3. internal memory according to claim 1, is characterized in that, described Heraeus tape thickness is 100 μm.
4. internal memory according to claim 1, is characterized in that, four chips two two are stacked on substrate.
5. internal memory according to claim 4, is characterized in that, is separated between two groups of chip by spatial tape.
CN201420823427.7U 2014-12-23 2014-12-23 A kind of internal memory Active CN204257636U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201420823427.7U CN204257636U (en) 2014-12-23 2014-12-23 A kind of internal memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201420823427.7U CN204257636U (en) 2014-12-23 2014-12-23 A kind of internal memory

Publications (1)

Publication Number Publication Date
CN204257636U true CN204257636U (en) 2015-04-08

Family

ID=52961913

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201420823427.7U Active CN204257636U (en) 2014-12-23 2014-12-23 A kind of internal memory

Country Status (1)

Country Link
CN (1) CN204257636U (en)

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