CN206441716U - It is a kind of to prevent the board structure of thin chip excessive glue - Google Patents
It is a kind of to prevent the board structure of thin chip excessive glue Download PDFInfo
- Publication number
- CN206441716U CN206441716U CN201621463843.6U CN201621463843U CN206441716U CN 206441716 U CN206441716 U CN 206441716U CN 201621463843 U CN201621463843 U CN 201621463843U CN 206441716 U CN206441716 U CN 206441716U
- Authority
- CN
- China
- Prior art keywords
- chip
- glue
- board structure
- bond regions
- prevent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Packages (AREA)
Abstract
The utility model be related to it is a kind of prevent the board structure of thin chip excessive glue, it include chip bond regions(1), the chip bond regions(1)It is dimensioned slightly smaller than chip size, the chip bond regions(1)Edge is provided with storage glue groove(2), the storage glue groove(2)Outside is provided with multiple routing fingers(3).The utility model is a kind of to prevent the board structure of thin chip excessive glue, and it can solve the problem that the problem of thin chip climbs glue.
Description
Technical field
The utility model be related to it is a kind of prevent the board structure of thin chip excessive glue, belong to technical field of semiconductor encapsulation.
Background technology
As electronic product especially portable mobile termianl is to high integration, lightening, miniaturization development, core is reduced
The inexorable trend for the microelectronics Packaging that piece volume is.
Adhering chip area size is slightly larger than chip size on traditional substrate, when chip is ultra-thin chip, needs simultaneously
When seeking certain glue thickness and coverage rate, on the one hand, chip, which is pushed, during load can cause the glue of chip surrounding to spill over chip upper surface;
On the other hand, due to the sinking and the flowing of glue of chip after the completion of load, glue can also spill over chip surface.Influence WB routings are made
Failed after into reliability.
Utility model content
Technical problem to be solved in the utility model is to provide one kind for above-mentioned prior art to prevent thin chip excessive glue
Board structure, it can solve the problem that the problem of thin chip climbs glue.
The technical scheme in the invention for solving the above technical problem is:It is a kind of to prevent the substrate knot of thin chip excessive glue
Structure, it includes chip bond regions, and the chip bond regions are dimensioned slightly smaller than chip size, and chip bond regions edge is set
It is equipped with the outside of storage glue groove, the storage glue groove and is provided with multiple routing fingers.
The glue groove that stores is the annular groove around chip bond regions edge.
It is described to store the rectangular channel that glue groove is multiple parallel arrangements around chip bond regions edge.
Compared with prior art, the utility model has the advantage of:
1st, substrate design feature:The chip of substrate bonds area edge and sets fluting, when ensureing the same of beneath chips coverage rate
When, unnecessary glue is flowed in substrate recess, prevents glue from climbing to chip upper surface;
2nd, technique is simple:It need to only be slotted on substrate by radium-shine mode;
3rd, it is widely applicable:It is applicable to different packing forms, organic substrate encapsulation or ceramic package etc..
Brief description of the drawings
Fig. 1 is a kind of structural representation for the board structure embodiment 1 for preventing thin chip excessive glue of the utility model.
Fig. 2 is Fig. 1 schematic cross-section.
Fig. 3 is a kind of structural representation for the board structure embodiment 2 for preventing thin chip excessive glue of the utility model.
Wherein:
Chip bond regions 1
Store glue groove 2
Routing finger 3.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing embodiment.
Embodiment 1:
As shown in Figure 1 and Figure 2, a kind of in the present embodiment prevents the board structure of thin chip excessive glue, and it includes chip and bonded
Area 1, the chip bond regions 1 are dimensioned slightly smaller than chip size, and the edge of chip bond regions 1 is provided with storage glue groove 2, institute
State the outside of storage glue groove 2 and be provided with multiple routing fingers 3.
The glue groove 2 that stores is the annular groove around the edge of chip bond regions 1.
Embodiment 2:
As shown in figure 3, the difference of embodiment 2 and embodiment 1 is:The storage glue groove 2 is around the surrounding of chip bond regions 1
The rectangular channel of multiple parallel arrangements at edge.
In addition to the implementation, the utility model also includes other embodiment, all use equivalents or equivalent
The technical scheme of substitute mode formation, all should fall within the utility model scope of the claims.
Claims (3)
1. a kind of prevent the board structure of thin chip excessive glue, it is characterised in that:It includes chip bond regions(1), the chip glue
Interface(1)It is dimensioned slightly smaller than chip size, the chip bond regions(1)Edge is provided with storage glue groove(2), the storage glue groove
(2)Outside is provided with multiple routing fingers(3).
2. a kind of the board structure of thin chip excessive glue is prevented according to claim 1, it is characterised in that:The storage glue groove
(2)For around chip bond regions(1)The annular groove of edge.
3. a kind of the board structure of thin chip excessive glue is prevented according to claim 1, it is characterised in that:The storage glue groove
(2)For around chip bond regions(1)The rectangular channel of multiple parallel arrangements of edge.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201621463843.6U CN206441716U (en) | 2016-12-29 | 2016-12-29 | It is a kind of to prevent the board structure of thin chip excessive glue |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201621463843.6U CN206441716U (en) | 2016-12-29 | 2016-12-29 | It is a kind of to prevent the board structure of thin chip excessive glue |
Publications (1)
Publication Number | Publication Date |
---|---|
CN206441716U true CN206441716U (en) | 2017-08-25 |
Family
ID=59641940
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201621463843.6U Active CN206441716U (en) | 2016-12-29 | 2016-12-29 | It is a kind of to prevent the board structure of thin chip excessive glue |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN206441716U (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111148370A (en) * | 2018-11-05 | 2020-05-12 | 光宝电子(广州)有限公司 | Semiconductor light emitting device and method for manufacturing the same |
CN113009648A (en) * | 2019-12-20 | 2021-06-22 | 青岛海信宽带多媒体技术有限公司 | Optical module |
US11927818B2 (en) | 2019-12-20 | 2024-03-12 | Hisense Broadband Multimedia Technologies Co., Ltd. | Optical module |
-
2016
- 2016-12-29 CN CN201621463843.6U patent/CN206441716U/en active Active
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN111148370A (en) * | 2018-11-05 | 2020-05-12 | 光宝电子(广州)有限公司 | Semiconductor light emitting device and method for manufacturing the same |
CN113009648A (en) * | 2019-12-20 | 2021-06-22 | 青岛海信宽带多媒体技术有限公司 | Optical module |
US11927818B2 (en) | 2019-12-20 | 2024-03-12 | Hisense Broadband Multimedia Technologies Co., Ltd. | Optical module |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20240128238A1 (en) | 3d system integration | |
US20210035955A1 (en) | Stacking integrated circuits containing serializer and deserializer blocks using through via | |
CN206441716U (en) | It is a kind of to prevent the board structure of thin chip excessive glue | |
KR102191669B1 (en) | Multi-chip package | |
SG163445A1 (en) | Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies | |
CN104078439A (en) | Semiconductor device and manufacturing method thereof | |
CN206864460U (en) | A kind of encapsulating structure for preventing chip excessive glue | |
WO2012021641A3 (en) | Stitch bump stacking design for overall package size reduction for multiple stack | |
CN203721707U (en) | Chip packaging structure | |
CN105118827A (en) | Three-dimensional chip stack packaging structure based on flexible substrate and packaging method | |
US20120100669A1 (en) | Method of manufacturing tmv package-on-package device | |
US6937477B2 (en) | Structure of gold fingers | |
CN102157477B (en) | Method for manufacturing semiconductor device | |
CN104183555B (en) | Semiconductor package and fabrication method thereof | |
CN203774319U (en) | Stackable packaging structure | |
WO2010144823A3 (en) | Method for manufacturing tight pitch, flip chip integrated circuit packages | |
CN206401303U (en) | A kind of chip-packaging structure for hindering glue | |
CN207651480U (en) | A kind of two access TVS devices | |
CN108630626A (en) | Without substrate encapsulation structure | |
CN202434508U (en) | Semiconductor chip stacking and encapsulating structure | |
CN105742197A (en) | Bonding wafer structure and preparation method therefor | |
CN105895587A (en) | Method for overcoming layering of substrate and die through bonding performance of DAF and low-roughness silicon wafer | |
CN204257636U (en) | A kind of internal memory | |
CN204361080U (en) | Circuits System and chip package thereof | |
CN219873533U (en) | Separated device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
GR01 | Patent grant | ||
GR01 | Patent grant |