CN203707109U - 一种多集成三极管 - Google Patents

一种多集成三极管 Download PDF

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CN203707109U
CN203707109U CN201420033139.1U CN201420033139U CN203707109U CN 203707109 U CN203707109 U CN 203707109U CN 201420033139 U CN201420033139 U CN 201420033139U CN 203707109 U CN203707109 U CN 203707109U
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bonding pad
base
triode
hole
layer
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黄佳
叶文浩
李建球
杨晓智
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SHENZHEN PENGWEI TECHNOLOGY CO LTD
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SHENZHEN PENGWEI TECHNOLOGY CO LTD
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Abstract

本实用新型公开了一种多集成三极管，其包括：封装胶壳（1），封装在封装胶壳内的三极管芯片（2）和二极管芯片（3）；三极管芯片的发射极层和基极层之间设有沟道电阻（R），二极管芯片连接在三极管的发射极和基极之间。本实用新型将三极管、二极管、电阻集成封装在一起,节省了制备三件分立元件的材料，还可用小功率三极管替代大功率三极管，有利于降低元件成本，减小PCB板面积和电子产品体积。

Description

一种多集成三极管
技术领域
本实用新型涉及三极管，尤其涉及一种将普通三极管芯片中集成电阻后，再将该集成三极管芯片和二极管封装在一起的新型多集成三极管。
背景技术
目前市面上输入电源电压在200-240V的条件下，使用的电子镇流器及荧光灯的电路中，有一种在DB3触发管的半桥电路中，采用开关功率三极管作为开关元件，会在基极与发射极之间并接一个电阻的，该线路中还会在其基极与发射极之间反向并接二极管，在现有技术大多采用分立的二极管和三极管组合、电阻与三极管分立使用，其缺陷是占用更多的PCB空间，不利于产品的小型化，且三个器件独立封装浪费更多的成本和材料。故此开发一种将三极管、二极管、电阻集成在一起的多集成三极管，是业内亟需解决的技术问题。
实用新型内容
本实用新型是要解决现有技术的上述问题，提出将三极管、二极管、电阻集成在一起的多集成三极管。
为解决上述技术问题，本实用新型提出的技术方案是设计一种多集成三极管，其包括：封装胶壳，封装在封装胶壳内的三极管芯片和二极管芯片；所述三极管芯片包含发射极层、包在发射极层周边和底面的基极层、包在基极层周边和底面的高阻层、贴在高阻层底面的集电极层，所述发射极层、基极层、高阻层的顶面平齐并在其上设有绝缘层，位于基极层上方的绝缘层中设有通孔、该通孔内设有用于连接基极层的基电极，发射极层中设有一个贯通的基区孔，该基区孔上方的绝缘层中设有通孔、该通孔和基区孔内设有用于连接发射极层的发射电极，发射电极在基区孔的底端连接发射极层、在基电极和发射电极之间的基极层中形成一个沟道电阻，集电极层底部焊接第一焊接片；所述二极管芯片包含由上而下叠置的阳极和阴极，该阴极底部焊接第二焊接片，所述阳极通过导线连接所述发射电极，基电极通过导线与第二焊接片焊接，发射电极通过导线与第三焊接片焊接，第一、第二、第三焊接片分别连接一端伸出封装胶壳之外的第一、第二、第三引脚。
所述第一焊接片和第一引脚为一整体，所述第二焊接片和第二引脚为一整体，所述第三焊接片和第三引脚为一整体。
所述第一焊接片、第二焊接片、第三焊接片处于同一平面。
所述第一、第二、第三焊接片之间留有间隙互不接触，各导线之间留有间隙互不接触。
与现有技术相比，本实用新型将三极管、二极管、电阻集成封装在一起,节省了制备三件分立元件的材料，降低了元件成本；三极管的Ic电流能力提高，Tf明显降低，减少开通损耗和开关时间，VCEO降低；可用小功率（小面积芯片）三极管替代大功率（大面积芯片）三极管，减小封装体积，进一步降低成本；使用本集成三极管，有利于减小PCB板面积，减小电子产品体积；广泛适用于电源电压为200-240V的半桥电路小功率照明电器中。
附图说明
图1为本实用新型较佳实施例的横截面示意图；
图2为本实用新型较佳实施例的电路原理图；
图3为本实用新型较佳实施例的内部立体结构示意图；
图4为本实用新型较佳实施例外观示意图。
具体实施方式
为了使本实用新型的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本实用新型作进一步详细说明。应当理解，此处所描述的具体实施例仅仅用于解释本实用新型，并不用于限定本实用新型。
本实用新型揭示了一种多集成三极管，将已集成电阻的三极管和连接三极管基极与发射极的二极管封装在一起。封装后的效果如图4所示，一个封装胶壳1外露三条引脚7、8、9。
参看图1示出的本实用新型较佳实施例横截面示意图，其包括：封装胶壳1，封装在封装胶壳内的三极管芯片2和二极管芯片3；所述三极管芯片包含发射极层2e、包在发射极层周边和底面的基极层2b、包在基极层周边和底面的高阻层2n、贴在高阻层底面的集电极层2c，所述发射极层、基极层、高阻层的顶面平齐并在其上设有绝缘层2d，位于基极层上方的绝缘层中设有通孔、该通孔内设有用于连接基极层的基电极2b1，发射极层中设有一个贯通的基区孔22，该基区孔上方的绝缘层中设有通孔、该通孔和基区孔内设有用于连接发射极层的发射电极2e1，发射电极在基区孔的底端连接发射极层、在基电极和发射电极之间的基极层中形成一个沟道电阻R，集电极层底部焊接第一焊接片4；所述二极管芯片包含由上而下叠置的阳极和阴极，该阴极底部焊接第二焊接片5，述阳极通过导线10连接所述发射电极，基电极2b1通过导线10与第二焊接片5焊接，发射电极通过导线10与第三焊接片6焊接，第一、第二、第三焊接片分别连接一端伸出封装胶壳之外的第一、第二、第三引脚7、8、9。
该技术从应用角度分析，三极管基极和发射极并联集成一个电阻，可以使VCBO与VCEO相等，可以使电子镇流器及荧光灯的电路中的开关三极管采用VCEO电压较低芯片替代VCEO高压芯片，并可以使用面积小芯片替代大面积芯片，从成本上节约。
在较佳实施例中，发射极层2e采用N+，基极层2b采用P，高阻层2n采用N-，集电极层2c采用N+。这样制成的集成三极管为NPN型三极管。绝缘层2d采用二氧化硅（SIO2），发射电极2e1和基电极2b1采用铝材。所述高阻层在位于基极层与集电极之间处的厚度为50微米。所述集电极采用电阻率为30Ω·cm至40Ω·cm的单晶硅。
本实用新型的电路原理如图2所示，三极管2的基极B和发射极E之间连接并联的二极管和电阻，二极管阳极连接发射极E、阴极连接基极B。
在较佳实施例中，所述第一焊接片4和第一引脚7为一整体，所述第二焊接片5和第二引脚8为一整体，所述第三焊接片6和第三引脚9为一整体。图3示出了较佳实施例的内部立体结构。
为了方便加工制造，第一焊接片4、第二焊接片5、第三焊接片6处于同一平面。
在较佳实施例中，第一、第二、第三焊接片之间留有间隙互不接触，以保持彼此之间绝缘；各导线10之间留有间隙互不接触，以保持彼此之间绝缘。
综上所述，本实用新型在发射极层2e上留一个基区孔，使发射极层上方的发射电极2e1与发射极层下方的基极层2b连接，由于基极层本身具有电阻，此结构相当于在发射极和基极之间连接了一个电阻；同时通过第一引脚7与第一焊接片4作为三极管的集电极，第二引脚8与第二焊接片5作为三极管的基极，第三引脚9与第三焊接片6作为三极管的发射极，第二焊接片5通过导线10与基极连接，第二焊接片上还连接二极管阴极，二极管阳极通过导线10与三极管发射极连接（或与第三焊接片6连接），第三焊接片6通过导线10与三极管发射极连接。然后将三极管和二极管封装在封装胶壳1内。以上实施例仅为举例说明，非起限制作用。任何未脱离本申请精神与范畴，而对其进行的等效修改或变更，均应包含于本申请的权利要求范围之中。

Claims (4)

1.一种多集成三极管，其特征在于包括：封装胶壳（1），封装在封装胶壳内的三极管芯片（2）和二极管芯片（3）；
所述三极管芯片包含发射极层（2e）、包在发射极层周边和底面的基极层（2b）、包在基极层周边和底面的高阻层（2n）、贴在高阻层底面的集电极层（2c），所述发射极层、基极层、高阻层的顶面平齐并在其上设有绝缘层（2d），位于基极层上方的绝缘层中设有通孔、该通孔内设有用于连接基极层的基电极（2b1），发射极层中设有一个贯通的基区孔（22），该基区孔上方的绝缘层中设有通孔、该通孔和基区孔内设有用于连接发射极层的发射电极（2e1），发射电极在基区孔的底端连接发射极层、在基电极和发射电极之间的基极层中形成一个沟道电阻（R），集电极层底部焊接第一焊接片（4）；
所述二极管芯片包含由上而下叠置的阳极和阴极，该阴极底部焊接第二焊接片（5），所述阳极通过导线连接所述发射电极，基电极通过导线与第二焊接片焊接，发射电极通过导线与第三焊接片（6）焊接，第一、第二、第三焊接片分别连接一端伸出封装胶壳之外的第一、第二、第三引脚（7、8、9）。
2.如权利要求1所述的多集成三极管，其特征在于：所述第一焊接片（4）和第一引脚（7）为一整体，所述第二焊接片（5）和第二引脚（8）为一整体，所述第三焊接片（6）和第三引脚（9）为一整体。
3.如权利要求2所述的多集成三极管，其特征在于：所述第一焊接片（4）、第二焊接片（5）、第三焊接片（6）处于同一平面。
4.如权利要求3所述的多集成三极管，其特征在于：所述第一、第二、第三焊接片之间留有间隙互不接触，各导线之间留有间隙互不接触。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3018710A1 (en) * 2014-11-10 2016-05-11 Nxp B.V. Arrangement of semiconductor dies
CN111063723A (zh) * 2019-11-25 2020-04-24 深圳深爱半导体股份有限公司 开关集成控制器和三极管芯片

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3018710A1 (en) * 2014-11-10 2016-05-11 Nxp B.V. Arrangement of semiconductor dies
US9685396B2 (en) 2014-11-10 2017-06-20 Nxp B.V. Semiconductor die arrangement
CN111063723A (zh) * 2019-11-25 2020-04-24 深圳深爱半导体股份有限公司 开关集成控制器和三极管芯片
CN111063723B (zh) * 2019-11-25 2021-12-28 深圳深爱半导体股份有限公司 开关集成控制器

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