CN203707109U - Multi-integration triode - Google Patents
Multi-integration triode Download PDFInfo
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- CN203707109U CN203707109U CN201420033139.1U CN201420033139U CN203707109U CN 203707109 U CN203707109 U CN 203707109U CN 201420033139 U CN201420033139 U CN 201420033139U CN 203707109 U CN203707109 U CN 203707109U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1203—Rectifying Diode
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Abstract
The utility model discloses a multi-integration triode which comprises a package rubber shell (1), a triode chip (2) packaged in the package rubber shell (1), and a diode chip (3) packaged in the package rubber shell (1). A channel resistor (R) is arranged between the emitter layer and the base electrode layer of the triode chip. The diode chip is connected between the emitter and the base electrode of the triode chip. According to the multi-integration triode, the triode, the diode and the resistor are packaged together, the material of preparing three discrete components is saved, a large power triode can be substituted by a small power triode, the reduction of element cost is facilitated, and the area of a PCB and the volume of an electronic product are reduced.
Description
Technical field
The utility model relates to triode, relate in particular to a kind of by after integrated resistor in common triode chip, then by this integrated triode chip the novel many integrated triodes together with diode package.
Background technology
Current input supply voltage is on the market under the condition of 200-240V, in the electric ballast using and the circuit of fluorescent lamp, have a kind of in the half-bridge circuit of DB3 trigger tube, adopt switch power triode as switch element, can be between base stage and emitter and connect a resistance, also can be between its base stage and emitter in this circuit oppositely and connect diode, mostly adopt discrete diode and triode combination in prior art, the discrete use of resistance and triode, its defect is to take more PCB space, be unfavorable for the miniaturization of product, and three device individual packages are wasted more cost and material.So develop a kind of many integrated triodes that triode, diode, resistance are integrated, it is the technical problem of needing in the industry solution badly.
Utility model content
The utility model is the problems referred to above that will solve prior art, proposes many integrated triodes that triode, diode, resistance are integrated.
For solving the problems of the technologies described above, the technical scheme the utility model proposes is a kind of many integrated triodes of design, and it comprises: packaging plastic shell, is encapsulated in triode chip and diode chip for backlight unit in packaging plastic shell, described triode chip comprises emitter layer, wrap in the base layer of emitter layer periphery and bottom surface, wrap in the resistive formation of base layer periphery and bottom surface, be attached to the collector layer of resistive formation bottom surface, described emitter layer, base layer, the end face of resistive formation is concordant and be provided with insulating barrier thereon, the insulating barrier that is arranged in base layer top is provided with through hole, in this through hole, be provided with the base electrode for connecting base layer, in emitter layer, be provided with the hole, base of a perforation, in the insulating barrier of this top, hole, base, be provided with through hole, this through hole is provided with the emission electrode for being connected emitter layer with in hole, base, emission electrode connects emitter layer in the bottom in hole, base, in base layer between base electrode and emission electrode, form a channel resistance, collector layer bottom welding the first bonding pad, described diode chip for backlight unit comprises from top to bottom stacked anode and negative electrode, this cathode bottom is welded the second bonding pad, described anode connects described emission electrode by wire, base electrode is by wire and the welding of the second bonding pad, emission electrode is by wire and the welding of the 3rd bonding pad, and first, second, third bonding pad connects respectively one end and stretches out first, second, third pin outside packaging plastic shell.
Described the first bonding pad and the first pin are an entirety, and described the second bonding pad and the second pin are an entirety, and described the 3rd bonding pad and the 3rd pin are an entirety.
Described the first bonding pad, the second bonding pad, the 3rd bonding pad are in same plane.
Between described first, second, third bonding pad, leave gap and do not contact mutually, between each wire, leave gap and do not contact mutually.
Compared with prior art, the utility model by triode, diode, resistance integration packaging together, has been saved the material of preparing three discrete components, has reduced element cost; The Ic current capacity of triode improves, and Tf obviously reduces, and reduces turn-on consumption and switching time, and VCEO reduces; Available small-power (small size chip) triode substitutes high-power (large-area chips) triode, reduces encapsulation volume, further reduces costs; Use this integrated triode, be conducive to reduce pcb board area, reduce electronic product volume; Being widely used in supply voltage is in the half-bridge circuit small-power electric lighting of 200-240V.
Accompanying drawing explanation
Fig. 1 is the cross sectional representation of the utility model preferred embodiment;
Fig. 2 is the circuit theory diagrams of the utility model preferred embodiment;
Fig. 3 is the inside perspective view of the utility model preferred embodiment;
Fig. 4 is the utility model preferred embodiment schematic appearance.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is described in further detail.Should be appreciated that specific embodiment described herein is only for explaining the utility model, and be not used in restriction the utility model.
The utility model has disclosed a kind of many integrated triodes, together with the diode package of the triode of integrated resistor and connecting triode base stage and emitter.As shown in Figure 4, a packaging plastic shell 1 exposes three pins 7,8,9 to effect after encapsulation.
Referring to the utility model preferred embodiment cross sectional representation shown in Fig. 1, it comprises: packaging plastic shell 1, is encapsulated in triode chip 2 and diode chip for backlight unit 3 in packaging plastic shell, described triode chip comprises emitter layer 2e, wrap in the base layer 2b of emitter layer periphery and bottom surface, wrap in the resistive formation 2n of base layer periphery and bottom surface, be attached to the collector layer 2c of resistive formation bottom surface, described emitter layer, base layer, the end face of resistive formation is concordant and be provided with insulating barrier 2d thereon, the insulating barrier that is arranged in base layer top is provided with through hole, in this through hole, be provided with the base electrode 2b1 for connecting base layer, in emitter layer, be provided with the hole, base 22 of a perforation, in the insulating barrier of this top, hole, base, be provided with through hole, this through hole and the emission electrode 2e1 being provided with in hole, base for being connected emitter layer, emission electrode connects emitter layer in the bottom in hole, base, in base layer between base electrode and emission electrode, form a channel resistance R, collector layer bottom welding the first bonding pad 4, described diode chip for backlight unit comprises from top to bottom stacked anode and negative electrode, this cathode bottom is welded the second bonding pad 5, state anode and connect described emission electrode by wire 10, base electrode 2b1 welds by wire 10 and the second bonding pad 5, emission electrode welds by wire 10 and the 3rd bonding pad 6, and first, second, third bonding pad connects respectively one end and stretches out first, second, third pin 7,8,9 outside packaging plastic shell.
This technology is from application point analysis, a transistor base and emitter integrated resistance in parallel, can make VCBO equate with VCEO, can make the switch triode in the circuit of electric ballast and fluorescent lamp adopt the lower chip of VCEO voltage to substitute VCEO high pressure chip, and can substitute large-area chips by the little chip of usable floor area, save from cost.
In preferred embodiment, emitter layer 2e adopts N+, and base layer 2b adopts P, and resistive formation 2n adopts N-, and collector layer 2c adopts N+.The integrated triode of making is like this NPN type triode.Insulating barrier 2d adopts silicon dioxide (SIO2), and emission electrode 2e1 and base electrode 2b1 adopt aluminium.Described resistive formation is 50 microns at the thickness of locating between base layer and collector electrode.It is the monocrystalline silicon of 30 Ω cm to 40 Ω cm that described collector electrode adopts resistivity.
Circuit theory of the present utility model as shown in Figure 2, connects diode in parallel and resistance between the base stage B of triode 2 and emitter E, diode anode connects emitter E, negative electrode connects base stage B.
In preferred embodiment, described the first bonding pad 4 and the first pin 7 are an entirety, and described the second bonding pad 5 and the second pin 8 are an entirety, and described the 3rd bonding pad 6 and the 3rd pin 9 are an entirety.Fig. 3 shows the inside stereochemical structure of preferred embodiment.
In order to facilitate processing and manufacturing, the first bonding pad 4, the second bonding pad 5, the 3rd bonding pad 6 are in same plane.
In preferred embodiment, between first, second, third bonding pad, leave gap and do not contact mutually, insulate each other keeping; Between each wire 10, leave gap and do not contact mutually, insulate each other keeping.
In sum, the utility model stays hole, a base on emitter layer 2e, the emission electrode 2e1 of emitter layer top is connected with the base layer 2b of emitter layer below, and because base layer itself has resistance, this structure is equivalent to connect a resistance between emitter and base stage; Pass through the first pin 7 and the first bonding pad 4 collector electrode as triode simultaneously, the second pin 8 and the second bonding pad 5 are as the base stage of triode, the 3rd pin 9 and the 3rd bonding pad 6 are as the emitter of triode, the second bonding pad 5 is connected with base stage by wire 10, on the second bonding pad, also connect diode cathode, diode anode is connected (or being connected with the 3rd bonding pad 6) by wire 10 with transistor emitter, the 3rd bonding pad 6 is connected with transistor emitter by wire 10.Then by triode and diode package in packaging plastic shell 1.Above embodiment is only for illustrating, non-providing constraints.Anyly do not depart from the application's spirit and category, and equivalent modifications or change that it is carried out all should be contained among the application's claim scope.
Claims (4)
1. an integrated triode more than, is characterized in that comprising: packaging plastic shell (1), is encapsulated in triode chip (2) and diode chip for backlight unit (3) in packaging plastic shell;
Described triode chip comprises emitter layer (2e), wrap in the base layer (2b) of emitter layer periphery and bottom surface, wrap in the resistive formation (2n) of base layer periphery and bottom surface, be attached to the collector layer (2c) of resistive formation bottom surface, described emitter layer, base layer, the end face of resistive formation is concordant and be provided with insulating barrier (2d) thereon, the insulating barrier that is arranged in base layer top is provided with through hole, in this through hole, be provided with the base electrode (2b1) for connecting base layer, in emitter layer, be provided with the hole, base (22) of a perforation, in the insulating barrier of this top, hole, base, be provided with through hole, this through hole and the emission electrode (2e1) being provided with in hole, base for being connected emitter layer, emission electrode connects emitter layer in the bottom in hole, base, in base layer between base electrode and emission electrode, form a channel resistance (R), collector layer bottom welding the first bonding pad (4),
Described diode chip for backlight unit comprises from top to bottom stacked anode and negative electrode, this cathode bottom is welded the second bonding pad (5), described anode connects described emission electrode by wire, base electrode is by wire and the welding of the second bonding pad, emission electrode is by wire and the welding of the 3rd bonding pad (6), and first, second, third bonding pad connects respectively one end and stretches out first, second, third pin (7,8,9) outside packaging plastic shell.
2. many integrated triodes as claimed in claim 1, it is characterized in that: described the first bonding pad (4) and the first pin (7) are an entirety, described the second bonding pad (5) and the second pin (8) are an entirety, and described the 3rd bonding pad (6) and the 3rd pin (9) are an entirety.
3. many integrated triodes as claimed in claim 2, is characterized in that: described the first bonding pad (4), the second bonding pad (5), the 3rd bonding pad (6) are in same plane.
4. many integrated triodes as claimed in claim 3, is characterized in that: between described first, second, third bonding pad, leave gap and do not contact mutually, leave gap and do not contact mutually between each wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420033139.1U CN203707109U (en) | 2014-01-20 | 2014-01-20 | Multi-integration triode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420033139.1U CN203707109U (en) | 2014-01-20 | 2014-01-20 | Multi-integration triode |
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| Publication Number | Publication Date |
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| CN203707109U true CN203707109U (en) | 2014-07-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420033139.1U Expired - Fee Related CN203707109U (en) | 2014-01-20 | 2014-01-20 | Multi-integration triode |
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| CN (1) | CN203707109U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3018710A1 (en) * | 2014-11-10 | 2016-05-11 | Nxp B.V. | Arrangement of semiconductor dies |
| CN110970412A (en) * | 2019-12-18 | 2020-04-07 | 深圳成光兴光电技术股份有限公司 | Integrated packaging structure and circuit of photoelectric receiving diode and triode |
| CN111063723A (en) * | 2019-11-25 | 2020-04-24 | 深圳深爱半导体股份有限公司 | Switch integrated controller and triode chip |
-
2014
- 2014-01-20 CN CN201420033139.1U patent/CN203707109U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3018710A1 (en) * | 2014-11-10 | 2016-05-11 | Nxp B.V. | Arrangement of semiconductor dies |
| US9685396B2 (en) | 2014-11-10 | 2017-06-20 | Nxp B.V. | Semiconductor die arrangement |
| CN111063723A (en) * | 2019-11-25 | 2020-04-24 | 深圳深爱半导体股份有限公司 | Switch integrated controller and triode chip |
| CN111063723B (en) * | 2019-11-25 | 2021-12-28 | 深圳深爱半导体股份有限公司 | Switch integrated controller |
| CN110970412A (en) * | 2019-12-18 | 2020-04-07 | 深圳成光兴光电技术股份有限公司 | Integrated packaging structure and circuit of photoelectric receiving diode and triode |
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Granted publication date: 20140709 Termination date: 20160120 |
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| EXPY | Termination of patent right or utility model |