CN203644776U - 一种低反压bed集成功率三极管 - Google Patents

一种低反压bed集成功率三极管 Download PDF

Info

Publication number
CN203644776U
CN203644776U CN201320804410.2U CN201320804410U CN203644776U CN 203644776 U CN203644776 U CN 203644776U CN 201320804410 U CN201320804410 U CN 201320804410U CN 203644776 U CN203644776 U CN 203644776U
Authority
CN
China
Prior art keywords
triode
bonding pad
integrated power
chip
pin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201320804410.2U
Other languages
English (en)
Inventor
黄佳
叶文浩
李建球
杨晓智
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SHENZHEN PENGWEI TECHNOLOGY CO LTD
Original Assignee
SHENZHEN PENGWEI TECHNOLOGY CO LTD
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SHENZHEN PENGWEI TECHNOLOGY CO LTD filed Critical SHENZHEN PENGWEI TECHNOLOGY CO LTD
Priority to CN201320804410.2U priority Critical patent/CN203644776U/zh
Application granted granted Critical
Publication of CN203644776U publication Critical patent/CN203644776U/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Led Devices (AREA)

Abstract

本实用新型公开了一种低反压BED集成功率三极管，包括：封装胶壳（1）及其内部的三极管芯片（2）和二极管芯片（3），三极管芯片焊在第一焊接片（4）上，二极管芯片焊在第二焊接片（5）上，三极管芯片的发射极层通过导线焊接第三焊接片（6），第一、第二、第三焊接片分别连接伸出封装胶壳的第一、第二、第三引脚（7、8、9）。本实用新型将三极管与二极管的集成在一起，有利于产品的小型化，更加节省材料和制作成本；同时提高了三极管的Ic电流，降低了Tf减少开通损耗和开关时间，降低VCEO；可用小功率（小面积芯片）三极管替代大功率（大面积芯片）三极管，有利于进一步减小封装体积，降低成本。

Description

一种低反压BED集成功率三极管
技术领域
本实用新型涉及三极管，尤其涉及一种将三极管和二极管封装在一起的低反压BED集成功率三极管。
背景技术
目前市面上输入电源电压在200-240V的条件下，使用的电子镇流器及荧光灯的电路中，广泛采用开关功率三极管作为开关元件，并且在其基极与发射极之间反向并接二极管，在现有技术大多采用分立的二极管和三极管组合使用，其缺陷是占用更多的PCB空间，不利于产品的小型化，且两个器件独立封装浪费更多的成本和材料。故此开发一种将三极管与二极管的集成在一起的具有低反压的功率三极管，是业内亟需解决的技术问题。
实用新型内容
本实用新型是要解决现有技术的上述问题，提出一种将三极管与二极管的集成在一起的具有低反压的功率三极管。
为解决上述技术问题，本实用新型提出的技术方案是设计一种低反压BED集成功率三极管，其包括：封装胶壳，封装在封装胶壳内的三极管芯片和二极管芯片，所述三极管芯片包含由上而下叠置的发射极层、基极层、高阻层、集电极，该集电极底部焊接第一焊接片，所述二极管芯片包含由上而下叠置的阳极和阴极，该阴极底部焊接第二焊接片，所述阳极通过导线连接所述发射极层，基极层通过导线与第二焊接片焊接，发射极层通过导线与第三焊接片焊接，第一、第二、第三焊接片分别连接一端伸出封装胶壳之外的第一、第二、第三引脚。
所述高阻层在位于基极层与集电极之间处的厚度为50微米。
所述集电极采用电阻率为30Ω·cm至40Ω·cm的单晶硅。
所述第一焊接片和第一引脚为一整体，所述第二焊接片和第二引脚为一整体，所述第三焊接片和第三引脚为一整体。
所述第一焊接片、第二焊接片、第三焊接片处于同一平面。
所述第一、第二、第三焊接片之间留有间隙互不接触，各导线之间留有间隙互不接触。
与现有技术相比，本实用新型将三极管与二极管的集成在一起，有利于产品的小型化，更加节省材料和制作成本；采用新型的结构，三极管的Ic电流能力提高，Tf明显降低，减少开通损耗和开关时间，VCEO降低；可用小功率（小面积芯片）三极管替代大功率（大面积芯片）三极管，减小封装体积，降低成本；广泛适用于电源电压为200-240V的半桥电路小功率照明电器中。
附图说明
下面结合附图和实施例对本实用新型作出详细的说明，其中：
图1为本实用新型较佳实施例的横截面示意图；
图2为本实用新型较佳实施例的电路原理图；
图3为本实用新型较佳实施例的内部立体结构示意图；
图4为本实用新型较佳实施例外观示意图。
具体实施方式
本实用新型揭示了一种低反压BED集成功率三极管，本实用新型是将三极管和连接三极管基极与发射极的二极管封装在一起。封装后的效果如图4所示，一个封装胶壳1外露三条引脚7、8、9。
参看图1示出的本实用新型较佳实施例横截面示意图，其包括：封装胶壳1，封装在封装胶壳内的三极管芯片2和二极管芯片3，所述三极管芯片包含由上而下叠置的发射极层2e、基极层2b、高阻层2n、集电极2c，该集电极底部焊接第一焊接片4，所述二极管芯片包含由上而下叠置的阳极和阴极，该阴极底部焊接第二焊接片5，所述阳极通过导线10连接所述发射极层，基极层通过导线10与第二焊接片5焊接，发射极层通过导线10与第三焊接片6焊接，第一、第二、第三焊接片分别连接一端伸出封装胶壳之外的第一、第二、第三引脚7、8、9。
本实用新型的电路原理如图2所示，三极管2的基极B和发射极E之间连接二极管，二极管阳极连接发射极E、阴极连接基极B。
在较佳实施例中，高阻层2n在位于基极层2b与集电极2c之间处的厚度L为50微米。集电极2c采用电阻率为30Ω·cm至40Ω·cm的单晶硅。这样的结构能使饱和压降大幅度降低，通过大量实验证明BVCEO≤390V-450V，BED集成功率三极管的Tf(下降时间)同比BVCE0≥420V减少，BED集成功率三极管BVCEO≤390V-450V的温升比BVCE0≥420V相等或小，输出功率基本一致,且大幅度降低饱和压降，IC电流能力提高，减少开通损耗，开关时间减少，VCEO降低。可以实现降低成本（可以用小面积芯片替代大面积芯片），同时还可以用于小封装结构替代大封装结构。
在较佳实施例中，所述第一焊接片4和第一引脚7为一整体，所述第二焊接片5和第二引脚8为一整体，所述第三焊接片6和第三引脚9为一整体。图3示出了较佳实施例的内部立体结构。
为了方便加工制造，第一焊接片4、第二焊接片5、第三焊接片6处于同一平面。
在较佳实施例中，第一、第二、第三焊接片之间留有间隙互不接触，以保持彼此之间绝缘；各导线10之间留有间隙互不接触，以保持彼此之间绝缘。
综上所述，本实用新型，通过第一引脚7与第一焊接片4作为三极管的集电极，第二引脚8与第二焊接片5作为三极管的基极，第三引脚9与第三焊接片6作为三极管的发射极，第二焊接片5通过导线10与基极连接，第二焊接片上还连接二极管阴极，二极管阳极通过导线10与三极管发射极连接（或与第三焊接片6连接），第三焊接片6通过导线10与三极管发射极连接。然后将三极管和二极管封装在封装胶壳1内。同时本实用新型中的三极管还采用低电阻率的单晶硅，薄的高阻层2n，提高Ic，降低Tf，减少开通损耗和开关时间。
以上实施例仅为举例说明，非起限制作用。任何未脱离本申请精神与范畴，而对其进行的等效修改或变更，均应包含于本申请的权利要求范围之中。

Claims (6)

1.一种低反压BED集成功率三极管，其特征在于包括：封装胶壳（1），封装在封装胶壳内的三极管芯片（2）和二极管芯片（3），所述三极管芯片包含由上而下叠置的发射极层（2e）、基极层（2b）、高阻层（2n）、集电极（2c），该集电极底部焊接第一焊接片（4），所述二极管芯片包含由上而下叠置的阳极和阴极，该阴极底部焊接第二焊接片（5），所述阳极通过导线连接所述发射极层，基极层通过导线与第二焊接片焊接，发射极层通过导线与第三焊接片（6）焊接，第一、第二、第三焊接片分别连接一端伸出封装胶壳之外的第一、第二、第三引脚（7、8、9）。
2.如权利要求1所述的低反压BED集成功率三极管，其特征在于：所述高阻层（2n）在位于基极层（2b）与集电极（2c）之间处的厚度为50微米。
3.如权利要求2所述的低反压BED集成功率三极管，其特征在于：所述集电极（2c）采用电阻率为30Ω·cm至40Ω·cm的单晶硅。
4.如权利要求3所述的低反压BED集成功率三极管，其特征在于：所述第一焊接片（4）和第一引脚（7）为一整体，所述第二焊接片（5）和第二引脚（8）为一整体，所述第三焊接片（6）和第三引脚（9）为一整体。
5.如权利要求4所述的低反压BED集成功率三极管，其特征在于：所述第一焊接片（4）、第二焊接片（5）、第三焊接片（6）处于同一平面。
6.如权利要求5所述的低反压BED集成功率三极管，其特征在于：所述第一、第二、第三焊接片之间留有间隙互不接触，各导线之间留有间隙互不接触。
CN201320804410.2U 2013-12-10 2013-12-10 一种低反压bed集成功率三极管 Expired - Fee Related CN203644776U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201320804410.2U CN203644776U (zh) 2013-12-10 2013-12-10 一种低反压bed集成功率三极管

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201320804410.2U CN203644776U (zh) 2013-12-10 2013-12-10 一种低反压bed集成功率三极管

Publications (1)

Publication Number Publication Date
CN203644776U true CN203644776U (zh) 2014-06-11

Family

ID=50876001

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201320804410.2U Expired - Fee Related CN203644776U (zh) 2013-12-10 2013-12-10 一种低反压bed集成功率三极管

Country Status (1)

Country Link
CN (1) CN203644776U (zh)

Similar Documents

Publication Publication Date Title
TWI415309B (zh) Preform Molded Polycrystalline Bearing Modules with Lead Frame Type
WO2014101338A1 (zh) 一种低寄生电感的igbt功率模块
CN206282838U (zh) 无源器件与有源器件的集成封装结构
CN101630676A (zh) 新型直接敷铜基板布局的绝缘栅双极性晶体管模块
CN213635985U (zh) 电源模组及其芯片封装结构
CN203707109U (zh) 一种多集成三极管
CN202949568U (zh) 一种大功率mems麦克风
CN201508835U (zh) 新型直接敷铜基板布局的绝缘栅双极性晶体管模块
CN101714544A (zh) 一种集成三极管及其制造方法
CN203644776U (zh) 一种低反压bed集成功率三极管
CN106449517B (zh) 一种堆叠式单基岛sip封装工艺
CN213905350U (zh) 电源模组及其芯片封装结构
CN214753737U (zh) 一种可以封装倒装ic芯片的支架及电子元器件
CN202259441U (zh) 一种新型led芯片
CN107482108A (zh) 一种新型smd灯珠
CN203721720U (zh) 一种双二极管串联连接的器件
CN203774321U (zh) 一种用于sot23半导体的双二极管封装结构
CN210723007U (zh) 一种用于集成功率模块的引线框架
CN201549504U (zh) 一种集成三极管
CN207165614U (zh) 一种新型smd灯珠
CN101661919A (zh) 大功率晶体管
CN111681997A (zh) 功率封装模块及电子装置
CN203910795U (zh) 一种系统级led封装器件
CN202996833U (zh) 一种复合封装的igbt器件
CN214313181U (zh) 一种大电流场效应晶体管

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140611

Termination date: 20151210

EXPY Termination of patent right or utility model