CN203351586U - Packaging structure - Google Patents

Packaging structure Download PDF

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Publication number
CN203351586U
CN203351586U CN2013203768042U CN201320376804U CN203351586U CN 203351586 U CN203351586 U CN 203351586U CN 2013203768042 U CN2013203768042 U CN 2013203768042U CN 201320376804 U CN201320376804 U CN 201320376804U CN 203351586 U CN203351586 U CN 203351586U
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CN
China
Prior art keywords
substrate
lead
bonding
wire
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn - After Issue
Application number
CN2013203768042U
Other languages
Chinese (zh)
Inventor
杨秉谋
孙元鹏
万帮卫
方先华
林政�
方彬彬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Zhenhua Microelectronics Co Ltd
Original Assignee
Shenzhen Zhenhua Microelectronics Co Ltd
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Filing date
Publication date
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Priority to CN2013203768042U priority Critical patent/CN203351586U/en
Application granted granted Critical
Publication of CN203351586U publication Critical patent/CN203351586U/en
Anticipated expiration legal-status Critical
Withdrawn - After Issue legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H01L2224/48991—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
    • H01L2224/48992—Reinforcing structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4941—Connecting portions the connecting portions being stacked
    • H01L2224/49429—Wedge and ball bonds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

The utility model discloses a packaging structure. The packaging structure comprises a substrate, a component installed on the substrate, and a lead connected between the substrate and the component. The lead comprises a first end, a second end, and a connecting point located between the first end and the second end. The first end is connected with the component to form a first bonding point, the connecting point is connected with the substrate to form a second bonding point, and the second end is connected with the substrate to form a third bonding point, so that the tail fiber portion of the lead which is located between the connecting point and the second end is fixed on the substrate through the connection of the third bonding point so as to achieve the purpose of reducing the tail fiber to fully control the length of the tail fiber within two times of the diameter of the lead.

Description

Encapsulating structure
Technical field
The utility model relates to a kind of encapsulating structure.
Background technology
Bonding is widely used in the packaging technology of semiconductor chip, thick film circuit because its technique realizes the characteristics such as simple, with low cost.Bonding is with the two ends of tiny metal lead wire components and parts such as connection substrate and semiconductor chip, resistance, electric capacity respectively, makes the circuit electric connection on each components and parts and substrate.During encapsulation, one end of lead-in wire is incorporated on components and parts and forms the first solder joint, then the rising line sending that goes between forms bank, is connected in afterwards on substrate, breaks lead-in wire, carrying out electric spark burns after ball the lead end on substrate and is reinforced bonding and form the second solder joint, block lead-in wire after forming the second solder joint, carry out the connection of next components and parts, yet block lead-in wire, can form tailfiber in the second bond pad locations, the long problems such as short circuit that easily cause of tailfiber, affect the electrical safety of encapsulating structure.
The utility model content
For addressing the above problem, the utility model provides a kind of can effectively avoid the long encapsulating structure of tailfiber and packaging technology thereof.
A kind of encapsulating structure, comprise substrate, be installed on the components and parts on substrate and be connected in substrate and components and parts between lead-in wire, described lead-in wire comprises first end, the second end and the tie point between first end and the second end, described first end is connected with components and parts and forms the first key chalaza, described tie point is connected with substrate and forms the second bonding point, and described the second end is connected with substrate and forms the 3rd bonding point.
Compared to prior art, the tailfiber during encapsulation of the utility model encapsulating structure, the second bonding point place formed carries out pressure welding, and residual tailfiber pressure welding, on substrate, is effectively controlled to the length of tailfiber.
The accompanying drawing explanation
The structural representation that Fig. 1 is the utility model encapsulating structure one embodiment.
the main element symbol description
Components and parts 10
The first key chalaza 20
Substrate 30
Bonding region 32
The second bonding point 40
Lead-in wire 50
First end 52
Tie point 54
The second end 56
The 3rd bonding point 60
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
As shown in Figure 1, the lead-in wire 50 that the utility model encapsulating structure comprises substrate 30, is installed on the components and parts 10 on substrate 30 and connects components and parts 10 and substrate 30.
Described components and parts 10 can be formed with circuit for semiconductor chip as light-emitting diode, resistance, inductance, electric capacity etc. on described substrate 30, for being electrically connected with components and parts 10, thereby realize the electrical connection of components and parts 10 and external circuit.Shown in substrate 30 can be printed circuit board (PCB) (PCB), metal-cored circuit board (MCPCB), ceramic substrate etc., the heat that components and parts 10 can be produced is derived, and avoids components and parts 10 overheated.
Components and parts 10 are connected with the circuit on substrate 30 in the mode of Bonding, that is to say, components and parts 10 50 are connected with substrate 30 by going between.Described Bonding can be thermocompression bonding, supersonic bonding or hot pressing supersonic bonding etc.Described lead-in wire 50 is tiny metal wire, as gold thread etc., comprises first end 52, the second end 56 and the tie point 54 between first end 52 and the second end 56, and described tie point 54 is close to the second end 56 relatively.Described first end 52 is connected with components and parts 10, described tie point 54 is connected with the circuit on substrate 30, described the second end 56 is connected on substrate 30, but do not play the electrical property effect in the circuit on substrate 30, the reinforcing bonding point 40 of lead-in wire 50 and the part of the second end 56 are tailfiber, by the end by tailfiber, be connected on substrate 30, thereby effectively control the length of lead-in wire 50 tailfibers, avoid causing short circuit, make it meet the requirement of 3.1.5.8.g in GJB548B-2005 " microelectronic component Test Methods And Procedures " method 2017.1, must not make " tailfiber of bonding wire 50 surpasses 2 times of lead-in wire 50 diameters in the length of bonding region 32 ".
During the encapsulation of the utility model encapsulating structure, at first 50 the first end 52 of going between is bonded on components and parts 10 and forms first key chalaza 20, then 50 risings that go between form bank, 50 the tie point 54 of going between afterwards is bonded on substrate 30, break lead-in wire, after carrying out electric spark burning ball, reinforced bonding and formed the second bonding 40 points on tie point 54, so components and parts 10 and the circuit on substrate 30 are electrically connected.On described substrate 30, can form bonding region 32 in the position corresponding to the circuit junction, be convenient to and lead-in wire 50 be connected.After 40 of formation the second bondings, block lead-in wire 50, to carry out the bonding operation of next components and parts 10,50 points that are truncated that go between are the second end 56 of lead-in wire 50.
After forming 40 of the second bondings, the lead-in wire 50 be truncated, locate to form tailfiber 40 of the second bondings, for the length of avoiding tailfiber long, tailfiber is pulled out and carried out pressure welding, it being applied to certain ultrasonic and pressure makes its surface raise at solid-state lower direct close contact temperature, ultrasonic by regulating, temperature, pressure and time, make to go between 50 tailfiber and the contact-making surface of substrate 30 are fully spread and are realized combination between atom, and tailfiber is fixed on substrate 30, the end of tailfiber, 50 the second end 56 of going between is connected on substrate 30 and forms the 3rd bonding point 60.Usually, be by the tailfiber pressure welding in the bonding region 32 of substrate 30, the distance of the second 40 of bondings and the 3rd bonding point 60 is about 0.05～1mm, 50 parts between 40 of the second bondings and the 3rd bonding point 60 that go between, the camber of tailfiber is 0.05～1mm.
The utility model is after 40 of the second bondings complete bonding, tailfiber is pulled out and carried out pressure welding, the end of tailfiber is fixed in the bonding region 32 of substrate 30, thereby guarantee that the encapsulating structure after encapsulation is unlikely to make tailfiber long, make it meet 3.1.5.8.g in GJB548B-2005 " microelectronic component Test Methods And Procedures " method 2017.1 and require must not receive " tailfiber of bonding wire 50 surpasses 2 times of lead-in wire 50 diameters in the length of bonding region 32 ", technique is simple, easy to make, and formed encapsulating structure is safe and reliable.
Above content is in conjunction with a kind of explanation of specifically by routine execution mode, the utility model being done, can not assert that concrete enforcement of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field; without departing from the concept of the premise utility; can also make some simple deduction or replace, all should be considered as belonging to the utility model scope of patent protection definite by submitted to claims.

Claims (4)

1. an encapsulating structure, comprise substrate, be installed on the components and parts on substrate and be connected in substrate and components and parts between lead-in wire, it is characterized in that: described lead-in wire comprises first end, the second end and the tie point between first end and the second end, described first end is connected with components and parts and forms the first key chalaza, described tie point is connected with substrate and forms the second bonding point, and described the second end is connected with substrate and forms the 3rd bonding point.
2. encapsulating structure according to claim 1 is characterized in that: the distance of described the second bonding point and the 3rd bonding point is 0.05～1mm.
3. encapsulating structure according to claim 1, it is characterized in that: the camber of the part of described lead-in wire between the second bonding point and the 3rd bonding point is 0.05～1mm.
4. encapsulating structure according to claim 1, it is characterized in that: be formed with circuit on described substrate, the second bonding point of described lead-in wire is connected with the circuit of substrate, and the 3rd bonding point does not play the electrical property effect in the circuit of substrate.
CN2013203768042U 2013-06-21 2013-06-21 Packaging structure Withdrawn - After Issue CN203351586U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2013203768042U CN203351586U (en) 2013-06-21 2013-06-21 Packaging structure

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Application Number Priority Date Filing Date Title
CN2013203768042U CN203351586U (en) 2013-06-21 2013-06-21 Packaging structure

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CN2013203768042U Withdrawn - After Issue CN203351586U (en) 2013-06-21 2013-06-21 Packaging structure

Country Status (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311142A (en) * 2013-06-21 2013-09-18 深圳市振华微电子有限公司 Packaging structure and packaging technology thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103311142A (en) * 2013-06-21 2013-09-18 深圳市振华微电子有限公司 Packaging structure and packaging technology thereof
CN103311142B (en) * 2013-06-21 2016-08-17 深圳市振华微电子有限公司 Encapsulating structure and packaging technology thereof

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C14 Grant of patent or utility model
GR01 Patent grant
AV01 Patent right actively abandoned

Granted publication date: 20131218

Effective date of abandoning: 20160817

AV01 Patent right actively abandoned

Granted publication date: 20131218

Effective date of abandoning: 20160817

C25 Abandonment of patent right or utility model to avoid double patenting