CN102856281A - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
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- CN102856281A CN102856281A CN2012100390338A CN201210039033A CN102856281A CN 102856281 A CN102856281 A CN 102856281A CN 2012100390338 A CN2012100390338 A CN 2012100390338A CN 201210039033 A CN201210039033 A CN 201210039033A CN 102856281 A CN102856281 A CN 102856281A
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
- H01L2224/48991—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids being formed on the semiconductor or solid-state body to be connected
- H01L2224/48992—Reinforcing structures
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- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
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- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8512—Aligning
- H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
- H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
- H01L2224/8518—Translational movements
- H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
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Abstract
The invention provides a semiconductor package and a manufacturing method thereof. The semiconductor package comprises a substrate, a chip and a bonding lead, wherein the chip is arranged on the substrate and consists of a welding pad, and the welding pad is positioned in the upper surface of the chip; the bonding lead is combined between the welding pad of the chip and the substrate so as to electrically connect the chip with the substrate, the loop height H of the bonding lead meets the formula: d'+h=H<d+h, wherein the d' represents the diameter of the part of the bonding lead, positioned on the chip, h represents the distance between the lower surface of the bonding lead and the surface of the welding pad, and d represents the original diameter of the bonding lead. According to the invention, the lower loop height can be realized, thus facilitating the height integration and miniaturization of the semiconductor package.
Description
Technical field
The invention belongs to the semiconductor packages field, specifically, relate to a kind of semiconductor package part and manufacture method thereof with low bank height.
Background technology
In semiconductor package process, for the pad on the chip is electrically connected with substrate (or lead frame), usually adopt lead key closing process to realize the interconnection of the two.Along with high density, miniaturization and the lightening trend of semiconductor package part, require the bank height of Bonding more and more lower.
Wire bonding method comprises wedge bonding and two kinds of technology of ball-shaped welded.Owing to comparing with the wedge bonding technology, the ball-shaped welded technical operation is more flexible and can realize that better precision controls, thus now widely used be the ball-shaped welded technology.In ball-shaped welded technique, chopper (being generally capillary chopper (capillary)) moves to chip bonding pad, that is, and and the position of the first means of spot welds.The first means of spot welds is by heat and the ultrasonic energy realization Metal Ball in a circle of surface soldered of chip bonding pad.Then, chopper is elevated to apical position and the mobile bank form that needs that forms of bank, to carry out the second point welding.The second point welding comprises the stitch bonding and draws buttock line.Draw buttock line to think that the formation of next bonding Metal Ball prepares after the second point welding.Then, chopper is elevated to suitable height with control buttock line length, at this moment tail end fracture, then chopper rises to the height that forms ball.By aforesaid operations, the neck place of solder bump forms bank on chip.
Fig. 1 shows the schematic diagram according to the bank of the employing Bonding formation of prior art.According to aforesaid method, by chip 10 ' on pad 11 ' locate adopt chopper that first of Bonding done once to press, so that bonding wire 13 ' pad 11 ' formation solder bump 12 ', as shown in Figure 1, therefore, chip 10 ' utilize pad 11 ' by bonding wire 13 ' be electrically connected with substrate or lead frame (not shown).In the prior art, carry out Bonding after, bonding wire 13 ' usually not with protection chip 10 ' protective layer 16 ' contact but separate certain distance.The height H that adopts the bank that the Bonding method of prior art obtains for from pad 11 ' upper surface to bonding wire 13 ' the distance away from the upper surface of chip; its be at least protective layer 16 ' height h and bonding wire 13 ' the diameter d sum; that is, H 〉=h+d.
Fig. 2 shows the schematic diagram according to another example of the bank of the employing Bonding formation of prior art.In Fig. 2, soldering appliance (chopper) carries out pressing for twice to first of Bonding, thereby chip 10 " by pad 11 " is electrically connected via the bonding wire 13 " with lead frame 14 " of pressing for twice, therefore, bonding wire 13 " at lead frame 14 " " is electrically connected with lead frame 14 with the contacted position 15 of bonding wire " with chip 10 ".Specifically, in this example of prior art, at para-linkage lead-in wire 13 " after carrying out pressing for twice; bonding wire 13 " with protective layer 16 " separates certain distance; wherein, when the para-linkage lead-in wire carried out pressing the first time, bonding wire 13 " at pad 11 " formed solder bump 12 ".Therefore, adopt the height H of the bank that the Bonding method of prior art obtains to be at least protective layer 16 " height h and bonding wire 13 ' the diameter d sum, that is, and H 〉=h+d.
Can be found out by Fig. 1 and Fig. 2, carry out Bonding by prior art, the height H of the bank that obtains is at least the diameter d of bonding wire and the height sum of protective layer.Therefore, in the prior art, no matter adopt once and press (Fig. 1) or twice and press (Fig. 2) and carry out Bonding, achieved minimum bank height all is restricted, thereby has influence on the miniaturization of semiconductor package part.
Summary of the invention
In order to solve the problem that the lower bank height of realization is restricted in the wire bonding method of prior art, the invention provides a kind of semiconductor package part and manufacture method thereof that can realize low striking height.
An aspect of of the present present invention provides a kind of semiconductor package part with low bank height, and described semiconductor package part comprises: substrate; Chip is arranged on the substrate, and chip comprises pad, and pad is arranged in the upper surface of chip; Bonding wire, be combined between the pad and substrate of chip, so that chip is electrically connected to substrate, wherein, the bank height H of bonding wire satisfies formula d '+h=H＜d+h, wherein, and the diameter that is positioned at the part on the chip of d ' expression bonding wire, h represents the lower surface of bonding wire to the distance on the surface of pad, and d represents the green diameter of bonding wire.
According to an aspect of the present invention, can make the bank height of bonding wire satisfy described formula by repeatedly pressing bonding wire.
According to an aspect of the present invention, the compression number of bonding wire can be 3～1000 times.
According to an aspect of the present invention, bonding wire can comprise the first bonding end of contacting with pad on the chip and extend and be positioned at first on the chip from the first bonding end.
According to an aspect of the present invention, the first of bonding wire can not contact with chip.
According to an aspect of the present invention, the first of bonding wire can contact with chip.
According to an aspect of the present invention; described semiconductor package part can also comprise protective layer; avoid the impact of outside moisture or air with the protection chip, wherein, described protective layer is arranged on the upper surface of chip and is arranged on the first below of bonding wire round pad.
According to an aspect of the present invention, the first of bonding wire can not contact with protective layer.
According to an aspect of the present invention, the first of bonding wire can contact with protective layer.
Another aspect of the present invention provides a kind of method of making semiconductor package part, and described method comprises the steps: A, prepares to be equipped with the substrate of chip, wherein, is provided with pad in the upper surface of chip; B, by wire bonding method bonding wire is attached to substrate from pad, so that chip is electrically connected to substrate, wherein, press bonding wire downwards, so that the bank height H of bonding wire satisfies formula d '+h=H＜d+h, wherein, the diameter that is positioned at the part on the chip of d ' expression bonding wire, h represents the lower surface of bonding wire to the distance on the surface of pad, and d represents the green diameter of bonding wire.
According to a further aspect in the invention, in step B, by wire bonding method with bonding wire after pad is attached to substrate, can be above bonding wire apply downward pressure by dull and stereotyped para-linkage lead-in wire and press bonding wire.
According to a further aspect in the invention, can come operate tablet by tube core connection device or material testing system equipment, so that dull and stereotyped para-linkage lead-in wire applies downward pressure.
According to a further aspect in the invention, in step B, can be after bonding wire be attached to pad, chopper priority along continuous straight runs and vertical direction are moved repeatedly press bonding wire, wherein, in the process that vertically moves down after chopper strides across pad, chopper is pressed bonding wire towards chip.
According to a further aspect in the invention, the number of times that is pressed of bonding wire can be 3～1000 times.
According to a further aspect in the invention, bonding wire can comprise the first bonding end of contacting with pad on the chip and extend and be positioned at first on the chip from the first bonding end.
According to a further aspect in the invention, the first of bonding wire can not contact with chip.
According to a further aspect in the invention, the first of bonding wire can contact with chip.
According to a further aspect in the invention, described method can also be included on the chip and round pad protective layer is set, and wherein, protective layer is positioned at the below of the first of bonding wire.
According to a further aspect in the invention, the first of bonding wire can not contact with protective layer.
According to a further aspect in the invention, the first of bonding wire can contact with protective layer.
According to the present invention, can realize lower bank height, thereby be beneficial to the integrated and miniaturization of the height of semiconductor package part.
Description of drawings
Fig. 1 shows the schematic diagram according to the bank of the employing Bonding formation of prior art.
Fig. 2 shows the schematic diagram according to another example of the bank of the employing Bonding formation of prior art.
Fig. 3 shows the structural representation of the semiconductor package part that has according to an embodiment of the invention low bank height.
Fig. 4 A to Fig. 4 I shows the according to an embodiment of the invention cutaway view of each step of wire bonding method.
Fig. 5 shows the structural representation of the semiconductor package part that produces by the method shown in Fig. 4 A to Fig. 4 I.
Fig. 6 A to Fig. 6 C shows the according to another embodiment of the present invention cutaway view of each step of wire bonding method.
Fig. 7 shows the structural representation according to the semiconductor package part of the low bank height of having of further embodiment of this invention.
Embodiment
Hereinafter, come with reference to the accompanying drawings to describe more fully the present invention, shown in the drawings of exemplary embodiment of the present invention.As the skilled person will recognize, in situation about all not breaking away from for the spirit or scope of principle of the present invention, can revise in a variety of ways the embodiment of description.
Recognize, describe in order to understand better and to be convenient to, size and the thickness of the composition member shown in the accompanying drawing provide arbitrarily, and the present invention is not subjected to the restriction of illustrated size and thickness.
In the accompanying drawings, for clarity, exaggerated the thickness in layer, zone etc.Identical label represents identical element in whole specification.Should be appreciated that, when the element such as layer, zone or substrate was known as on another element, can directly on described another element, perhaps also can there be intermediary element in this element.Selectively, when element is known as directly on another element, there is not intermediary element.
Describe the semiconductor package part that has low bank height according to of the present invention in detail below in conjunction with accompanying drawing.
Fig. 3 shows the structural representation that has the semiconductor package part of low bank height according to of the present invention.
With reference to Fig. 3, semiconductor package part comprises substrate 100 and is arranged on chip 10 on the substrate 100, and chip 10 comprises the pad 11 of the upper surface that is arranged in chip 10 and is arranged on protective layer 16 on the upper surface of chip 10 round pad 11.Semiconductor package part 100 according to the present invention also comprises the pad 11 that is combined in chip 10 and the bonding wire 13 between the substrate 100, so that chip 10 is electrically connected to substrate 100." similar, solder bump 12 para-linkage lead-in wire when carrying out Bonding carries out that press first time and in pad 11 formation, belongs to the part of bonding wire 13 to solder bump 12 in the semiconductor package part of prior art illustrated in figures 1 and 2 ' with 12.According to the present invention, substrate 100 can be printed circuit board (PCB) (PCB) or lead frame.
Different from the semiconductor package part (as depicted in figs. 1 and 2) of prior art is that the height of the bank that forms according to this embodiment of the invention is less than the height sum of green diameter and the protective layer 16 of bonding wire 13.In the semiconductor package part according to this embodiment of the invention, bonding wire 13 contacts with protective layer 16, and makes protective layer 16 protruding entering in the bonding wire 13 through repeatedly pressing bonding wire 13 in the process of carrying out Bonding, as shown in Figure 3.Specifically, bonding wire 13 contacts with protective layer 16, and the top of protective layer 16 protrudes in the bonding wire 13 so that protective layer 16 protrude into being partly embedded in the bonding wire 13 in the bonding wire 13.To be explained in more detail this hereinafter.Yet, the invention is not restricted to this.For example; although not shown, bonding wire 13 can not contact with protective layer 16, in this case; the bank height H of bonding wire 13 still satisfies H less than the relation of the height sum of the green diameter of bonding wire and pad, thereby has realized low bank height.To this, those skilled in the art under instruction of the present invention, can understand bonding wire not with the contacted situation of protective layer.
Therefore, according to the height of the bank of semiconductor package part of the present invention less than the height (as depicted in figs. 1 and 2) according to the bank of the semiconductor package part of prior art, thereby be beneficial to the microminiaturization that realizes semiconductor package part.Here, the height of bank refer to from the surface of pad bonding wire away from the distance the surface of chip.
According to this embodiment of the invention, protective layer 16 is arranged on the upper surface of chip 10 round pad 11, is used for protecting chip 10 to avoid the impact of outside moisture or air.According to one embodiment of present invention, protective layer 16 can be formed by light-sensitive polyimide (PSPI).
With reference to Fig. 3, the second bonding end that bonding wire 13 comprises the first bonding end of contacting with pad 11 on the chip 10 (or be called " bonding point "), extends and be positioned at first on the chip 11, extend beyond chip 10 and the second portion above substrate 100 and extend and contact with the pad of substrate 100 from second portion from first from the first bonding end, wherein, the diameter of the first of bonding wire is less than the diameter of the second portion of bonding wire.
In Fig. 3, be provided with protective layer 16 at chip 10, and the first of bonding wire 13 contacts with protective layer 16.Yet, the invention is not restricted to this.In the situation that protective layer 16 is not set, the first of bonding wire 13 can contact with chip 10 or not contact with chip 10.
According to one embodiment of present invention, bonding wire 13 can be attached to substrate 100 being pressed more than twice, to contact with protective layer 16.Preferably, the number of times that bonding wire 13 is pressed can be 3～1000 times, so that the top of protective layer 16 is embedded in the bonding wire 13.
The below will describe the manufacture method that has the semiconductor package part of low bank height according to of the present invention.
According to the present invention, the manufacture method with semiconductor package part of low bank height may further comprise the steps:
(1) preparation is equipped with the substrate of chip, wherein, is provided with pad in the upper surface of chip;
(2) by wire bonding method bonding wire is combined between pad and the substrate, so that chip is electrically connected to substrate, wherein, presses bonding wire downwards, so that the bank height H of bonding wire satisfies following formula a:
d′+h＝H＜d+h，
In the formula, the diameter that is positioned at the part on the chip of d ' expression bonding wire, h represent the lower surface of bonding wire to the distance of bond pad surface, and d represents the green diameter of bonding wire.
According to the present invention, in the superincumbent step (2), can form protective layer by having light-sensitive polyimide (PSPI).Here, can adopt method well known in the art is that chip arranges pad and protective layer.Therefore, no longer it is given unnecessary details here.
According to the present invention, in the superincumbent step (2), can adopt diverse ways so that the bank height H of bonding wire satisfies top formula a, the below will be described in detail it.
The below describes according to an embodiment of the invention wire bonding method in detail with reference to Fig. 4 A to Fig. 4 I.Fig. 4 A to Fig. 4 I shows the according to an embodiment of the invention cutaway view of each step of wire bonding method.
According to this embodiment of the invention, chip on being positioned at substrate arranges after the pad, utilize and be used for providing the chopper of bonding wire at first bonding wire to be attached to pad, chopper priority along continuous straight runs and vertical direction are moved repeatedly press bonding wire, wherein, in the process that vertically moves down after chopper strides across pad, chopper is pressed bonding wire towards chip, so that the bank height of bonding wire reduces.
Specifically, at first, be ready to be equipped with on it substrate of chip, wherein, in the upper surface of chip, be provided with pad.According to one embodiment of present invention, can be when chip arrange pad, at the upper surface of chip protective layer round solder pad arrangements is set.According to another embodiment of the present invention, can only pad be set and protective layer is not set at chip.For convenience of description, the below will be described for the situation that has formed pad and protective layer at chip.
Then, with reference to Fig. 4 A, chopper 1 (being preferably the capillary chopper) is aimed at the pad 11 in the chip (not shown), the cusp of chopper 1 is contacted with pad 11, and the end of bonding wire 13 forms solder bumps 12 at pad 11, be used for chip 10 on pad 11 combinations.Then, lift chopper 1, make its vertically (that is, the y direction of principal axis) distance y 1 that moves up (that is, making the cusp of chopper 1 move to respectively A1, B1 2 points), shown in Fig. 4 B; Then, chopper 1 along continuous straight runs (that is, along the x axle among Fig. 4 B) is moved right apart from x1 (that is, making the cusp of chopper 1 move to respectively A2, B2 2 points), so that bonding wire 13 is crooked under the effect of chopper 1, shown in Fig. 4 C to the right; Then, make chopper 1 vertically move down distance y 2 (that is, making the cusp of chopper 1 move to respectively A3, B3 2 points), thereby bonding wire 13 is pressed downwards under the effect of chopper 1, shown in Fig. 4 D; Then, shown in Fig. 4 E, again lift chopper 1 (that is, making the cusp of chopper 1 move to respectively A4, B4 2 points), thereby form first bank of bonding wire 13 at chip 10.The length of the bank that can determine bonding wire 13 according to size and the actual needs of chip here, and height; That is to say, moving horizontally apart from x1 and vertical displacement y1, y2 of chopper can be determined according to actual needs.
Next, repeat the step shown in Fig. 4 B to Fig. 4 E, make bonding wire 13 again form bank.Specifically, shown in Fig. 4 F, make chopper 1 along continuous straight runs (that is, x direction of principal axis) again move right (that is, making the cusp of chopper 1 move to respectively A5, B5 2 points), then with reference to Fig. 4 G, make chopper vertically (that is, y direction of principal axis) move down (that is, making the cusp of chopper 1 move to respectively A6, B6 2 points) and press bonding wire 13, press thereby para-linkage lead-in wire 13 carries out secondary, form bank P1-A3-P2-A6.Here, carry out secondary when pressing, according to actual conditions, chopper 1 move horizontally distance and vertically displacement can be according to actual conditions and identical or different with the distance of Fig. 4 B to Fig. 4 D.
Then, again or repeatedly repeat the step shown in Fig. 4 B to Fig. 4 E, make bonding wire again or repeatedly form bank (shown in Fig. 4 H), remove at last chopper to descend the Bonding of a bit, obtain the structure shown in Fig. 4 I.Specifically, again or repeatedly repeat chopper to lift-move horizontally-action of pressing, bonding wire 13 is contacted with protective layer 16 with the form of pressing and chip 10 is electrically connected to substrate (or lead frame) 10.Chopper 1 move horizontally distance and vertically displacement can be identical or different with the distance of Fig. 4 B to Fig. 4 D.According to the present invention, can use chopper to carry out repeatedly (being no less than twice) along first direction to second point of Bonding and press.According to a preferred embodiment of the invention, the number of times of repeatedly pressing can be 3 times to 1000 times.If press twice, then can not get the effect of expecting; If the number of times of pressing too many (more than 1000 times) then can increase manufacturing cost.
Fig. 5 shows the structural representation of the semiconductor package part that produces by the method shown in Fig. 4 A to Fig. 4 I.
With reference to Fig. 5, the second bonding end that bonding wire 13 comprises the first bonding end of contacting with pad 11 on the chip 10, extends and be positioned at first on the chip 11, extend beyond chip 10 and the second portion above substrate 100 and extend and contact with the pad of substrate 100 from second portion from first from the first bonding end, wherein, the diameter d of the first of bonding wire ' less than the diameter of the second portion of bonding wire.
Therefore, the bank height H that obtains by wire bonding method of the present invention is the height h sum of diameter d ' (d ' less than the green diameter d of bonding wire 13) with the protective layer 16 of the bonding wire 13 after pressing.Carry out the bank that Bonding obtains according to prior art and compare with illustrated in figures 1 and 2, the bank height that the method according to this invention obtains is obviously less, therefore is easy to realize the microminiaturization of semiconductor package part.
Therefore, according to this embodiment of the invention, begin repeatedly to press to Bonding second point direction from first of solder bump Bonding on the chip, can realize the Bonding of low bank height.
Fig. 6 A to Fig. 6 C shows the according to another embodiment of the present invention cutaway view of each step of wire bonding method.
According to another embodiment of the present invention, pad 11 is set and is arranged on protective layer 16 on the upper surface of chip 10 round pad 11 being installed in chip 100 on the substrate.Then, can utilize existing wire bonding method on the pad 11 of chip 10, bonding wire 13 to be attached to substrate (or lead frame), as shown in Figure 6A.
Then; utilize dull and stereotyped M to apply downward pressure to bonding wire 13, as shown in Fig. 6 B, so that the part that contacts with protective layer 16 of bonding wire 13 is pressed and is out of shape; thereby the top that makes protective layer 16 protrudes in the bonding wire 13, thereby obtains the structure shown in Fig. 6 C.According to one embodiment of present invention, can connecting by tube core (die attaching) equipment or material testing system (material test system, MTS) equipment makes dull and stereotyped M para-linkage lead-in wire apply downward pressure.Yet, the invention is not restricted to this; Under instruction of the present invention, those skilled in the art can adopt other method that is fit to come the para-linkage lead-in wire to apply downward pressure.
Therefore, for the semiconductor package part that obtains by this embodiment of the invention, its bank height H be the bonding wire 13 after pressing diameter d ' with the height h sum of protective layer 16.Carry out the bank that Bonding obtains according to prior art and compare with illustrated in figures 1 and 2, the bank height that the method according to this invention obtains is obviously less, therefore is easy to realize the microminiaturization of semiconductor package part.
Fig. 7 shows the structural representation according to the semiconductor package part of the low bank height of having of further embodiment of this invention.
Different from the embodiment of front, in the semiconductor package part in Fig. 7, protective layer is not set on the chip, in addition, the semiconductor package part of the semiconductor package part of Fig. 7 and the embodiment of front is basic identical.
With reference to Fig. 7, semiconductor package part comprises substrate 100, be arranged on the substrate 100 and comprise the chip of pad 11 and be combined in the pad 11 of chip and the bonding wire 13 between the substrate 100, wherein, pad 11 is arranged in the upper surface of chip, and bonding wire 13 is electrically connected to substrate 100 with chip.According to the present invention, the bank height H of bonding wire is less than the height sum of green diameter and the pad of bonding wire 13, that is, according to the bank height of bonding wire of the present invention bank height (as depicted in figs. 1 and 2) less than bonding wire of the prior art.
In Fig. 7, bonding wire 13 does not contact with chip.Yet, the invention is not restricted to this, bonding wire 13 can contact with chip.
Can adopt the method shown in the method shown in Fig. 4 A to Fig. 4 I or Fig. 6 A to Fig. 6 C to come the semiconductor package part of shop drawings 7, therefore, this no longer be given unnecessary details.
In addition, although not shown in the accompanying drawings, can finish the Bonding of semiconductor package part and after forming the bonding wire of low bank height, can carry out encapsulating process and come chip is sealed.
Therefore, according to the present invention, by the bonding wire on the compression chip its cross section is broadened, so that the height of bank diminishes, thereby be conducive to realize the microminiaturization of semiconductor package part.
Although described the present invention in conjunction with accompanying drawing of the present invention, it should be understood that and to make variants and modifications to the present invention in the situation that do not break away from the spirit and scope of the present invention.
Claims (20)
1. semiconductor package part is characterized in that described semiconductor package part comprises:
Substrate;
Chip is arranged on the substrate, and chip comprises pad, and pad is arranged in the upper surface of chip; And
Bonding wire is combined between the pad and substrate of chip, so that chip is electrically connected to substrate,
Wherein, the bank height H of bonding wire satisfies formula
d′+h＝H＜d+h，
Wherein, the diameter that is positioned at the part on the chip of d ' expression bonding wire, h represent the lower surface of bonding wire to the distance on the surface of pad, and d represents the green diameter of bonding wire.
2. semiconductor package part according to claim 1 is characterized in that making the bank height of bonding wire satisfy described formula by repeatedly pressing bonding wire.
3. semiconductor package part according to claim 2, the compression number that it is characterized in that bonding wire is 3～1000 times.
4. semiconductor package part according to claim 1 is characterized in that bonding wire comprises the first bonding end of contacting with pad on the chip and extends and be positioned at first on the chip from the first bonding end.
5. semiconductor package part according to claim 4 is characterized in that the first of bonding wire does not contact with chip.
6. semiconductor package part according to claim 4 is characterized in that the first of bonding wire contacts with chip.
7. semiconductor package part according to claim 4; it is characterized in that described semiconductor package part also comprises protective layer; avoid the impact of outside moisture or air with the protection chip; wherein, described protective layer is arranged on the upper surface of chip and is arranged on the first below of bonding wire round pad.
8. semiconductor package part according to claim 7 is characterized in that the first of bonding wire does not contact with protective layer.
9. semiconductor package part according to claim 7 is characterized in that the first of bonding wire contacts with protective layer.
10. a method of making semiconductor package part is characterized in that described method comprises the steps:
A, preparation are equipped with the substrate of chip, wherein, are provided with pad in the upper surface of chip;
B, by wire bonding method bonding wire is attached to substrate from pad, so that chip is electrically connected to substrate,
Wherein, press bonding wire downwards, so that the bank height H of bonding wire satisfies formula
d′+h＝H＜d+h，
Wherein, the diameter that is positioned at the part on the chip of d ' expression bonding wire, h represent the lower surface of bonding wire to the distance on the surface of pad, and d represents the green diameter of bonding wire.
11. method according to claim 10, it is characterized in that in step B, by wire bonding method with bonding wire after pad is attached to substrate, above bonding wire, apply downward pressure by dull and stereotyped para-linkage lead-in wire and press bonding wire.
12. method according to claim 11 is characterized in that coming operate tablet by tube core connection device or material testing system equipment, so that dull and stereotyped para-linkage lead-in wire applies downward pressure.
13. method according to claim 10, it is characterized in that in step B, after bonding wire is attached to pad, chopper priority along continuous straight runs and vertical direction are moved repeatedly press bonding wire, wherein, in the process that vertically moves down after chopper strides across pad, chopper is pressed bonding wire towards chip.
14. method according to claim 13 is characterized in that the number of times that bonding wire is pressed is 3～1000 times.
15. the described method of each claim in 14 according to claim 10 is characterized in that bonding wire comprises the first bonding end of contacting with pad on the chip and extends and be positioned at first on the chip from the first bonding end.
16. method according to claim 15 is characterized in that the first of bonding wire does not contact with chip.
17. method according to claim 15 is characterized in that the first of bonding wire contacts with chip.
18. method according to claim 15 is characterized in that described method also is included on the chip round pad protective layer to be set that wherein, protective layer is positioned at the below of the first of bonding wire.
19. method according to claim 18 is characterized in that the first of bonding wire does not contact with protective layer.
20. method according to claim 18 is characterized in that the first of bonding wire contacts with protective layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2012100390338A CN102856281A (en) | 2012-02-17 | 2012-02-17 | Semiconductor package and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100390338A CN102856281A (en) | 2012-02-17 | 2012-02-17 | Semiconductor package and manufacturing method thereof |
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| CN102856281A true CN102856281A (en) | 2013-01-02 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107301989A (en) * | 2017-06-06 | 2017-10-27 | 深圳国民飞骧科技有限公司 | A kind of method for determining bonding wire chip surface pad spacing |
| CN116329830A (en) * | 2023-05-29 | 2023-06-27 | 宁波尚进自动化科技有限公司 | Welding method of chip pins |
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|---|---|---|---|---|
| CN1501485A (en) * | 1998-11-19 | 2004-06-02 | ���µ�����ҵ��ʽ���� | Electronic device |
| CN101803015A (en) * | 2007-07-17 | 2010-08-11 | 赛特克斯半导体公司 | Semiconductor chip package with bent outer leads |
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- 2012-02-17 CN CN2012100390338A patent/CN102856281A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1501485A (en) * | 1998-11-19 | 2004-06-02 | ���µ�����ҵ��ʽ���� | Electronic device |
| CN101803015A (en) * | 2007-07-17 | 2010-08-11 | 赛特克斯半导体公司 | Semiconductor chip package with bent outer leads |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107301989A (en) * | 2017-06-06 | 2017-10-27 | 深圳国民飞骧科技有限公司 | A kind of method for determining bonding wire chip surface pad spacing |
| WO2018223569A1 (en) * | 2017-06-06 | 2018-12-13 | 深圳飞骧科技有限公司 | Method for determining bonding pad spacing on the surface of bonding wire chip |
| CN116329830A (en) * | 2023-05-29 | 2023-06-27 | 宁波尚进自动化科技有限公司 | Welding method of chip pins |
| CN116329830B (en) * | 2023-05-29 | 2023-08-29 | 宁波尚进自动化科技有限公司 | Welding method of chip pins |
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Application publication date: 20130102 |