CN208848858U - A kind of semiconductor vertical wire bond structure - Google Patents
A kind of semiconductor vertical wire bond structure Download PDFInfo
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- CN208848858U CN208848858U CN201821264947.3U CN201821264947U CN208848858U CN 208848858 U CN208848858 U CN 208848858U CN 201821264947 U CN201821264947 U CN 201821264947U CN 208848858 U CN208848858 U CN 208848858U
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- weld pad
- routing
- solder joint
- semiconductor
- vertical
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/7825—Means for applying energy, e.g. heating means
- H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/78301—Capillary
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Abstract
The utility model provides a kind of semiconductor vertical wire bond structure, the semiconductor vertical wire bond structure includes semiconductor chip, routing weld pad, vertical conduction column and virtual weld pad, wherein, the semiconductor chip surface has the first solder joint and the second solder joint of discrete setting, the routing weld pad is located at first solder joint, it is connected with the semiconductor chip built-in function device, the vertical conduction column is connected to routing weld pad surface, the virtual weld pad is located at second solder joint, for providing all line platforms for the formation of the vertical conduction column.The utility model is by increasing virtual weld pad to the second solder joint, it eliminates in vertical routing as the damage caused by front layer of the second solder joint, and then improves the flatness of vertical routing technique front layer base and generate the risk of removing, the electric signal transmission performance of each conductive layer in chip is improved, and helps to improve the efficiency and accuracy of vertical routing technique.
Description
Technical field
The utility model belongs to field of semiconductor package, is related to a kind of semiconductor vertical wire bond structure.
Background technique
All calculating and communication system require power transmission subsystem.Power transmission system converts the high voltage of power supply
For many different low-voltages needed for separate devices in system.In being fanned out to encapsulation, all layers are connected with power signals
Conducting wire determine the amplitude of signal transmission loss.
In existing vertical routing technique, routing is carried out at the first solder joint, tangent line is carried out at the second solder joint, due to the
Exclusive weld pad is had no at two solder joints, the thread cutting action of the second solder joint is completed on front layer PI/ metal layer, can cause to damage to front layer
Hurt (damage), and forms multiple pits.Since multiple pits cause surface irregularity, plastic packaging molding (molding) it
Afterwards, large stretch of removing (peeling) is easily formed, chip internal structure and electrical property can be had an impact；Such as damage too deep, meeting shadow
The flatness for ringing front layer causes electric signal to cause signal to be interrupted in this layer transmission.
Therefore, a kind of semiconductor vertical wire bond structure how is provided, to eliminate in vertical routing since the second solder joint is produced
Raw damage improves the flatness of vertical routing technique front layer base and generates the risk of removing, improves each conduction in chip
The electric signal transmission performance of layer and the efficiency and accuracy for improving vertical routing technique, it is urgently to be resolved to become those skilled in the art
An important technological problems.
Utility model content
In view of the foregoing deficiencies of prior art, the purpose of this utility model is to provide a kind of semiconductor vertical routings
Structure, the flatness for influencing front layer base for solving existing vertical routing technique generate removing after causing plastic packaging to form, and
The problem of influencing the electric signal transmission performance of conductive layer.
In order to achieve the above objects and other related objects, the utility model provides a kind of semiconductor vertical wire bond structure, packet
It includes:
Semiconductor chip, surface have the first solder joint and the second solder joint of discrete setting；
Routing weld pad is located at first solder joint, is connected with the semiconductor chip built-in function device；
Vertical conduction column is connected to routing weld pad surface；
Virtual weld pad is located at second solder joint, for providing all line platforms for the formation of the vertical conduction column.
Optionally, the thickness range of the virtual weld pad is 2~5 μm.
Optionally, the top surface area of the virtual weld pad is greater than the base area of the chopper.
Optionally, the top surface area of the virtual weld pad is 1.1~1.5 times of the base area of the chopper.
Optionally, the semiconductor chip surface is equipped with insulating layer, and the virtual weld pad is located at the surface of insulating layer, and
It is not attached to the semiconductor chip built-in function device.
Optionally, the vertical conduction column is used for three-dimension packaging.
Optionally, the quantity of the routing weld pad and the virtual weld pad is multiple, and the virtual weld pad with it is described
Routing weld pad corresponds.
Optionally, the quantity of the routing weld pad and the virtual weld pad is multiple, and at least one is described virtual
Weld pad corresponds to multiple routing weld pads.
Optionally, the shape of the virtual weld pad includes any one in round, rectangular.
As described above, the semiconductor vertical wire bond structure of the utility model, has the advantages that the utility model
Semiconductor vertical wire bond structure increases virtual weld pad to the second solder joint, eliminates in vertical routing and is produced by the second solder joint in front layer
Raw damage, and then improve the flatness of vertical routing technique front layer base and generate the risk of removing, it improves every in chip
The electric signal transmission performance of one conductive layer, and help to improve the efficiency and accuracy of vertical routing technique.
Detailed description of the invention
Fig. 1 is shown as the schematic diagram of the semiconductor vertical wire bond structure of the utility model.
Fig. 2 is shown as the method and process flow chart in embodiment two.
Fig. 3 is shown as the process flow chart of the method and step S2 in embodiment two.
Fig. 4 is shown as the structural schematic diagram of the semiconductor chip of the offer of the method in embodiment two.
A metal wire is provided in the method that Fig. 5 is shown as in embodiment two, the metal wire passes through the schematic diagram of chopper.
The line tail of the metal wire is fused into the schematic diagram of metal ball in the method that Fig. 6 is shown as in embodiment two.
The chopper is dropped at first solder joint in the method that Fig. 7 is shown as in embodiment two, by the metal
Ball bond to routing weld pad surface schematic diagram.
The schematic diagram for rising the chopper after the completion of pressure welding in the method that Fig. 8 is shown as in embodiment two.
Fig. 9 is shown as signal that the metal wire is ironed on the virtual weld pad surface in the method in embodiment two
Figure.
Make the metal wire ironed using the upward pulling force of the chopper in the method that Figure 10 is shown as in embodiment two
Locate the schematic diagram of fracture.
Component label instructions
1 semiconductor chip
2 first solder joints
3 second solder joints
4 routing weld pads
5 virtual weld pads
6 metal wires
7 choppers
8 metal balls
9 vertical conduction columns
S1~S2, S2-1~S2-6 step
Specific embodiment
Illustrate the embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this theory
Content disclosed by bright book understands other advantages and effect of the utility model easily.The utility model can also be by addition
Different specific embodiments are embodied or practiced, and the various details in this specification can also be based on different viewpoints and answer
With carrying out various modifications or alterations under the spirit without departing from the utility model.
Fig. 1 is please referred to Figure 10.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of utility model is only shown with related component in the utility model rather than when according to actual implementation in schema then
Component count, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind
Become, and its assembly layout kenel may also be increasingly complex.
Embodiment one
The utility model provides a kind of semiconductor vertical wire bond structure, referring to Fig. 1, being shown as the semiconductor vertical routing
Structural schematic diagram, the semiconductor vertical wire bond structure include semiconductor chip 1, routing weld pad 4, vertical conduction column 9 and virtual
Weld pad 5, wherein 1 surface of semiconductor chip has the first solder joint and the second solder joint of discrete setting, the routing weld pad 4
At first solder joint, it is connected with the 1 built-in function device of semiconductor chip, the vertical conduction column 9 is connected to institute
4 surface of routing weld pad is stated, the virtual weld pad 5 is located at second solder joint, for mentioning for the formation of the vertical conduction column 9
For all line platforms.
Specifically, the semiconductor chip 1, which refers to, the semiconductor technologies such as is etched on semiconductor sheet material, is routed, system
At the semiconductor devices for being able to achieve certain function.Routing (English name: Wire Bonding) also cry pressure welding, binding, bonding,
Wire bond etc. refers to using wire (gold thread, aluminum steel etc.), using hot pressing or the ultrasonic energy, completes solid-state electricity in microelectronic component
The connection of road intraconnection wiring, i.e. connection between chip and circuit or lead frame.In the utility model, using vertically beating
Wiring technology makes vertical conduction column 9 on the routing weld pad 4, and the vertical conduction column 9 is used for subsequent three-dimensional stacked encapsulation.
That is, connecting the semiconductor chip 1 with other packaging bodies by the conductive column 9, three-dimensional stacked encapsulation knot is formed
Structure.
Specifically, the semiconductor chip 1 can have multiple tie points to need to draw, therefore the quantity of the routing weld pad 4
It can be to be multiple, correspondingly, the quantity of the virtual weld pad 5 is also multiple.Wherein, the routing weld pad 4 and the virtual weld pad 5
Can correspond, that is to say, that can be separately provided by each routing weld pad for needing to make vertical conduction column one it is described virtual
Weld pad 5.In other embodiments, it is also possible at least one described virtual weld pad 5 and corresponds to multiple routing weld pads 4,
That is, a virtual weld pad 5 is shared by two or more routing weld pads 4.The virtual weld pad 5
The distance between described routing weld pad 4 determined by the height of vertical conduction column to be formed, the virtual weld pad 5 with it is described
The distance between routing weld pad 4 needs to be less than the height of vertical conduction column to be formed.
It should be pointed out that " virtual " in the virtual weld pad (English name: Dummy pad) is not necessarily referring to the weld pad not
In the presence of, and refer to the weld pad and be not attached to the 1 built-in function device of semiconductor chip.In fact, the virtual weld pad 5 is tool
There is entity.In the present embodiment, the routing weld pad 4 is all made of conductive metallic material with the virtual weld pad 5, including but unlimited
In the materials such as aluminium (Al), copper (Cu), golden (Au).
Specifically, 1 surface of semiconductor chip is equipped with insulating layer, the virtual weld pad 5 is located at the surface of insulating layer,
And it is not attached to the semiconductor chip built-in function device.The material of the insulating layer includes but is not limited to silica, nitrogen
The materials such as SiClx, polyimides (PI).
Specifically, the shape of the virtual weld pad 5 includes but is not limited to round, rectangular etc..The thickness of the virtual weld pad 5
Range is 2~5 μm.Tangent line can be made up using thickness possessed by the virtual weld pad 5 by the way that the virtual weld pad 5 is arranged
When chopper at the second solder joint caused by be recessed, improve the flatness on 1 surface of semiconductor chip after vertical routing technique, from
And reduce the probability of the large stretch of removing of formation after plastic packaging molding.
Specifically, the top surface area of the virtual weld pad 5 is preferably greater than the base area of chopper, to disperse chopper tangent line
When pressure, reduce tangent line when the second solder joint at sinking degree, eliminate the damage as caused by the second solder joint in vertical routing
Wound improves the flatness of vertical routing technique front layer base, improves the electric signal transmission performance of each conductive layer in chip.
In the present embodiment, the top surface area of the virtual weld pad is preferably the 1.1~1.5 of the base area of the chopper
Times, the area of the virtual weld pad is too small, then it can not disperse pressure when tangent line, and area is excessive, then can introduce parasitic capacitance,
Device inside semiconductor chip is interfered.
The semiconductor vertical wire bond structure of the utility model eliminates vertical routing by increasing virtual weld pad to the second solder joint
In as the damage caused by front layer of the second solder joint, and then improve the flatness of vertical routing technique front layer base and generate stripping
From risk, improve the electric signal transmission performance of each conductive layer in chip.In addition, the presence of the virtual weld pad also helps
In the efficiency and accuracy that improve vertical routing technique.
Embodiment two
A kind of method making semiconductor vertical wire bond structure described in embodiment one is provided in the present embodiment, please refers to figure
2, it is shown as the process flow chart of this method, comprising the following steps:
Step S1 is first carried out: referring to Fig. 3, providing semiconductor chip 1,1 surface of semiconductor chip, which has, to be divided
The first solder joint and the second solder joint set are erected, is equipped with and the 1 built-in function device phase of semiconductor chip at first solder joint
Routing weld pad 4 even is equipped with virtual weld pad 5 at second solder joint.
Specifically, the semiconductor chip 1, which refers to, the semiconductor technologies such as is etched on semiconductor sheet material, is routed, system
At the semiconductor devices for being able to achieve certain function.The semiconductor chip 1 can have multiple tie points to need to draw, therefore described
The quantity of routing weld pad 4 can be multiple.
Specifically, the virtual weld pad can be separately provided by each routing weld pad for needing to make vertical conduction column
5, it can also be shared with a virtual weld pad 5 by two or more routing weld pads 4.The virtual weld pad 5
The distance between described routing weld pad 4 determined by the height of vertical conduction column to be formed, the virtual weld pad 5 with it is described
The distance between routing weld pad 4 needs to be less than the height of vertical conduction column to be formed.
It should be pointed out that " virtual " in the virtual weld pad (English name: Dummy pad) is not necessarily referring to the weld pad not
In the presence of, and refer to the weld pad and be not attached to the 1 built-in function device of semiconductor chip.In fact, the virtual weld pad 5 is tool
There is entity.In the present embodiment, the routing weld pad 4 is all made of conductive metallic material with the virtual weld pad 5, including but unlimited
In the materials such as aluminium (Al), copper (Cu), golden (Au).The shape of the virtual weld pad 5 includes but is not limited to round, rectangular etc..
Specifically, 1 surface of semiconductor chip is equipped with insulating layer, the virtual weld pad 5 is located at the surface of insulating layer,
And it is not attached to the semiconductor chip built-in function device.The material of the insulating layer includes but is not limited to silica, nitrogen
The materials such as SiClx, polyimides (PI).
Then it executes step S2: carrying out routing on the routing weld pad 4, carry out tangent line on the virtual weld pad 5,
Bracing wire is carried out above the routing weld pad 4, so that metal wire 6 is broken at tangent line, obtain connecting with the routing weld pad hangs down
Straight conductive column 9.
As an example, referring to Fig. 4, the step S2 include it is following step by step:
As shown in figure 5, executing step S2-1: providing a metal wire 6, the metal wire 6 passes through chopper 7 and stays in chopper head
One section of safe distance out.
Specifically, soldering tip of the chopper 7 as pressure welding, wherein having a perforation for allowing the metal wire to pass through, institute
It states and is equipped with a wire clamp (not shown) above chopper 7, for controlling the length of metal wire.This is the ordinary skill in the art, herein
It repeats no more.
Specifically, the material of the metal wire 6 includes but is not limited to the materials such as aluminium (Al), copper (Cu), golden (Au).The gold
The diameter for belonging to line 6 is selected according to the diameter of vertical conduction column to be prepared.
As shown in fig. 6, executing step S2-2: the line tail of the metal wire 6 is fused into metal ball 8.
As an example, EFO (Electronic Flame Off, electronic striking) is acted at the line tail of the metal wire 6,
Make one metal ball of line urogenesis.
As shown in fig. 7, executing step S2-3: the chopper 7 being dropped at first solder joint, by the metal ball 8
Pressure welding is to 4 surface of routing weld pad.
As shown in figure 8, executing step S2-4: rising the chopper 7 after the completion of pressure welding.
As shown in figure 9, executing step S2-5: when the chopper 7 rises to routing desired height position, by the chopper
The wire clamp of 7 tops is closed, and the chopper 7 is declined and is moved at second solder joint, by the metal wire 6 in the void
Quasi- weld pad surface is ironed.Wherein, ironed process is known as tangent line.
Specifically, using thickness possessed by the virtual weld pad 5, can be made up due to the presence of the virtual weld pad 5
It is recessed caused by chopper is at the second solder joint when tangent line, improves the smooth of 1 surface of semiconductor chip after vertical routing technique
Degree, to form the probability of large stretch of removing after reducing plastic packaging molding.
Specifically, the chopper 7 by the metal wire while the virtual weld pad surface is ironed, also progress level side
To concussion, such as the direction XY concussion, the metal wire is pressed thinner so that metal wire be easier drawn in laminating position
It is disconnected.
Specifically, the top surface area of the virtual weld pad 5 is preferably greater than the base area of chopper 7, cut with dispersing chopper
Pressure when line is eliminated in vertical routing to reduce sinking degree when tangent line at the second solder joint since the second solder joint is produced
Raw damage improves the flatness of vertical routing technique front layer base, improves the electric signal transmission of each conductive layer in chip
Energy.
In the present embodiment, the top surface area of the virtual weld pad is preferably the 1.1~1.5 of the base area of the chopper
Times, the area of the virtual weld pad is too small, then it can not disperse pressure when tangent line, and area is excessive, then can introduce additional electricity
Hold, the device inside semiconductor chip is interfered.
As shown in Figure 10, it executes step S2-6: the chopper 7 being moved to preset height above first solder joint and is protected
It holds the wire clamp to close, is broken the metal wire in laminating position using the upward pulling force of the chopper.
So far, it is made on the routing weld pad 4 at first solder joint by vertical routing technique and obtains vertical conduction column
9.The vertical conduction column 9 is used for subsequent three-dimensional stacked encapsulation.That is, passing through the conductive column 9 for the semiconductor
Chip 1 is connect with other packaging bodies, forms three-dimensional stacked encapsulating structure.
In conclusion the semiconductor vertical wire bond structure of the utility model increases virtual weld pad to the second solder joint, eliminates and hang down
As the damage caused by front layer of the second solder joint in straight routing, so the flatness of the vertical routing technique front layer base of improvement and
The risk for generating removing, improves the electric signal transmission performance of each conductive layer in chip, and help to improve vertical routing work
The efficiency and accuracy of skill.So the utility model effectively overcomes various shortcoming in the prior art and has high industrial benefit
With value.
The above embodiments are only illustrative of the principle and efficacy of the utility model, and not for limitation, this is practical new
Type.Any person skilled in the art can all carry out above-described embodiment under the spirit and scope without prejudice to the utility model
Modifications and changes.Therefore, such as those of ordinary skill in the art without departing from the revealed essence of the utility model
All equivalent modifications or change completed under mind and technical idea, should be covered by the claim of the utility model.
Claims (9)
1. a kind of semiconductor vertical wire bond structure characterized by comprising
Semiconductor chip, surface have the first solder joint and the second solder joint of discrete setting；
Routing weld pad is located at first solder joint, is connected with the semiconductor chip built-in function device；
Vertical conduction column is connected to routing weld pad surface；
Virtual weld pad is located at second solder joint, for providing all line platforms for the formation of the vertical conduction column.
2. semiconductor vertical wire bond structure according to claim 1, it is characterised in that: the thickness range of the virtual weld pad
It is 2~5 μm.
3. semiconductor vertical wire bond structure according to claim 1, it is characterised in that: the top surface area of the virtual weld pad
The base area of chopper used when greater than tangent line.
4. semiconductor vertical wire bond structure according to claim 1, it is characterised in that: the top surface area of the virtual weld pad
1.1~1.5 times of the base area of chopper used when for tangent line.
5. semiconductor vertical wire bond structure according to claim 1, it is characterised in that: the semiconductor chip surface is equipped with
Insulating layer, the virtual weld pad is located at the surface of insulating layer, and is not attached to the semiconductor chip built-in function device.
6. semiconductor vertical wire bond structure according to claim 1, it is characterised in that: the vertical conduction column is for three-dimensional
Encapsulation.
7. semiconductor vertical wire bond structure according to claim 1, it is characterised in that: the routing weld pad and described virtual
The quantity of weld pad is multiple, and the virtual weld pad and the routing weld pad correspond.
8. semiconductor vertical wire bond structure according to claim 1, it is characterised in that: the routing weld pad and described virtual
The quantity of weld pad is multiple, and at least one described virtual weld pad corresponds to multiple routing weld pads.
9. semiconductor vertical wire bond structure according to claim 1, it is characterised in that: the shape of the virtual weld pad includes
Any one in round, rectangular.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821264947.3U CN208848858U (en) | 2018-08-06 | 2018-08-06 | A kind of semiconductor vertical wire bond structure |
| US16/369,891 US10854476B2 (en) | 2018-08-06 | 2019-03-29 | Semiconductor vertical wire bonding structure and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821264947.3U CN208848858U (en) | 2018-08-06 | 2018-08-06 | A kind of semiconductor vertical wire bond structure |
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| Publication Number | Publication Date |
|---|---|
| CN208848858U true CN208848858U (en) | 2019-05-10 |
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ID=66355265
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| Application Number | Title | Priority Date | Filing Date |
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| CN201821264947.3U Active CN208848858U (en) | 2018-08-06 | 2018-08-06 | A kind of semiconductor vertical wire bond structure |
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| Country | Link |
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| CN (1) | CN208848858U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112652549A (en) * | 2019-10-10 | 2021-04-13 | 中芯长电半导体（江阴）有限公司 | Vertical routing equipment and routing method |
| CN116754627A (en) * | 2023-08-21 | 2023-09-15 | 苏州矽联传感科技有限公司 | Bioelectrode manufacturing method, bioelectrode and biosensing device |
-
2018
- 2018-08-06 CN CN201821264947.3U patent/CN208848858U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112652549A (en) * | 2019-10-10 | 2021-04-13 | 中芯长电半导体（江阴）有限公司 | Vertical routing equipment and routing method |
| CN116754627A (en) * | 2023-08-21 | 2023-09-15 | 苏州矽联传感科技有限公司 | Bioelectrode manufacturing method, bioelectrode and biosensing device |
| CN116754627B (en) * | 2023-08-21 | 2024-03-08 | 苏州矽联传感科技有限公司 | Bioelectrode manufacturing method, bioelectrode and biosensing device |
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Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City) Patentee after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd. Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province Patentee before: SJ Semiconductor (Jiangyin) Corp. |
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