CN203350306U - Second-order compensation reference voltage generation circuit - Google Patents

Abstract

The utility model discloses a second-order compensation reference voltage generation circuit. Based on SiGeBiCMOS technology, the traditional bandgap reference PTAT current is copied in an mirror image manner, a PTAT current square generating circuit comprising NPN transistors in the SiGeBiCMOS technology is employed to generate a current in proportion with the square of temperature to compensate the higher-order term of VBE, and a reference voltage source with a high precision is further obtained. The key point is that the voltage terms respectively related to the one degree term and quadratic term of temperature are generated through the PTAT current and the PTAT square current, the corresponding non-linear term in VBE is compensated, and the reference voltage with a high precision is further obtained. Thereby the PTAT current square generating circuit is the core circuit module. The complexity of the reference circuit is reduced, the stability of the reference voltage is raised, application requirements of a high performance analog-to-digital converter, a high performance digital-to-analog converter and other high performance integrated circuits are satisfied.

Description

A kind of second order standard of compensation voltage generation circuit

Technical field

The utility model relates to the microelectronic circuit technical field, particularly the BiCMOS of a kind of high precision, low-temperature coefficient (bipolar complementary metal oxide semiconductor) reference voltage source circuit.

Background technology

Reference source typically refers to accurate, the stable signal source of doing voltage reference and current reference in circuit.Along with the development of IC industry, in the design of integrated circuit such as high-performance A/D converter (ADC), D/A (DAC), power management, the design of the reference source of high precision, low-temperature coefficient, high stable is very crucial.

Typical CMOS(complementary metal oxide semiconductor (CMOS)) principle of work of with gap reference source is: the base-emitter voltage V with negative temperature coefficient that utilizes parasitic bipolar transistor in CMOS technique _bEdifference DELTA V with the base stage that there is positive temperature coefficient (PTC) under different current densities-emitting stage voltage _bEwith suitable weights addition, thereby reach the purpose of zero-temperature coefficient.An important index weighing voltage-reference is temperature coefficient TC (TemperatureCoefficient), and its expression formula is:

$\mathrm{TC}=\left(\frac{V_{\max }-V_{\min }}{V_{\mathrm{average}}\×(T_{\max }-T_{\min })}\right)\×{10}^6$ Ppm/ ℃ (wherein ppm be 1,000,000/)

Wherein, V _maxand V _minmean respectively reference voltage maximal value and minimum value, V _averagemean reference voltage mean value, T _maxand T _minmean respectively temperature mxm. and minimum.

Typical first compensation phase reference source circuit structure as shown in Figure 1.Wherein, the formed feedback control loop of operational amplifier OTA forces the voltage of its positive-negative input end to remain equal, and the emitter junction Area Ratio of supposing bipolar transistor Q1, Q2 is N, and the base stage of Q1, Q2-emitting stage voltage difference is

so flow through resistance R ₁, R ₂article two, the electric current of branch road equates, and all to absolute temperature, is directly proportional (PTAT),

can draw reference voltage thus

$V_{\mathrm{ref}}=V_{\mathrm{BE}2}+\frac{R_2}{{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="HDA00003536029800011.png,HDA00003536029800021.png"\; state="\{\{state\}\}">R</figure-callout>}}_1}\frac{\mathrm{kT}}{q}\ln \left(N\right)$

Wherein, V _bE2for the base stage of transistor Q2-emitting stage voltage, k is Boltzmann constant, and q is electron charge, and T is absolute temperature.

Due to the base stage of bipolar transistor-emitting stage voltage V _bEthere is negative temperature coefficient, be about-2mV/ ℃, and Δ V _bEthere is positive temperature coefficient (PTC), be about 0.085mV/ ℃.Therefore, suitably select resistance ratio R ₂/ R ₁emitter junction Area Ratio N with transistor Q1, Q2, can make V _refthe single order item of middle temperature is cancelled out each other, and obtains the reference voltage V of a low-temperature coefficient _ref, the temperature coefficient of typical first compensation phase is generally at 10～50ppm/ ℃.As can be seen here, typical with gap reference source is only to base stage-emitting stage voltage V _bEfirst-order linear partly compensate, thereby precision is limited, can't meet the requirement to reference voltage of high-precision analog circuit and Digital Analog Hybrid Circuits.

For the stability that overcomes single order temperature compensation reference source and the restriction of accuracy, the scientific research personnel has proposed multiple high-order compensation technology to obtain the reference voltage of high precision, high stability, second order compensation iso-curvature compensation technique as segmentation curvature correction, index temperature compensation and temperature, its temperature coefficient is about 3～10ppm/ ℃, makes the reference source performance be increased dramatically.Yet these technology all are based on the second order compensating circuit of standard CMOS process, owing to adopting complicated circuit structure, make the reference source chip occupying area large, and because device mismatch causes the bad stability of output voltage.

The utility model content

The utility model provides a kind of second order standard of compensation voltage generation circuit, the utility model has reduced the complexity of reference circuit, improved the stability of reference voltage, met the application of high-performance A/D converter (ADC), D/A (DAC) and other high performance integrated circuit, described below:

The utility model is based on SiGeBiCMOS technique, and by traditional with gap benchmark PTAT electric current is carried out to image copying, the PTAT current squaring generative circuit that utilizes the NPN transistor in SiGeBiCMOS technique to form produces and compensates V to a temperature square proportional electric current _bEhigher order term, and then obtain high-precision reference voltage source.Core concept of the present utility model is to produce respectively and the temperature voltage item that once item is relevant with quadratic term by PTAT electric current and PTAT squared current, compensation V _bEthe nonlinear terms of middle correspondence, and then obtain high-precision reference voltage.Therefore, PTAT current squaring generation circuit is core circuit module of the present utility model.

A kind of second order standard of compensation voltage generation circuit, described second order standard of compensation voltage generation circuit comprises: PTAT current generating circuit, PTAT current squaring generative circuit, the 4th PMOS pipe and the 5th resistance, wherein,

Described PTAT current generating circuit comprises: the source class of a PMOS pipe connects power supply, the one PMOS pipe drain electrode connects the 3rd resistance, base stage and the collector of another termination the 6th NPN transistor of described the 3rd resistance, the emitter of described the 6th NPN transistor connects the 5th resistance, described another port ground connection of the 5th resistance; The 2nd PMOS tube source grade connects described power supply, the 2nd PMOS pipe leaks level and connects the second resistance, another termination first resistance of described the second resistance, another termination the 7th NPN transistor base stage and collector of the first resistance, described the 7th NPN transistor emitter connects the 5th resistance, and the 5th another port of resistance connects described ground; The reverse input end of operational amplifier connects described the 6th NPN transistor base stage and collector, between described the second resistance of the input termination in the same way of described operational amplifier and described the first resistance, described operational amplifier output terminal connects the grid level of a described PMOS pipe, described the 2nd PMOS pipe;

Described PTAT current squaring generative circuit comprises: the source class of the 5th PMOS pipe connects described power supply, described the 5th gate pmos level connects a described PMOS pipe, described the second gate pmos level, described the 5th PMOS pipe leaks level and connects the first NPN transistor collector and base stage, described the first NPN transistor emitting stage connects the 3rd NPN transistor collector and base stage, described the 3rd NPN transistor emitting stage ground connection; The second NPN transistor collector connects described power supply, described the second NPN transistor base stage connects the first NPN transistor base stage, described the second NPN transistor emitting stage connects the 4th NPN transistor collector, described the 4th NPN transistor ground level connects the 3rd NPN transistor base stage, described the 4th NPN transistor emitting stage ground connection; Described the 4th NPN transistor collector of the 4th resistance one termination, the described ground of another termination; The 3rd PMOS tube source grade connects described power supply, described the 3rd gate pmos level and drain electrode short circuit, described the 3rd PMOS pipe drain electrode connects the 5th NPN transistor collector, and described the 5th NPN transistor base stage connects described the 4th NPN transistor collector, and described the 5th NPN transistor emitting stage connects described ground;

Described the 4th PMOS tube source grade connects described power supply, and described the 4th gate pmos level connects described the 3rd gate pmos level, and the 4th PMOS pipe leaks level and connects described the 5th resistance.

The beneficial effect of the technical scheme that the utility model provides is: the PTAT current squaring standard of compensation voltage source that the utility model provides, can effectively improve the precision of reference voltage; The PTAT current squaring standard of compensation voltage source circuit that the utility model provides is simple in structure, only by PTAT current mirror in traditional with gap circuit is copied, can produce and temperature square continuous item by simple PTAT current squaring generative circuit, and then compensate V _bEin quadratic term, power consumption is lower, can be used for, in the circuit such as high-precision A/D converter (ADC), D/A (DAC), having very high practical value.

The accompanying drawing explanation

Fig. 1 has provided traditional with gap reference source schematic diagram;

Fig. 2 has provided the second order standard of compensation voltage generation circuit of the utility model design.

In accompanying drawing, being listed as follows of each parts:

M1: a PMOS pipe; M2: the 2nd PMOS pipe;

M3: the 3rd PMOS pipe; M4: the 4th PMOS pipe;

M5: the 5th PMOS pipe; R ₁: the first resistance;

R ₂: the second resistance; R ₃: the 3rd resistance;

R ₄: the 4th resistance; R ₅: the 5th resistance;

Q1: the first NPN transistor; Q2: the second NPN transistor;

Q3: the 3rd NPN transistor; Q4: the 4th NPN transistor;

Q5: the 5th NPN transistor; Q6: the 6th NPN transistor;

Q7: the 7th NPN transistor; A, B: node;

VDD: power supply; GND: ground;

OTA: operational amplifier; X, Y: emitter junction area ratio;

I _cTAT: the 4th ohmically electric current; V _re _f: reference voltage;

collector current on the 5th NPN transistor;

I _pTAT: the collector current on the 3rd NPN transistor, and for flowing through the electric current of the first resistance, the second resistance and the 3rd resistance.

Embodiment

For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing, the utility model embodiment is described in further detail.

In order to reduce the complexity of reference circuit, improve the stability of reference voltage, meet the application of high-performance A/D converter (ADC), D/A (DAC) and other high performance integrated circuit, the utility model embodiment provides a kind of second order standard of compensation voltage generation circuit, referring to Fig. 2, described below:

The utility model provides a kind of reference voltage source of PTAT current squaring compensation model.This reference voltage source is on existing single order temperature compensation basis, the PTAT electric current produced by the original with gap of mirror image reference source, utilize PTAT current squaring generative circuit to produce and temperature square relevant electric current item, this electric current is injected to resistance and is converted to and temperature square relevant voltage, so with the compensation that superposes of the reference voltage of traditional first compensation phase.The reference voltage source of the PTAT current squaring compensation model that therefore, the utility model provides comprises:

The PTAT current generating circuit, produce PTAT electric current and first compensation phase.

PTAT current squaring generative circuit, for generation of the PTAT squared current.

The PTAT current generating circuit: the source class of a PMOS pipe M1 meets power vd D, and a PMOS pipe M1 drain electrode connects the 3rd resistance R ₃, the 3rd resistance R ₃base stage and the collector of another termination the 6th NPN transistor Q6, the emitter of the 6th NPN transistor Q6 connects the 5th resistance R ₅, the 5th resistance R ₅another port ground connection GND.The 2nd PMOS pipe M2 source class meets power vd D, and the 2nd PMOS pipe M2 leaks level and connects the second resistance R ₂, the second resistance R ₂another termination first resistance R ₁, the first resistance R ₁another termination the 7th NPN transistor Q7 base stage and collector, the 7th NPN transistor Q7 emitter connects the 5th resistance R ₅, the 5th resistance R ₅another port ground connection GND.The reverse input end of operational amplifier OTA connects the 6th NPN transistor Q6 base stage and collector (being the B point), the input termination in the same way of operational amplifier OTA the second resistance R ₂with first between resistance R 1 (being the A point), the grid level of operational amplifier OTA output termination the one PMOS pipe M1, the 2nd PMOS pipe M2.

PTAT current squaring generative circuit: the source class of the 5th PMOS pipe M5 meets power vd D, the 5th PMOS pipe M5 grid level connects a PMOS pipe M1, the 2nd PMOS pipe M2 grid level, the 5th PMOS pipe M5 leaks level and connects the first NPN transistor Q1 collector and base stage, the first NPN transistor Q1 emitting stage connects the 3rd NPN transistor Q3 collector and base stage, the 3rd NPN transistor Q3 emitting stage ground connection GND.The second NPN transistor Q2 collector meets power vd D, the second NPN transistor Q2 base stage connects the first NPN transistor Q1 base stage, the second NPN transistor Q2 emitting stage connects the 4th NPN transistor Q4 collector, the 4th NPN transistor Q4 ground level connects the 3rd NPN transistor Q3 base stage, the 4th NPN transistor Q4 emitting stage ground connection GND.The 4th resistance R ₄one termination the 4th NPN transistor Q4 collector, other end ground connection GND.The 3rd PMOS pipe M3 source class meets power vd D, the 3rd PMOS pipe M3 grid level and drain electrode short circuit, the 3rd PMOS pipe M3 drain electrode connects the 5th NPN transistor Q5 collector, and the 5th NPN transistor Q5 base stage connects the 4th NPN transistor Q4 collector, the 5th NPN transistor Q5 emitting stage ground connection GND.

The 4th PMOS pipe M4 source class meets power vd D, and the 4th PMOS pipe M4 grid level connects the 3rd PMOS pipe M3 grid level, and the 4th PMOS pipe M4 leaks level and connects the 5th resistance R ₅.

The PTAT current squaring standard of compensation voltage source of the utility model design, equal the second resistance R by introducing resistance ₂the 3rd resistance R ₃, the drain-source voltage of having eliminated because of a PMOS pipe M1 does not wait with the drain-source voltage that the 2nd PMOS manages M2 the current mismatch caused.Operational amplifier OTA is connected on respectively A, B 2 points with reverse input end in the same way, and output is connected on a PMOS pipe M1, the 2nd PMOS pipe M2 grid level.By introducing the deep negative feedback, make A, B two point voltages equate, and then the first resistance R is flow through in generation ₁the PTAT electric current, reference source is produced to the single order temperature compensation.

In PTAT current squaring generative circuit, the PTAT electric current produced by the 5th PMOS pipe M5 image copying PTAT current generating circuit, and then produce the PTAT squared current.

It will be appreciated by those skilled in the art that accompanying drawing is the schematic diagram of a preferred embodiment, above-mentioned the utility model embodiment sequence number, just to describing, does not represent the quality of embodiment.

The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, all within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., within all should being included in protection domain of the present utility model.

Claims (1)

1. a second order standard of compensation voltage generation circuit, is characterized in that, described second order standard of compensation voltage generation circuit comprises: PTAT current generating circuit, PTAT current squaring generative circuit, the 4th PMOS pipe and the 5th resistance, wherein,

Described PTAT current generating circuit comprises: the source class of a PMOS pipe connects power supply, the one PMOS pipe drain electrode connects the 3rd resistance, base stage and the collector of another termination the 6th NPN transistor of described the 3rd resistance, the emitter of described the 6th NPN transistor connects the 5th resistance, described another port ground connection of the 5th resistance; The 2nd PMOS tube source grade connects described power supply, the 2nd PMOS pipe leaks level and connects the second resistance, another termination first resistance of described the second resistance, another termination the 7th NPN transistor base stage and collector of the first resistance, described the 7th NPN transistor emitter connects the 5th resistance, and the 5th another port of resistance connects described ground; The reverse input end of operational amplifier connects described the 6th NPN transistor base stage and collector, between described the second resistance of the input termination in the same way of described operational amplifier and described the first resistance, described operational amplifier output terminal connects the grid level of a described PMOS pipe, described the 2nd PMOS pipe;

Described PTAT current squaring generative circuit comprises: the source class of the 5th PMOS pipe connects described power supply, described the 5th gate pmos level connects a described PMOS pipe, described the second gate pmos level, described the 5th PMOS pipe leaks level and connects the first NPN transistor collector and base stage, described the first NPN transistor emitting stage connects the 3rd NPN transistor collector and base stage, described the 3rd NPN transistor emitting stage ground connection; The second NPN transistor collector connects described power supply, described the second NPN transistor base stage connects the first NPN transistor base stage, described the second NPN transistor emitting stage connects the 4th NPN transistor collector, described the 4th NPN transistor ground level connects the 3rd NPN transistor base stage, described the 4th NPN transistor emitting stage ground connection; Described the 4th NPN transistor collector of the 4th resistance one termination, the described ground of another termination; The 3rd PMOS tube source grade connects described power supply, described the 3rd gate pmos level and drain electrode short circuit, described the 3rd PMOS pipe drain electrode connects the 5th NPN transistor collector, and described the 5th NPN transistor base stage connects described the 4th NPN transistor collector, and described the 5th NPN transistor emitting stage connects described ground;

Described the 4th PMOS tube source grade connects described power supply, and described the 4th gate pmos level connects described the 3rd gate pmos level, and the 4th PMOS pipe leaks level and connects described the 5th resistance.

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