CN203288586U - Double-layer shallow cavity type circuit package casing - Google Patents
Double-layer shallow cavity type circuit package casing Download PDFInfo
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- CN203288586U CN203288586U CN2013202392925U CN201320239292U CN203288586U CN 203288586 U CN203288586 U CN 203288586U CN 2013202392925 U CN2013202392925 U CN 2013202392925U CN 201320239292 U CN201320239292 U CN 201320239292U CN 203288586 U CN203288586 U CN 203288586U
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- cavity
- circuit
- circuit package
- capping
- leading foot
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Abstract
The utility model relates to the circuit package technology field, and especially relates to a double-layer shallow cavity type circuit package casing. The double-layer shallow cavity type circuit package casing comprises a housing and a fixed plate disposed in the housing, wherein the top surface and the bottom surface of the housing are respectively provided with a first seal cover and a second seal cover, and the fixed plate is in parallel with the first seal cover and the second seal cover; and a first cavity is formed by the first seal cover and the fixed plate and used for disposing analog circuits, and a second cavity is formed by the second seal cover and the fixed plate and used for disposing digital circuits. The analog circuits and the digital circuits are respectively installed in the two cavities to be isolated, so that high-frequency signals of the two kinds of circuits can be prevented from mutual crosstalk and electromagnetic interference between the two kinds of circuits can be prevented, and reliability of the circuits can be increased.
Description
Technical field
The utility model relates to the circuit package technical field, relates in particular to the shallow cavate circuit package of a kind of bilayer shell.
Background technology
The surface mount of the general hybrid integrated circuit for having high assembled density of Flat type packaged shell, its basis material is kovar alloy, frame-type or column type go between one-sided, bilateral from shell or surrounding is drawn, shell is fit to adopt the capping of parallel seam welding technique, and cover plate generally adopts etch pattern step lid.
Hybrid integrated circuit generally comprises analog circuit and digital circuit, when existing Flat type packaged shell is used for mounting of hybrid integrated circuit, owing to only having an airtight cavity and limited by shell sizes, analog circuit and digital circuit share positive and negative VDD-to-VSS line usually, have crosstalking of the interference of electromagnetic field and high-frequency signal between two kinds of circuit of inside cavity, this impact of electrical quantity on circuit is very large, and the reliability of circuit is low, and existing flat shell mechanism is roomy, uses inconvenience.
Therefore, for above deficiency, the utility model provides the shallow cavate circuit package of a kind of bilayer shell.
The utility model content
The technical problem that (one) will solve
The purpose of this utility model is to provide the problem that the shallow cavate circuit package of a kind of bilayer shell is crosstalked with the interference of electromagnetic field that solves existing Flat type packaged shell and exist between analog circuit and digital circuit in use and high-frequency signal.
(2) technical scheme
In order to solve the problems of the technologies described above, the utility model provides the shallow cavate circuit package of a kind of bilayer shell, it comprises housing and the fixed head that is arranged in described housing, the end face of described housing and bottom surface have respectively the first capping and the second capping, described fixed head is parallel with described the first capping and described the second capping, described the first capping and described fixed head form the first cavity and are used for placing analog circuit, and described the second capping and described fixed head form the second cavity and be used for placing digital circuit.
Wherein, on the coplanar side of described the first cavity and described the second cavity, delegation's leading foot is set respectively, the setting of staggering of the leading foot of the leading foot of described the first cavity and described the second cavity on described the first cavity and the stacked direction of described the second cavity.
Wherein, described leading foot is the glass insulator leading foot.
Wherein, in the side of described the first cavity or the second cavity, be provided with ledge, be provided with flange hole on described ledge.
(3) beneficial effect
technique scheme of the present utility model has following advantage: the double-deck shallow cavate circuit package shell that the utility model provides is by arranging fixed head in housing, described fixed head is parallel with described the first capping and described the second capping, described the first capping and described fixed head form the first cavity and are used for placing analog circuit, described the second capping and described fixed head form the second cavity and are used for placing digital circuit, analog circuit and digital circuit are arranged on respectively in these two cavitys, two kinds of circuit are isolated, can avoid the high-frequency signal of two kinds of circuit mutually crosstalk and two kinds of circuit between electromagnetic interference, improved the reliability of circuit.
Description of drawings
Fig. 1 is the double-deck shallow cavate circuit package shell vertical view of the utility model embodiment;
Fig. 2 is the A-A cutaway view of Fig. 1;
Fig. 3 is the front view of the double-deck shallow cavate circuit package shell of the utility model embodiment.
In figure, capping in 1: the first; Capping in 2: the second; 3: fixed head; 4: leading foot; 5 flange holes.
Embodiment
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.Following examples are used for explanation the utility model, but are not used for limiting scope of the present utility model.
As depicted in figs. 1 and 2, the shallow cavate circuit package of a kind of bilayer provided by the invention shell, it comprises housing and the fixed head 3 that is arranged in described housing, the end face of described housing and bottom surface have respectively the first capping 1 and the second capping 2, described fixed head 3 is parallel with described the first capping and described the second capping, the first capping 1 and fixed head 3 form the first cavity and are used for placing analog circuit, and the second capping 2 and fixed head 3 form the second cavity and be used for placing digital circuit.Analog circuit and digital circuit can be fixed on respectively on two faces of fixed head 3, then with the first capping 1 and the second capping 2, described analog circuit and digital circuit are encapsulated; Analog circuit and digital circuit can adopt PCB circuit board, thick film circuit board or film circuit board; , according to the requirement of overall volume, can rationally regulate the overall dimension size of each cavity; Two kinds of circuit can be provided with positive and negative VDD-to-VSS line separately.
Like this, the circuit package shell that will provide by the utility model, analog circuit and digital circuit are arranged on respectively in the first cavity and the second cavity, two kinds of circuit are isolated, can avoid the high-frequency signal of two kinds of circuit mutually crosstalk and two kinds of circuit between electromagnetic interference, and rational in infrastructure, make easily with easy to use.
Further, as shown in Figure 3, the leading foot that the leading foot of delegation's leading foot 4, the first cavitys and the second cavity be set respectively on the coplanar side of the first cavity and the second cavity setting of staggering on the first cavity and the stacked direction of the second cavity; Leading foot 4 can be the glass insulator leading foot.As required, can one deck leading foot 4 be set in a side, both sides, three sides or four sides of the first cavity, the number of described leading foot 4 can design as required; As required, can one deck leading foot 4 be set in a side, both sides, three sides or four sides of the second cavity, the number of described leading foot 4 can design as required; The output signal of analog circuit and digital circuit can be by leading foot 4 in the outside connection of cavity; The setting of staggering of the single leading foot of the first cavity and the single leading foot of the second cavity, can prevent from causing short circuit in two-layer leading foot contact.
Further, as shown in Figure 1, in the side of described the first cavity or the second cavity, be provided with ledge, be provided with corresponding flange hole 5 on described ledge.Like this, can conveniently circuit package shell of the present utility model be arranged on other workpiece.
The utility model is specially adapted to the HZQZ01 type and stares the encapsulation of super low noise front end circuit.
The above is only preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite that does not break away from the utility model know-why; can also make some improvement and modification, these improve and modification also should be considered as protection range of the present utility model.
Claims (4)
1. the shallow cavate circuit package of bilayer shell, it is characterized in that: it comprises housing and the fixed head (3) that is arranged in described housing, the end face of described housing and bottom surface have respectively the first capping (1) and the second capping (2), described fixed head (3) is parallel with described the first capping and described the second capping, described the first capping (1) and described fixed head (3) form the first cavity and are used for placing analog circuit, and described the second capping (2) and described fixed head (3) form the second cavity and be used for placing digital circuit.
2. circuit package shell according to claim 1, it is characterized in that: delegation's leading foot (4) is set respectively, the setting of staggering of the leading foot of the leading foot of described the first cavity and described the second cavity on the coplanar side of described the first cavity and described the second cavity on described the first cavity and the stacked direction of described the second cavity.
3. circuit package shell according to claim 2, it is characterized in that: described leading foot (4) is the glass insulator leading foot.
4. circuit package shell according to claim 1, it is characterized in that: the side at described the first cavity or the second cavity is provided with ledge, is provided with flange hole (5) on described ledge.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013202392925U CN203288586U (en) | 2013-05-06 | 2013-05-06 | Double-layer shallow cavity type circuit package casing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013202392925U CN203288586U (en) | 2013-05-06 | 2013-05-06 | Double-layer shallow cavity type circuit package casing |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203288586U true CN203288586U (en) | 2013-11-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013202392925U Expired - Lifetime CN203288586U (en) | 2013-05-06 | 2013-05-06 | Double-layer shallow cavity type circuit package casing |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203288586U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185749A (en) * | 2015-06-29 | 2015-12-23 | 华东光电集成器件研究所 | Double-sided encapsulation shell for parallel seam welding |
| CN106449527A (en) * | 2016-08-23 | 2017-02-22 | 太仓市威士达电子有限公司 | Metal casing for integrated circuit packaging |
| CN109936932A (en) * | 2019-03-08 | 2019-06-25 | 河北中瓷电子科技有限公司 | Ceramics, glass and metal ternary encapsulating package and preparation method |
| CN117316878A (en) * | 2023-11-28 | 2023-12-29 | 北京七星华创微电子有限责任公司 | Packaging shell and packaging electronic device |
-
2013
- 2013-05-06 CN CN2013202392925U patent/CN203288586U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105185749A (en) * | 2015-06-29 | 2015-12-23 | 华东光电集成器件研究所 | Double-sided encapsulation shell for parallel seam welding |
| CN105185749B (en) * | 2015-06-29 | 2018-02-27 | 华东光电集成器件研究所 | A kind of double-faced packaging shell for parallel seam welding |
| CN106449527A (en) * | 2016-08-23 | 2017-02-22 | 太仓市威士达电子有限公司 | Metal casing for integrated circuit packaging |
| CN109936932A (en) * | 2019-03-08 | 2019-06-25 | 河北中瓷电子科技有限公司 | Ceramics, glass and metal ternary encapsulating package and preparation method |
| CN117316878A (en) * | 2023-11-28 | 2023-12-29 | 北京七星华创微电子有限责任公司 | Packaging shell and packaging electronic device |
| CN117316878B (en) * | 2023-11-28 | 2024-02-13 | 北京七星华创微电子有限责任公司 | Packaging shell and packaging electronic device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 100015 Jiuxianqiao Chaoyang District, East Beijing Road, building M2, floor 1, No. 2 Patentee after: North China Science and technology group Limited by Share Ltd. Address before: 100015 Jiuxianqiao Chaoyang District, East Beijing Road, building M2, floor 1, No. 2 Patentee before: BEIJING SEVENSTAR ELECTRONIC Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180307 Address after: 100015 Jiuxianqiao Road, Chaoyang District, Chaoyang District, Beijing, No. 798 Art District ceramics one street Patentee after: BEIJING QIXING HUACHUANG MICROELECTRONICS CO.,LTD. Address before: 100015 Jiuxianqiao Chaoyang District, East Beijing Road, building M2, floor 1, No. 2 Patentee before: North China Science and technology group Limited by Share Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20131113 |