CN202855551U - Electronic part - Google Patents
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- CN202855551U CN202855551U CN 201220540807 CN201220540807U CN202855551U CN 202855551 U CN202855551 U CN 202855551U CN 201220540807 CN201220540807 CN 201220540807 CN 201220540807 U CN201220540807 U CN 201220540807U CN 202855551 U CN202855551 U CN 202855551U
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Abstract
The utility model provides an electronic part which can inhibit generation of a relatively large gap in a laminated body. The laminated body (11) is formed by laminating a plurality of ceramic layers and has an upper surface (S1), a bottom surface (S2) and two oppositely-arranged end faces (S3, S4). Capacitor conductor layers (30, 31) are arranged on ceramic layers to form a capacitor. External electrodes (12a, 12b) cover the end faces (S3, S4) and bend back towards the upper surface (S1) and the bottom surface (S2). Pseudo conductor layers (40, 41) are arranged on ceramic layers which are nearer to a position of the bottom surface (S2) than the ceramic layers on which the capacitor conductor layers (30, 31) are arranged, when downward-view observation is carried out from a z-axis direction, the ceramic layers are overlapped with tail ends (Tb, Td) of portions of the external electrodes (12a, 12b) bending back towards the bottom surface (S2), and thickness of the pseudo conductor layers (40, 41) is greater than that of the capacitor conductor layers (30, 31).
Description
Technical field
The utility model relates to electronic unit, particularly relates to the electronic unit of built-in capacitor.
Background technology
As existing electronic unit, the chip-type electronic component that has as everyone knows patent documentation 1 for example to put down in writing.Figure 22 is the sectional structure chart of the chip-type electronic component 500 put down in writing of patent documentation 1.
As shown in figure 22, chip-type electronic component 500 possesses duplexer 502, outer electrode 504a, outer electrode 504b, reinforced layer 506 and capacitor C.Duplexer 502 consists of in the mode of stacked a plurality of ceramic layers, and forms rectangular-shaped.Outer electrode 504a, 504b arrange in the mode of the mutual opposed end face that covers duplexer 502 respectively, and go back to upper surface, lower surface and side.
Capacitor C is built in the duplexer 502, and a plurality of capacitor conductor layers consist of in the mode with the ceramic layer interaction cascading.Reinforced layer 506 is built in duplexer 502, is arranged at upside and the downside by stacked direction than capacitor C.When overlooking observation from stacked direction, reinforced layer 506 is overlapping with the end of outer electrode 504a, 504b.
In the chip-type electronic component 500 that consists of in the above described manner, high to the resistance to ag(e)ing of the mechanical stresses such as bending, stretching.In more detail, after being installed on circuit substrate, the partitioning circuitry substrate at this moment, applies bending stress to chip-type electronic component sometimes, externally forms the crack near electrode 504a and the 504b.Yet, because chip-type electronic component 500 is provided with reinforced layer 506, even therefore externally be formed with the crack near electrode 504a, the 504b, utilize reinforced layer 506 also can suppress the expansion in crack.That is the resistance to ag(e)ing of the mechanical stresses such as, 500 pairs of bendings of chip-type electronic component, stretching improves.
Yet chip-type electronic component 500 still forms the crack at duplexer 502 sometimes, and the crack arrives the capacitor conductor layer.Because also have reinforced layer 506 except having electrode for capacitors in chip-type electronic component 500, so number of poles increases and easily produces fault of construction, therefore need to form than unfertile land the thickness of reinforced layer 506 and capacitor conductor layer.When forming reinforced layer 506 and capacitor conductor layer than unfertile land in the above described manner, owing to forming more emptying aperture (emptying aperture) at reinforced layer 506 and capacitor conductor layer, so till the crack extends near the capacitor conductor layer to avoid reinforced layer 506 by the mode of emptying aperture.Consequently, moisture is invaded the capacitor conductor layer by the crack, and the reliability as capacitor is reduced.
The prior art document
Patent documentation
Patent documentation 1: TOHKEMY 2002-75780 communique
The utility model content
Therefore, the purpose of this utility model is to provide a kind of electronic unit, and this electronic unit can suppress the crack and cross pseudo-conductor layer and arrive near the capacitor conductor.
For the method for dealing with problems
According to an electronic unit that mode is related of the present utility model, described electronic unit possesses: rectangular-shaped duplexer, it is formed by stacked a plurality of dielectric layers, and has two ends and mutual opposed upper surface and bottom surface, mutual opposed two sides and mutual opposed two end faces that are positioned at stacked direction; The capacitor conductor layer, it is arranged on the described dielectric layer and consists of capacitor; Outer electrode, it covers described end face, and goes back to described upper surface and described bottom surface; And pseudo-conductor layer, it is arranged on the described dielectric layer that is positioned at than the position of the more close described bottom surface of described dielectric layer that is provided with described a plurality of capacitor conductors, and when overlooking observation from stacked direction, the part of going back to described bottom surface in this puppet conductor layer and the described outer electrode terminal overlapping, the thickness of the described capacitor conductor layer of the Thickness Ratio of described pseudo-conductor layer is large.
The effect of utility model
According to the utility model, can suppress the crack and cross pseudo-conductor layer and arrive near the capacitor conductor.
Description of drawings
Fig. 1 is the stereoscopic figure of the related electronic unit of execution mode.
Fig. 2 is the exploded perspective view of duplexer of the electronic unit of Fig. 1.
Fig. 3 is the sectional structure chart of the electronic unit of Fig. 1.
Fig. 4 is the sectional structure chart of the electronic unit of comparative example use.
Fig. 5 is the chart that analysis result is shown.
Fig. 6 is the sectional structure chart of the related electronic unit of the first variation.
Fig. 7 is the sectional structure chart of the related electronic unit of the second variation.
Fig. 8 is the sectional structure chart of the related electronic unit of the 3rd variation.
Fig. 9 is the sectional structure chart of the related electronic unit of the 4th variation.
Figure 10 is the inside vertical view of the related electronic unit of the 5th variation.
Figure 11 is the inside vertical view of the related electronic unit of the 6th variation.
Figure 12 is the inside vertical view of the related electronic unit of the 7th variation.
Figure 13 is the inside vertical view of the related electronic unit of the 8th variation.
Figure 14 is the sectional structure chart of the related electronic unit of the 9th variation.
Figure 15 is the inside vertical view of the related electronic unit of the 9th variation.
Figure 16 is the sectional structure chart of the related electronic unit of the tenth variation.
Figure 17 is the sectional structure chart of the related electronic unit of the 11 variation.
Figure 18 is the inside vertical view of the related electronic unit of the 12 variation.
Figure 19 is the inside vertical view of the related electronic unit of the 13 variation.
Figure 20 is the inside vertical view of the related electronic unit of the 14 variation.
Figure 21 is the inside vertical view of the related electronic unit of the 15 variation.
Figure 22 is the sectional structure chart of the chip-type electronic component put down in writing of patent documentation 1.
Among the figure:
The S1 upper surface
The S2 bottom surface
S3, S4 end face
S5, S6 side
Ta～Td terminal (tip)
10,10a～10o electronic unit
11 duplexers
12a, 12b outer electrode
17a～17o ceramic layer
30a～30d, 31a～31c capacitor conductor layer
Pseudo-(the ダ ミ one) conductor layer of 40a～40f, 41a～41f
Embodiment
Below, with reference to accompanying drawing the related electronic unit of execution mode of the present utility model is described.
(structure of electronic unit)
At first, describe with reference to the structure of accompanying drawing to the related electronic unit of execution mode.Fig. 1 is the stereoscopic figure of the related electronic unit 10 of execution mode.Fig. 2 is the exploded perspective view of duplexer 11 of the electronic unit 10 of Fig. 1.In Fig. 2, omit ceramic layer 17g～17i.Fig. 3 is the sectional structure chart of the electronic unit of Fig. 1.Below, the stacked direction of duplexer 11 is defined as the z direction of principal axis.When overlooking observation duplexer 11 from the z direction of principal axis, the direction that the long limit of duplexer 11 is extended is defined as the x direction of principal axis.When overlooking from the z direction of principal axis when observing duplexer 11, the direction that the minor face of duplexer 11 is extended is defined as the y direction of principal axis.
Such as Fig. 1～shown in Figure 3, electronic unit 10 is chip capacitors, possesses duplexer 11, outer electrode 12 (12a, 12b), capacitor conductor layer 30 (30a～30d), 31 (31a～31c) (not shown in Fig. 1) and pseudo-conductor layer 40 (40a～40f), 41 (41a～41f) (not shown in Fig. 1).
As shown in Figure 2, duplexer 11 is by a plurality of ceramic layers (dielectric layer) 17 (17a～17o) consist of so that the mode that is arranged in order from the axial positive direction side direction of z negative direction side is stacked.Ceramic layer 17 forms rectangle, by with BaTiO
3For main component and contain Bi
2O
3Dielectric ceramics make.Below, the interarea of the axial positive direction side of the z of ceramic layer 17 is called the surface, the interarea of the axial negative direction side of the z of ceramic layer 17 is called the back side.
The upper surface S1 of duplexer 11 consists of by being arranged at the axial surface of the ceramic layer 17a of positive direction side of leaning on most of z.The bottom surface S2 of duplexer 11 consists of by being arranged at the axial back side of the ceramic layer 17o of negative direction side of leaning on most of z.And end face S3 is linked to each other by the minor face of the axial negative direction side of the x of ceramic layer 17a～17o and consists of.End face S4 is linked to each other by the minor face of the axial positive direction side of the x of ceramic layer 17a～17o and consists of.Side S5 is linked to each other by the long limit of the axial positive direction side of the y of ceramic layer 17a～17o and consists of.Side S6 is linked to each other by the long limit of the axial negative direction side of the y of ceramic layer 17a～17o and consists of.
Such as Fig. 2 and shown in Figure 3, capacitor conductor layer 30a～30d is arranged at respectively on the surface of ceramic layer 17e, 17g, 17i, 17k, and is built in duplexer 11.Capacitor conductor layer 30a～30d forms rectangle, and extracts out at the minor face of the axial negative direction side of the x of ceramic layer 17e, 17g, 17i, 17k.
Such as Fig. 2 and shown in Figure 3, capacitor conductor layer 31a～31c is arranged at respectively on the surface of ceramic layer 17f, 17h, 17j, and is built in duplexer 11.Capacitor conductor layer 31a～31c forms rectangle, and extracts out at the minor face of the axial positive direction side of the x of ceramic layer 17f, 17h, 17j.When overlooking observation from the z direction of principal axis, capacitor conductor layer 30a～30d and capacitor conductor layer 31a～31c are overlapping.Thus, between capacitor conductor layer 30,31, be formed with capacitor C.
Yet electronic unit 10 reduces pseudo-conductor layer 40,41 emptying aperture amount and increases coverage (coverage) in order to suppress the crack to arrive the capacitor conductor layer.Pseudo-conductor layer 40,41 coverage are preferably more than 70% and below 100%.In the situation that have the pseudo-conductor layer of multilayer, be preferably in whole above-mentioned scopes.And, in order to prevent the fault of construction of duplexer 11, capacitor conductor layer 30,31 thinner, coverage is preferably more than 60% and below 70%.
Observe capacitor conductor layer 30,31 and pseudo-conductor layer 40 when overlooking from the z direction of principal axis, 41 the time, coverage be from 100% deduct be formed at capacitor conductor layer 30,31 and the area of pseudo-conductor layer 40,41 emptying aperture with respect to capacitor conductor layer 30,31 and the value of the ratio of pseudo-conductor layer 40,41 area.Be the mean value of each layer in the situation that have the pseudo-conductor layer of multilayer.The mensuration of coverage is undertaken by following order.
At first, peel off the ceramic layer 17 of electronic unit 10 and make capacitor conductor layer 30,31 and pseudo-conductor layer 40,41 expose, and utilize SEM to take.The image that obtained by SEM is implemented binary coding (binaryzation) process, obtain from capacitor conductor layer 30,31 and the area of the ceramic layer 17 observed of pseudo-conductor layer 40,41 gap (emptying aperture).Then, from 100% deduct with from capacitor conductor layer 30,31 and the area of the ceramic layer 17 observed of pseudo-conductor layer 40,41 gap (emptying aperture) divided by capacitor conductor layer 30,31 and pseudo-conductor layer 40,41 area and multiply by 100 value.Thus, calculate coverage.
(manufacture method of electronic unit)
Then, the manufacture method of electronic unit 10 described.In addition, accompanying drawing is quoted Fig. 1～Fig. 3.
At first, to BaTiO
3, Bi
2O
3, BaCO
3Material powder add the organic solvent of polyvinyl butyral resin system's (Port リ PVC ニ Le Block チ ラ one Le) adhesive and ethanol (エ タ ノ one Le) etc. and drop into ball mill, carry out wet type and be in harmonious proportion and obtain ceramic slurry.Material powder constitutes with BaTiO
3Be 100 moles (モ Le section), Bi
2O
3Be 3 moles, BaCO
3The ratio that is 2 moles is mixed.Utilize the scraping blade method that the ceramic slurry that obtains is formed sheet and makes its drying at slide glass (carrier sheet), should become the ceramic raw material of ceramic layer 17 thin slice (ceramic green sheet) thereby make.The thickness that should become the ceramic raw material thin slice of ceramic layer 17 is for example 6 μ m.
Then, utilize silk screen print method in the ceramic raw material thin slice coating that should become ceramic layer 17 by the paste that conductive material consists of, form thus capacitor conductor layer 30,31 and pseudo-conductor layer 40,41.The paste that is made of conductive material is by adding organic bond to metal dust and organic solvent obtains.Metal dust is Al, Cu, Ni. Capacitor conductor layer 30,31 thickness are more than the 0.1 μ m and below the 2.0 μ m.Pseudo-conductor layer 40,41 thickness are more than the 0.1 μ m and below the 10.0 μ m.
Then, stacked female duplexer that should become the ceramic raw material thin slice of ceramic layer 17 and do not fired.Then, utilize the hydrostatic pressing punching press that female duplexer of not firing is implemented pressure welding.
Then, female duplexer of not firing is cut into given size and obtains a plurality of duplexers of not firing 11.Then, roller (バ レ Le: the barrel) attrition process of attrition process etc. is implemented on the surface of duplexer 11.
Then, the duplexer 11 of will not firing in atmospheric environment is heated to 270 ℃, and makes the adhesive burning in the duplexer 11 of not firing.And then the duplexer 11 of not firing.Firing temperature is for example 650 ℃.
Then, form outer electrode 12 at duplexer 11.Specifically, utilize known infusion method, slit method (engineering method) etc., contain Bi in the coating of the surface of duplexer 11
2O
3-SiO
2-BaO is the Ag paste of frit.Then, in atmosphere, with 600～900 ℃ Ag, Cu, Ni paste are burnt firework (baked is paid け), form thus outer electrode 12.According to above operation, electronic unit 10 is finished.
(effect)
According to above electronic unit 10, such as described below, because coverage is high, emptying aperture is few and coverage is large, even form the crack at duplexer 11, also can utilize pseudo-conductor layer to suppress the crack and arrive near the capacitor conductor layer, because not invading moisture so that the capacitor Reliability Enhancement.
In electronic unit 10, pseudo-conductor layer 40d～40f, 41d～41f are arranged at respectively on the surface of ceramic layer 17l～17n, and this ceramic layer 17l～17n is positioned at the position than the more close bottom surface S2 of ceramic layer 17e～17k that is provided with capacitor conductor layer 30a～30d, 31a～31c.In addition, when overlooking from the z direction of principal axis when observing, as shown in Figure 3, the terminal Tb of the part of turning back to bottom surface S2 among pseudo-conductor layer 40d～40f and the outer electrode 12a is overlapping.When overlooking from the z direction of principal axis when observing, as shown in Figure 3, the terminal Td of the part of turning back to bottom surface S2 among pseudo-conductor layer 41d～41f and the outer electrode 12b is overlapping.In addition, the axial thickness of z of pseudo-conductor layer 40,41 the axial Thickness Ratio capacitor of z conductor layer 30,31 is large.Thus, when carrying out the substrate segmentation process, produce distortion and cause outer electrode 12a, 12b to be stretched at electronic unit 10 and circuit substrate, even thus the crack from terminal Tb, Td to z axial positive direction side extend and produce, because pseudo-conductor layer 40,41 thickness are large (namely, coverage is high), also can suppress this crack and expand to the axial positive direction side of z from pseudo-conductor layer 40f, 41f.Consequently, be suppressed at the crack that duplexer 11 forms the degree that arrives capacitor conductor layer 30,31.
In addition, in electronic unit 10, pseudo-conductor layer 40,41 forms than heavy back, and capacitor conductor layer 30,31 non-ly forms than heavy back.Therefore, can prevent the fault of construction of duplexer 11.
In addition, outer electrode 12a, 12b are implemented electroplating processes.Therefore, when implementing electroplating processes, electroplate liquid might be invaded in the duplexer 11.Yet, in electronic unit 10, because pseudo-conductor layer 40,41 coverage are high, therefore can suppress electroplate liquid and invade in the duplexer 11.
In addition, the destruction toughness (Tough of ceramic layer 17) value is
On the other hand, the pseudo-conductor layer 40 that coverage is high, 41 destruction toughness value are at more than 10 times of destruction toughness value of ceramic layer 7.Thus, in electronic unit 10, near easily damaged terminal Tb, Td, pseudo-conductor layer 40,41 is set, suppresses thus the breakage of duplexer 11.
In addition, in electronic unit 10, terminal Ta～Td and the pseudo-conductor layer 40,41 of outer electrode 12a, 12b are in same potential, and, pseudo-conductor layer 40,41 coverage uprise, and the leakage current that terminal Ta～Td circulates that therefore can suppress from outer electrode 12a, 12b is inputted to capacitor conductor layer 30,31.
(simulation result)
The present inventor carries out the emulation of following explanation for the effect that clearer and more definite electronic unit 10 plays.Fig. 4 is the sectional structure chart of the employed electronic unit 110 of comparative example.
The second model that the present inventor makes the first model of the structure with electronic unit 10 and has the structure of electronic unit 110.Difference between the first model and the second model is pseudo-conductor layer 40,41 have or not.Then, in the first model and the second model externally the expansion in the crack that produces of the terminal Td of electrode 12b resolve.Fig. 5 is the chart that analysis result is shown.Transverse axis represents the x coordinate, and the longitudinal axis represents the z coordinate.The x origin is end face S3, and the z origin is upper surface S1.
According to Fig. 5, know the second model and expand to the axial positive direction side of z by the position that is provided with pseudo-conductor layer 41 at the first model.On the other hand, know in the first model, the crack stops in the position that is provided with pseudo-conductor layer 41 to the advancing of the axial positive direction side of z, and axial positive direction skidding advances along pseudo-conductor layer 41 to x, and namely to extend (Jin in the high part of residual stress capable in the crack).According to this emulation, know by being provided with the large pseudo-conductor layer 40,41 of the high and thick degree of coverage, and residual stress is uprised, thereby can control the propagation direction of large fracture.
(the first variation)
Below, with reference to accompanying drawing the related electronic unit 10a of the first variation is described.Fig. 6 is the sectional structure chart of the related electronic unit 10a of the first variation.
As shown in Figure 6, pseudo-conductor layer 40,41 also can be arranged at upper surface S1 and bottom surface S2 near.That is, pseudo-conductor layer 40,41 arranges in the mode of separating with capacitor conductor layer 30,31.Thus, can be suppressed at pseudo-conductor layer 40,41 and capacitor conductor layer 30,31 between produce electrostatic capacitance.Consequently, in electronic unit 10a, the design that is used for obtaining the electrostatic capacitance value of target becomes easy.
In addition, when pseudo-conductor layer 40,41 separates with capacitor conductor layer 30,31, since pseudo-conductor layer 40,41 with capacitor conductor layer 30,31 between the generation electrostatic capacitance diminish, even therefore produce accumulation skew (ず れ) at pseudo-conductor layer 40,41, the change value of this electrostatic capacitance is little also can.Consequently, in electronic unit 10a, the design that is used for obtaining the electrostatic capacitance value of target becomes easy.
(the second variation)
Below, with reference to accompanying drawing the related electronic unit 10b of the second variation is described.Fig. 7 is the sectional structure chart of the related electronic unit 10b of the second variation.
As shown in Figure 7, pseudo-conductor layer 40,41 also can be arranged at capacitor conductor layer 30,31 near.That is, pseudo-conductor layer 40,41 arranges in the mode of separating with upper surface S1 and bottom surface S2.Thus, pseudo-conductor layer 40,41 is not positioned at the axial two ends of z of duplexer 11.Consequently, can suppress in the duplexer 11 pseudo-conductor layer 40,41 with ceramic layer 17 between produce relevant peeling off.
(the 3rd variation and the 4th variation)
Below, with reference to accompanying drawing the 3rd variation related electronic unit 10c and the related electronic unit 10d of the 4th variation are described.Fig. 8 is the sectional structure chart of the related electronic unit 10c of the 3rd variation.Fig. 9 is the sectional structure chart of the related electronic unit 10d of the 4th variation.
Such as Fig. 8 and shown in Figure 9, pseudo-conductor layer 40,41 the axial end of x can not line up yet.In addition, when overlooking observation from the axial positive direction side of z, in electronic unit 10c, the pseudo-conductor layer overlapping with terminal Ta～Td of outer electrode 12a, 12b is pseudo-conductor layer 40c, 40d, 41c, 41d.Similarly, when overlooking observation from the axial positive direction side of z, in electronic unit 10d, the pseudo-conductor layer overlapping with terminal Ta～Td of outer electrode 12a, 12b is pseudo-conductor layer 40a, 40f, 41a, 41f.
(the 5th variation and the 6th variation)
Below, with reference to accompanying drawing the 5th variation related electronic unit 10e and the related electronic unit 10f of the 6th variation are described.Figure 10 is the inside vertical view of the related electronic unit 10e of the 5th variation.Figure 11 is the inside vertical view of the related electronic unit 10f of the 6th variation.
Such as Figure 10 and shown in Figure 11, pseudo-conductor layer 40 not only is connected with the part of the end face S3 that is formed at outer electrode 12a, also is connected with the side S5 that is formed at outer electrode 12a, the part of S6.Similarly, pseudo-conductor layer 41 not only is connected with the part of the end face S4 that is formed at outer electrode 12b, also is connected with the side S5 that is formed at outer electrode 12b, the part of S6.
In electronic unit 10e, 10f with above such structure, pseudo-conductor layer 40,41 the axial width of y broaden.Thus, even side S5 or side S6 are used as installed surface and electronic unit 10e, 10f are installed on circuit substrate, also can be suppressed at duplexer 11 and produce the crack.
(the 7th variation and the 8th variation)
Below, with reference to accompanying drawing the 7th variation related electronic unit 10g and the related electronic unit 10h of the 8th variation are described.Figure 12 is the inside vertical view of the related electronic unit 10g of the 7th variation.Figure 13 is the inside vertical view of the related electronic unit 10h of the 8th variation.
Such as Figure 12 and shown in Figure 13, pseudo-conductor layer 40,41 also can be split into a plurality of.
(the 9th variation)
Below, with reference to accompanying drawing the related electronic unit 10i of the 9th variation is described.Figure 14 is the sectional structure chart of the related electronic unit 10i of the 9th variation.Figure 15 is the inside vertical view of the related electronic unit 10i of the 9th variation.
Such as Figure 14 and shown in Figure 15, pseudo-conductor layer 40,41 can not be connected with outer electrode 12a, 12b yet.
As mentioned above, pseudo-conductor layer 40,41 is not connected with outer electrode 12a, 12b, and pseudo-conductor layer 40,41 area diminish thus.Consequently, can be suppressed to be provided with between pseudo-conductor layer 40,41 the ceramic layer 17 and produce splitting.
In addition, pseudo-conductor layer 40,41 is not connected with outer electrode 12a, 12b, and pseudo-conductor layer 40,41 does not expose at end face S3, S4 and side S5, the S6 of duplexer 11 thus.Therefore, in the time of being suppressed at the excision of carrying out duplexer 11, roller (バ レ Le), produce splitting being provided with between pseudo-conductor layer 40,41 the ceramic layer 17.In addition, can suppress moisture invades from being provided with between pseudo-conductor layer 40,41 the ceramic layer 17.
(the tenth variation)
Below, with reference to accompanying drawing the related electronic unit 10j of the tenth variation is described.Figure 16 is the sectional structure chart of the related electronic unit 10j of the tenth variation.
As shown in figure 16, pseudo-conductor layer 40,41 also can be arranged at upper surface S1 and bottom surface S2 near.Thus, with the related electronic unit 10a of the first variation in the same manner, in electronic unit 10j, the design that is used for obtaining the target electrostatic capacitance value becomes easy.
(the 11 variation)
Below, with reference to accompanying drawing the related electronic unit 10k of the 11 variation is described.Figure 17 is the sectional structure chart of the related electronic unit 10k of the 11 variation.
As shown in figure 17, pseudo-conductor layer 40,41 also can be arranged at capacitor conductor layer 30,31 near.Thus, with the related electronic unit 10b of the second variation in the same manner, in electronic unit 10k, can suppress in the duplexer 11 pseudo-conductor layer 40,41 with ceramic layer 17 between produce relevant peeling off.
(the 12 variation and the 13 variation)
Below, with reference to accompanying drawing the 12 variation related electronic unit 101 and the related electronic unit 10m of the 13 variation are described.Figure 18 is the inside vertical view of the related electronic unit of the 12 variation 101.Figure 19 is the inside vertical view of the related electronic unit 10m of the 13 variation.
Such as Figure 18 and shown in Figure 19, pseudo-conductor layer 40 also can only be connected with the side S5 that is formed at outer electrode 12a, the part of S6.Similarly, pseudo-conductor layer 41 also can only be connected with the side S5 that is formed at outer electrode 12b, the part of S6.
(the 14 variation and the 15 variation)
Below, with reference to accompanying drawing the 14 variation related electronic unit 10n and the related electronic unit 10o of the 15 variation are described.Figure 20 is the inside vertical view of the related electronic unit 10n of the 14 variation.Figure 21 is the inside vertical view of the related electronic unit 10o of the 15 variation.
Such as Figure 20 and shown in Figure 21, pseudo-conductor layer 40,41 also can be divided into a plurality of.
(other execution mode)
The electronic unit that consists of in the above described manner is not limited to the related electronic unit of described execution mode 10,10a～10o, can change in the scope of its purport.
In the manufacture method of electronic unit 10, although pseudo-conductor layer 40,41 is formed by print process, also can be formed by additive method.Additive method can be enumerated: for example, metal forming is pasted on the ceramic raw material thin slice and forms pseudo-conductor layer 40,41 method, form pseudo-conductor layer 40, method of 41 etc. by injection molding forming.
At first, form pseudo-conductor layer 40 to metal forming is pasted on the ceramic raw material thin slice, 41 method describes.
Utilize static that metal forming is pasted on film (film).Then, to the pseudo-conductor layer 40 that forms the ceramic raw material thin slice, 41 part printing binder.The film and the ceramic raw material thin slice that are pasted with metal forming are fitted, only film is peeled off from the ceramic raw material thin slice.Thus, form pseudo-conductor layer 40,41.
In addition, metal forming is pasted on the ceramic raw material thin slice and forms pseudo-conductor layer 40,41 method, also can be realized by following injection molding forming.
Specifically, in the formation puppet conductor layer 40 of ceramic raw material thin slice, 41 part printing and stacked ceramic paste of carrying out carburizing (カ one ボ Application enters り), and cut, fire.Having carried out on the part of carburizing the part after the coated with ceramic paste burns and loses and become the cavity.Form pseudo-conductor layer 40,41 by injecting the metal paste to this cavity.
Industrial utilizability
As mentioned above, the utility model is useful for electronic unit, particularly arrives near the point the capacitor conductor excellent suppressing the crack to cross pseudo-conductor layer.
Claims (8)
1. an electronic unit is characterized in that,
Possess:
Rectangular-shaped duplexer, it is formed by stacked a plurality of dielectric layers, and has two ends and mutual opposed upper surface and bottom surface, mutual opposed two sides and mutual opposed two end faces that are positioned at stacked direction;
The capacitor conductor layer, it is arranged on the described dielectric layer and consists of capacitor;
Outer electrode, it covers described end face, and goes back to described upper surface and described bottom surface; And
Pseudo-conductor layer, it is arranged on the described dielectric layer that is positioned at than the position of the more close described bottom surface of described dielectric layer that is provided with described a plurality of capacitor conductors, and when overlooking observation from stacked direction, the part of going back to described bottom surface in this puppet conductor layer and the described outer electrode terminal overlapping
The thickness of the described capacitor conductor layer of the Thickness Ratio of described pseudo-conductor layer is large.
2. electronic unit according to claim 1 is characterized in that,
The coverage of described pseudo-conductor layer is more than 70% and below 100%.
3. electronic unit according to claim 2 is characterized in that,
When overlooking the described pseudo-conductor layer of observation from stacked direction, coverage is to deduct the area of the emptying aperture that is formed at this puppet conductor layer with respect to the value of the ratio of the area of this puppet conductor layer from 100%.
4. each described electronic unit in 3 according to claim 1 is characterized in that,
Described pseudo-conductor layer is connected with described outer electrode.
5. each described electronic unit in 3 according to claim 1 is characterized in that,
Described pseudo-conductor layer is not connected with described outer electrode.
6. each described electronic unit in 3 according to claim 1 is characterized in that,
Described outer electrode is gone back to two described sides.
7. electronic unit according to claim 4 is characterized in that,
Described outer electrode is gone back to two described sides.
8. electronic unit according to claim 5 is characterized in that,
Described outer electrode is gone back to two described sides.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011233106A JP5482763B2 (en) | 2011-10-24 | 2011-10-24 | Electronic components |
| JP2011-233106 | 2011-10-24 |
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| Publication Number | Publication Date |
|---|---|
| CN202855551U true CN202855551U (en) | 2013-04-03 |
Family
ID=47986722
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220540807 Expired - Lifetime CN202855551U (en) | 2011-10-24 | 2012-10-22 | Electronic part |
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| JP (1) | JP5482763B2 (en) |
| CN (1) | CN202855551U (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20130104338A (en) * | 2012-03-13 | 2013-09-25 | 삼성전기주식회사 | Multi-layered ceramic electronic component and manufacturing method of the same |
| KR102064007B1 (en) * | 2012-12-13 | 2020-01-08 | 삼성전기주식회사 | Multilayer ceramic device |
| KR101514509B1 (en) * | 2013-02-26 | 2015-04-22 | 삼성전기주식회사 | Multilayer ceramic device |
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| KR101598297B1 (en) * | 2014-10-06 | 2016-02-26 | 삼성전기주식회사 | Multi-layered ceramic electronic component and mounting circuit thereof |
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| KR102149790B1 (en) | 2015-02-13 | 2020-08-31 | 삼성전기주식회사 | Multi-layered ceramic electronic part and board having the same |
| KR101933416B1 (en) | 2016-12-22 | 2019-04-05 | 삼성전기 주식회사 | Capacitor Component |
| JP2018198326A (en) * | 2018-08-21 | 2018-12-13 | 太陽誘電株式会社 | Multilayer capacitor |
| JP2018198327A (en) * | 2018-08-21 | 2018-12-13 | 太陽誘電株式会社 | Multilayer capacitor and method of manufacturing the same |
| KR20210025877A (en) | 2019-08-28 | 2021-03-10 | 삼성전기주식회사 | Multilayered electronic component |
| JP2022032641A (en) | 2020-08-13 | 2022-02-25 | 株式会社村田製作所 | Component built-in substrate |
| US11830676B2 (en) | 2021-01-07 | 2023-11-28 | KYOCERA AVX Components Corporation | Multilayer ceramic capacitor having ultra-broadband performance |
| WO2023243504A1 (en) * | 2022-06-16 | 2023-12-21 | 京セラ株式会社 | Layered ceramic electronic component |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000353636A (en) * | 1999-04-06 | 2000-12-19 | Matsushita Electric Ind Co Ltd | Laminated ceramic part |
| JP2002015941A (en) * | 2000-06-28 | 2002-01-18 | Matsushita Electric Ind Co Ltd | Chip-type electronic component |
| JP2005167290A (en) * | 2005-03-11 | 2005-06-23 | Murata Mfg Co Ltd | Method of manufacturing laminated ceramic electronic component |
| JP2011151224A (en) * | 2010-01-22 | 2011-08-04 | Murata Mfg Co Ltd | Laminated ceramic capacitor, and method of manufacturing the same |
-
2011
- 2011-10-24 JP JP2011233106A patent/JP5482763B2/en active Active
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2012
- 2012-10-22 CN CN 201220540807 patent/CN202855551U/en not_active Expired - Lifetime
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| JP5482763B2 (en) | 2014-05-07 |
| JP2013093374A (en) | 2013-05-16 |
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