CN202855551U - Electronic part - Google Patents

Electronic part Download PDF

Info

Publication number
CN202855551U
CN202855551U CN 201220540807 CN201220540807U CN202855551U CN 202855551 U CN202855551 U CN 202855551U CN 201220540807 CN201220540807 CN 201220540807 CN 201220540807 U CN201220540807 U CN 201220540807U CN 202855551 U CN202855551 U CN 202855551U
Authority
CN
China
Prior art keywords
electronic component
conductor layer
layer
dummy conductor
capacitor
Prior art date
Application number
CN 201220540807
Other languages
Chinese (zh)
Inventor
大塚善弘
Original Assignee
株式会社村田制作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2011233106A priority Critical patent/JP5482763B2/en
Priority to JP2011-233106 priority
Application filed by 株式会社村田制作所 filed Critical 株式会社村田制作所
Application granted granted Critical
Publication of CN202855551U publication Critical patent/CN202855551U/en

Links

Abstract

The utility model provides an electronic part which can inhibit generation of a relatively large gap in a laminated body. The laminated body (11) is formed by laminating a plurality of ceramic layers and has an upper surface (S1), a bottom surface (S2) and two oppositely-arranged end faces (S3, S4). Capacitor conductor layers (30, 31) are arranged on ceramic layers to form a capacitor. External electrodes (12a, 12b) cover the end faces (S3, S4) and bend back towards the upper surface (S1) and the bottom surface (S2). Pseudo conductor layers (40, 41) are arranged on ceramic layers which are nearer to a position of the bottom surface (S2) than the ceramic layers on which the capacitor conductor layers (30, 31) are arranged, when downward-view observation is carried out from a z-axis direction, the ceramic layers are overlapped with tail ends (Tb, Td) of portions of the external electrodes (12a, 12b) bending back towards the bottom surface (S2), and thickness of the pseudo conductor layers (40, 41) is greater than that of the capacitor conductor layers (30, 31).

Description

电子部件 Electronic components

技术领域 FIELD

[0001] 本实用新型涉及电子部件,特别是涉及内置电容器的电子部件。 [0001] The present invention relates to an electronic component, particularly to an electronic component built-in capacitors.

背景技术 Background technique

[0002] 作为现有的电子部件,众所周知有例如专利文献I所记载的芯片型电子部件。 [0002] As a conventional electronic component, there is known a chip-type electronic component described in Patent Document I, for example. 图22是专利文献I所记载的芯片型电子部件500的剖面结构图。 FIG 22 is a cross-sectional structural view of the chip-type electronic component 500 described in Patent Document I.

[0003] 如图22所示,芯片型电子部件500具备层叠体502、外部电极504a、外部电极504b、加强层506以及电容器C。 [0003] 22, the chip-type electronic component 500 includes a laminate 502, the external electrode 504a, an external electrode 504b, reinforcing layer 506, and a capacitor C. 层叠体502以层叠多个陶瓷层的方式构成,并形成为长方体状。 The laminate 502 to stack a plurality of layers constituting the ceramic, and is formed into a rectangular parallelepiped shape. 外部电极504a、504b分别以覆盖层叠体502的相互对置的端面的方式设置,并折回到上表面、下表面以及侧面。 External electrodes 504a, 504b are opposed to each other to cover the end surfaces of the laminated body 502 is provided, folded back and an upper surface, a lower surface and side surfaces.

[0004] 电容器C内置于层叠体502内,多个电容器导体层以与陶瓷层交互层叠的方式构成。 [0004] The capacitor C built in the laminated body 502, a plurality of capacitor conductor layer and ceramic layers are alternately stacked configuration mode. 加强层506内置于层叠体502,设置于比电容器C靠层叠方向的上侧以及下侧。 506 incorporated in the laminated reinforcing layer 502 disposed on the capacitor C in the stacking direction than the upper side and the lower side. 当从层叠方向俯视观察时,加强层506与外部电极504a、504b的端部重叠。 When viewed from the laminating direction of the plan, reinforcing layer 506 and the external electrode 504a, the end portion 504b overlapping.

[0005] 在以上述方式构成的芯片型电子部件500中,对弯曲、拉伸等机械应力的耐老化性闻。 [0005] In the chip-type electronic component 500 configured as described above, aging resistance to mechanical stress smell bending, stretching or the like. 更详细地说,在安装于电路基板之后,有时分割电路基板,此时,向芯片型电子部件施加弯曲应力,在外部电极504a和504b附近形成裂缝。 More specifically, after mounting on the circuit board, the circuit board may dividing this case, the bending stress is applied to the chip-type electronic component, formation of cracks in the vicinity of the external electrodes 504a and 504b. 然而,由于芯片型电子部件500设置有加强层506,因此即使在外部电极504a、504b附近形成有裂缝,利用加强层506也能抑制裂缝的扩展。 However, since the chip-type electronic component 500 is provided with a reinforcing layer 506, thereby forming cracks even in the vicinity of the external electrodes 504a 504b, with the reinforcing layer 506 can be suppressed crack propagation. 即,芯片型电子部件500对弯曲、拉伸等机械应力的耐老化性提高。 I.e., improved aging resistance to mechanical stresses bending and stretching 500 pairs of chip-type electronic component.

[0006] 然而,芯片型电子部件500仍旧有时在层叠体502形成裂缝,裂缝到达电容器导体层。 [0006] However, the chip-type electronic component 500 may still be formed in the laminated body 502 cracks, cracks reaching the conductor layer capacitor. 因为在芯片型电子部件500中除了具有电容器电极之外还具有加强层506,因此电极个数增加而容易产生结构缺陷,因此需要较薄地形成加强层506以及电容器导体层的厚度。 Because, in addition to chip-type electronic component having the capacitor electrode 500 also has a reinforcing layer 506 outside, thus increasing the number of electrodes and prone to structural defects, and therefore the thickness of the reinforcing layer 506 and the capacitor conductor layer needs to be formed thinly. 当以上述方式较薄地形成加强层506以及电容器导体层时,由于在加强层506以及电容器导体层形成较多的空孔(空孔),因此裂缝以避开加强层506而通过空孔的方式延伸至电容器导体层附近为止。 When the above-described manner is formed a thin reinforcing layer 506 and the conductive layer of the capacitor, as more voids (pores) formed in the reinforcing layer 506 and the capacitor conductor layer, so as to avoid crack reinforcement layer 506 by way of pores extends up to the vicinity of the conductor layer capacitor. 其结果是,水分通过裂缝而侵入电容器导体层,使作为电容器的可靠性降低。 As a result, intrusion of moisture through the cracks and the capacitor conductor layer, reducing the reliability as a capacitor.

[0007] 现有技术文献 [0007] The prior art documents

[0008] 专利文献 [0008] Patent Document

[0009] 专利文献1:日本特开2002-75780号公报实用新型内容 [0009] Patent Document 1: Japanese Laid-Open Patent Publication No. 2002-75780 SUMMARY

[0010] 因此,本实用新型的目的在于提供一种电子部件,该电子部件能够抑制裂缝越过伪导体层而到达电容器导体附近。 [0010] Accordingly, the present invention aims to provide an electronic component, the electronic component can be suppressed over the crack reaches the vicinity of the dummy conductor layer capacitor conductor.

[0011] 用于解决问题的方法 [0011] A method for solving problems

[0012] 根据本实用新型的一个方式所涉及的电子部件,所述电子部件具备:长方体状的层叠体,其由层叠多个电介质层而成,并具有位于层叠方向的两端且相互对置的上表面和底面、相互对置的两个侧面、以及相互对置的两个端面;电容器导体层,其设置于所述电介质层上并构成电容器;外部电极,其覆盖所述端面,并且折回到所述上表面以及所述底面;以及伪导体层,其被设置在位于比设置有所述多个电容器导体的所述电介质层更靠近所述底面的位置的所述电介质层上,并且从层叠方向俯视观察时,该伪导体层与所述外部电极中的折回到所述底面的部分的末端重叠,所述伪导体层的厚度比所述电容器导体层的厚度大。 [0012] The electronic component of the present invention related to one embodiment, the electronic component includes: a rectangular parallelepiped-shaped laminate comprising a laminate made of a plurality of dielectric layers, and having both ends of the stacking direction and opposed to each other the upper surface and a bottom surface, two side surfaces opposite to each other, and the mutually opposing two end; capacitor conductor layer disposed on the dielectric layer and forming a capacitor; external electrode covering the end surfaces, and the folded and said upper surface to said bottom surface; and a dummy conductor layer, which is provided with a plurality of provided positioned than the dielectric layer of the capacitor closer to the conductor on the bottom surface of the dielectric layer position, and from when viewed from the laminating direction, the dummy conductor layer and the external electrode of the bottom surface of the folded back end portion overlaps the dummy conductor layer has a thickness greater than the thickness of the conductive layer of the capacitor.

[0013] 实用新型的效果 [0013] Advantageous Effects

[0014] 根据本实用新型,能够抑制裂缝越过伪导体层而到达电容器导体附近。 [0014] According to the present invention, cracks can be suppressed over the conductive layer to reach the vicinity of the dummy capacitor conductor.

附图说明 BRIEF DESCRIPTION

[0015] 图1是一个实施方式所涉及的电子部件的外观立体图。 [0015] FIG. 1 is an external perspective view of an electronic component according to a preferred embodiment.

[0016] 图2是图1的电子部件的层叠体的分解立体图。 [0016] FIG. 2 is an exploded perspective view of the laminate of the electronic component of FIG.

[0017] 图3是图1的电子部件的剖面结构图。 [0017] FIG. 3 is a sectional structural view of the electronic component of FIG.

[0018] 图4是比较例使用的电子部件的剖面结构图。 [0018] FIG. 4 is a sectional structural view of a comparative example using the electronic component.

[0019] 图5是示出解析结果的图表。 [0019] FIG. 5 is a graph illustrating the analysis result.

[0020] 图6是第一变形例所涉及的电子部件的剖面结构图。 [0020] FIG. 6 is a cross-sectional structural view of an electronic component according to a first modification.

[0021] 图7是第二变形例所涉及的电子部件的剖面结构图。 [0021] FIG. 7 is a cross-sectional structural view of an electronic component according to a second modification.

[0022] 图8是第三变形例所涉及的电子部件的剖面结构图。 [0022] FIG. 8 is a sectional structural view of an electronic component according to a third modification.

[0023] 图9是第四变形例所涉及的电子部件的剖面结构图。 [0023] FIG. 9 is a cross-sectional structural view of an electronic component according to a fourth modification.

[0024] 图10是第五变形例所涉及的电子部件的内部俯视图。 [0024] FIG 10 is an internal plan view of an electronic component according to a fifth modification.

[0025] 图11是第六变形例所涉及的电子部件的内部俯视图。 [0025] FIG 11 is an internal plan view of an electronic component according to a sixth modification.

[0026] 图12是第七变形例所涉及的电子部件的内部俯视图。 [0026] FIG 12 is an internal plan view of an electronic component according to a seventh modification.

[0027] 图13是第八变形例所涉及的电子部件的内部俯视图。 [0027] FIG 13 is an internal plan view of an electronic component according to an eighth modification.

[0028] 图14是第九变形例所涉及的电子部件的剖面结构图。 [0028] FIG. 14 is a cross-sectional structural view of an electronic component according to a ninth modification.

[0029] 图15是第九变形例所涉及的电子部件的内部俯视图。 [0029] FIG 15 is an internal plan view of an electronic component according to a ninth modification.

[0030] 图16是第十变形例所涉及的电子部件的剖面结构图。 [0030] FIG. 16 is a cross-sectional structural view of an electronic component according to a tenth modification.

[0031] 图17是第i^一变形例所涉及的电子部件的剖面结构图。 [0031] FIG 17 is a cross-sectional structural view of a i ^ electronic component according to a deformation.

[0032] 图18是第十二变形例所涉及的电子部件的内部俯视图。 [0032] FIG 18 is an internal plan view of an electronic component according to a twelfth modification.

[0033] 图19是第十三变形例所涉及的电子部件的内部俯视图。 [0033] FIG 19 is an internal plan view of an electronic component according to a thirteenth modification.

[0034] 图20是第十四的变形例所涉及的电子部件的内部俯视图。 [0034] FIG 20 is an internal plan view of a fourteenth embodiment of the electronic component of the modification involved.

[0035] 图21是第十五变形例所涉及的电子部件的内部俯视图。 [0035] FIG 21 is an internal electronic component according to a fifteenth modification plan view.

[0036] 图22是专利文献I所记载的芯片型电子部件的剖面结构图。 [0036] FIG. 22 is a cross-sectional structural view of the chip-type electronic component described in Patent Document I.

[0037] 图中: [0037] FIG:

[0038] SI上表面 [0038] SI upper surface

[0039] S2 底面 [0039] S2 bottom surface

[0040] S3、S4 端面 [0040] S3, S4 end surface

[0041] S5、S6 侧面 [0041] S5, S6 side

[0042] Ta〜Td末端(先端) [0042] Ta~Td end (tip)

[0043] 10、IOa〜IOo 电子部件 [0043] 10, IOa~IOo electronic component

[0044] 11层叠体[0045] 12a、12b 外部电极 [0044] 11 laminated body [0045] 12a, 12b external electrode

[0046] 17a〜17o 陶瓷层 [0046] 17a~17o ceramic layer

[0047] 30a〜30d、31a〜31c 电容器导体层 [0047] 30a~30d, 31a~31c capacitor conductor layer

[0048] 40a 〜40f、41a 〜41f 伪(夕' S — )导体层 [0048] 40a ~40f, 41a ~41f dummy (Xi 'S -) conductor layer

具体实施方式 Detailed ways

[0049] 以下,参照附图对本实用新型的实施方式所涉及的电子部件进行说明。 [0049] Hereinafter, with reference to the accompanying drawings of the electronic component of the present invention embodiment will be described.

[0050](电子部件的结构) [0050] (Structure of the electronic component)

[0051] 首先,参照附图对一个实施方式所涉及的电子部件的结构进行说明。 [0051] First, with reference to the drawings of a structure of an electronic component according to the embodiment will be described. 图1是一个实施方式所涉及的电子部件10的外观立体图。 FIG. 1 is an external perspective view of an electronic component according to an embodiment 10 of the embodiment. 图2是图1的电子部件10的层叠体11的分解立体图。 FIG 2 is an exploded perspective view of a multilayer electronic component body 10 of FIG. 11. 在图2中省略陶瓷层17g〜17i。 17g~17i ceramic layer is omitted in FIG. 图3是图1的电子部件的剖面结构图。 3 is a sectional structural view of the electronic component of FIG. 以下,将层叠体11的层叠方向定义为z轴方向。 Hereinafter, a stacking direction of the stack 11 is z-axis direction. 当从z轴方向俯视观察层叠体11时,将层叠体11的长边延伸的方向定义为X轴方向。 When viewed from the z-axis direction to observe 11, it will define the longitudinal direction of the laminated body 11 extending in the X-axis direction of the laminate. 当从z轴方向俯视观察层叠体11时,将层叠体11的短边延伸的方向定义为y轴方向。 When viewed from the z-axis direction were observed 11, 11 defined in the direction of the short sides of laminated body extending to the y-axis laminate.

[0052] 如图1〜图3所示,电子部件10是芯片电容器,具备层叠体11、外部电极12 (12a、12b)、电容器导体层30(30a〜30d)、31(31a〜31c)(在图1中未图示)以及伪导体层40 (40a 〜40f)、41 (41a 〜41f)(在图1 中未图示)。 [0052] As shown in FIG. 1 ~ 3, the electronic component is a chip capacitor 10 includes a laminate body 11, the external electrode 12 (12a, 12b), the capacitor conductor layer 30 (30a~30d), 31 (31a~31c) ( in FIG. 1, not shown) and 40 (40a ~40f dummy conductor layer), 41 (41a ~41f) (not shown in FIG. 1).

[0053] 层叠体11形成为长方体状,其具有位于z轴方向的两端的上表面SI以及底面S2、相互对置(对向+ 3 )的端面S3、S4、以及相互对置的侧面S5、S6。 [0053] The laminate 11 is formed into a rectangular parallelepiped shape, with both ends of the z-axis direction on the surface SI and a bottom surface S2, facing each other (on the + 3) end surfaces of S3, S4, and the mutually opposed side surfaces S5, S6. 但是,层叠体11通过实施倒角而在角以及棱线中形成带有圆形的形状。 However, the laminated body 11 is formed with a circular shape and the ridge lines at the corner by chamfering. 以下,在层叠体11中,将z轴方向的正方向侧的面设为上表面SI,将z轴方向的负方向侧的面设为底面S2。 Hereinafter, the laminated body 11 in the plane direction of the z-axis positive direction side is the upper surface of the SI, the surface to the bottom surface S2 of the negative z-axis direction side. 并且,将X轴方向的负方向侧的面设为端面S3,将X轴方向的正方向侧的面设为端面S4。 Then, the surface of the X-axis direction to the negative direction side end surface S3, the face direction is the positive X-axis direction side end surface S4. 并且,将y轴方向的正方向侧的面设为侧面S5,将y轴方向的负方向侧的面设为侧面S6。 Then, the surface of the positive direction of the y-axis direction side of the side surface S5, the plane side surface S6 is set to the negative direction of the y-axis direction side. 当电子部件10安装于电路基板时,底面S2是与该电路基板的主面对置的安装面。 When the electronic component 10 mounted on the circuit board, the bottom surface S2 with a main face of the circuit board facing the mounting surface.

[0054] 如图2所示,层叠体11通过多个陶瓷层(电介质层)17 (17a〜17ο)以从ζ轴方向的正方向侧向负方向侧依次排列的方式层叠而构成。 [0054] As shown in FIG, 11 to the positive direction from the negative ζ-axis direction by the lateral plurality of ceramic layers (dielectric layer) 17 (17a~17ο) sequentially arranged side are laminated laminate 2 is configured. 陶瓷层17形成为长方形,由以BaTiO3为主要成分且含有Bi2O3的电介质陶瓷制成。 Ceramic layer 17 is formed in a rectangular shape, made of a dielectric ceramic BaTiO3 as a main component and containing Bi2O3 as a. 以下,将陶瓷层17的ζ轴方向的正方向侧的主面称作表面,将陶瓷层17的ζ轴方向的负方向侧的主面称作背面。 Hereinafter, the positive direction of the main surface of the ceramic layer ζ-axis direction is referred to as the side surface 17, the principal surface of the negative direction ζ-axis direction of the ceramic layer 17 is referred to as the back side.

[0055] 层叠体11的上表面SI由设置于ζ轴方向的最靠正方向侧的陶瓷层17a的表面构成。 [0055] SI upper surface of the laminate 11 is constituted by ζ in the axial direction is provided on the most positive side surface of the ceramic layer 17a. 层叠体11的底面S2由设置于Z轴方向的最靠负方向侧的陶瓷层17ο的背面构成。 The back surface of the ceramic layer closest to the negative side of the bottom surface S2 of the laminate 11 by the setting in the Z-axis direction 17ο configuration. 并且,端面S3由陶瓷层17a〜17ο的χ轴方向的负方向侧的短边相连而构成。 Further, the end surface S3 are connected to the negative side in the short-axis direction of the ceramic layers χ 17a~17ο edge. 端面S4由陶瓷层17a〜17ο的χ轴方向的正方向侧的短边相连而构成。 Constituted by the end surface S4 is connected to the positive direction side of the short-axis direction of the ceramic layers χ 17a~17ο edge. 侧面S5由陶瓷层17a〜17ο的y轴方向的正方向侧的长边相连而构成。 S5 long side of the positive y-axis direction of the ceramic layers 17a~17ο side edges so connected together. 侧面S6由陶瓷层17a〜17ο的y轴方向的负方向侧的长边相连而构成。 S6 by the long side of the ceramic layer 17a~17ο y-axis direction is connected to the negative side edges constituted.

[0056] 电容器导体层30a〜30d、31a〜31c是以Al、N1、Cu等为主要成分的材料制成的导体层,并通过经陶瓷层17相互对置而构成电容器。 [0056] The capacitor conductor layer 30a~30d, 31a~31c conductor layer is made of Al, N1, Cu as the main component, and 17 opposed to each other through a capacitor constituted by the ceramic layer.

[0057] 如图2以及图3所示,电容器导体层30a〜30d分别设置于陶瓷层17e、17g、171、17k的表面上,并内置于层叠体11。 [0057] As shown in FIG. 2 and FIG. 3, the capacitor conductor layer 30a~30d are disposed on the ceramic layer 17e, 17g, surface 171,17k and 11 incorporated in the laminate. 电容器导体层30a〜30d形成为长方形,并在陶瓷层17e、17g、171、17k的χ轴方向的负方向侧的短边抽出。 30a~30d capacitor conductor layer formed in a rectangular shape, and extracting the short-axis direction is the negative direction χ ceramic layer 17e, 17g, 171,17k side edges. [0058] 如图2以及图3所示,电容器导体层31a〜31c分别设置于陶瓷层17f、17h、17j的表面上,并内置于层叠体11。 [0058] As shown in FIG. 2 and FIG. 3, the capacitor conductor layers are provided in the ceramic layer 31a~31c 17f, 17h, 17j of the upper surface, and 11 incorporated in the laminate. 电容器导体层31a〜31c形成为长方形,并在陶瓷层17f、17h、17j的X轴方向的正方向侧的短边抽出。 31a~31c capacitor conductor layer formed in a rectangular shape, and the ceramic layer 17f, 17h, the short direction of the X axis positive direction side edge 17j withdrawn. 当从z轴方向俯视观察时,电容器导体层30a〜30d与电容器导体层31a〜31c重叠。 When viewed from the z-axis direction, and the capacitor conductor layer capacitor conductor layer 31a~31c 30a~30d overlap. 由此,在电容器导体层30、31之间形成有电容器C。 Thus, between the capacitor conductor layers 30, 31 is formed with a capacitor C.

[0059] 外部电极12a、12b是涂敷Ag、Cu、Ni糊剂(paste)而形成的电极。 [0059] The external electrodes 12a, 12b is coated with Ag, Cu, Ni electrode paste (Paste) is formed. 外部电极12a覆盖端面S3,并且向上表面S1、底面S2以及侧面S5、S6折回。 External electrode covering the end face 12a S3, and up surfaces S1, S2 and the bottom surface side surfaces S5, S6 folded. 并且,外部电极12a与电容器导体层30a〜30d连接。 The external electrode 12a is connected to the capacitor conductor layer 30a~30d. 更详细地说,外部电极12a以覆盖电容器导体层30a〜30d从端面S3露出的部分的方式覆盖层叠体11的端面S3的整面。 More specifically, the external electrode portion 12a so as to cover the capacitor conductor layer exposed from the end surface S3 30a~30d cover the entire surface of the end surface S3 of the laminate 11.

[0060] 外部电极12b覆盖端面S4,并且向上表面S1、底面S2以及侧面S5、S6折回。 [0060] The end face of the external electrode 12b covering S4, and upwardly surfaces S1, S2 and the bottom surface side surfaces S5, S6 folded. 并且,外部电极12b与电容器导体层31a〜31c连接。 Further, the external electrode 12b is connected to the capacitor conductor layer 31a~31c. 更详细地说,外部电极12b以覆盖电容器导体层31a〜31c从端面S4露出的部分的方式覆盖层叠体11的端面S4的整面。 More specifically, the external electrode 12b so as to cover the capacitor conductor layer 31a~31c cover the entire surface of the laminate 11 from the end surface S4 of the embodiment is exposed portion of the end surface S4.

[0061] 伪导体层40a〜40f、41a〜41f是由以Al、N1、Cu为主要成分的材料制成的导体层。 [0061] The dummy conductor layer 40a~40f, 41a~41f conductive layer is made to Al, N1, Cu as the main component. 伪导体层40a〜40c、41a〜41c分别设置于陶瓷层17b〜17d的表面上,该陶瓷层17b〜17d位于比设置有电容器导体层30a〜30d、31a〜31c的陶瓷层17e〜17k更靠近上表面SI的位置。 Dummy conductor layer 40a~40c, 41a~41c are disposed on the surface of the ceramic layer 17b~17d, 17b~17d positioned over the ceramic layer is provided with a conductor layer capacitor 30a~30d, 31a~31c ceramic layers closer 17e~17k the position of the upper surface SI. 伪导体层40d〜40f、41d〜41f分别设置于陶瓷层171〜17η的表面上,该陶瓷层171〜17η位于比设置有电容器导体层30a〜30d、31a〜31c的陶瓷层17e〜17k靠近底面S2的位置。 Dummy conductor layer 40d~40f, 41d~41f are disposed on the surface of the ceramic layer 171~17η, 171~17η positioned over the ceramic layer is provided with a conductor layer capacitor 30a~30d, 31a~31c near the bottom surface of the ceramic layer 17e~17k S2 position.

[0062] 伪导体层40a〜40f形成为长方形,在陶瓷层17b〜17d、171〜17η的χ轴方向的负方向侧的短边抽出。 [0062] 40a~40f dummy conductor layer formed in a rectangular, drawn in the negative direction of the ceramic layer short 17b~17d, χ axis direction 171~17η side edges. 由此,伪导体层40a〜40f与外部电极12a连接。 Thus, the dummy conductor connected to the outer electrode layer 40a~40f 12a. 并且,当从z轴方向俯视观察时,如图3所示,伪导体层40a〜40c与外部电极12a中的向上表面SI折回的部分的末端Ta重叠。 And, in plan view from the z-axis direction in FIG. 3, the upper surface Ta and the terminal SI of the external electrode 12a of the folded portion of the dummy conductor layer 40a~40c overlap. 当从z轴方向俯视观察时,如图3所示,伪导体层40d〜40f与外部电极12a中的向底面S2折回的部分的末端Tb重叠。 When viewed from the z-axis direction, as shown in FIG. 3, the external terminal electrodes 12a in the folded portion of the bottom surface S2 of the dummy conductor layer overlapping 40d~40f Tb.

[0063] 伪导体层41a〜41f形成为长方形,在陶瓷层17b〜17d、171〜17η的χ轴方向的正方向侧的短边抽出。 [0063] 41a~41f dummy conductor layer formed in a rectangular, ceramic layer 17b~17d, the positive direction of the short axis direction χ 171~17η side edge extraction. 由此,伪导体层41a〜41f与外部电极12b连接。 Thus, the dummy conductor connected to the outer electrode layer 41a~41f 12b. 并且,当从z轴方向俯视观察时,如图3所示,伪导体层41a〜41c与外部电极12b中的向上表面SI折回的部分的末端Tc重叠。 And, in plan view from the z-axis direction in FIG. 3, the end surface of upward SI Tc external electrode 12b of the folded portion of the dummy conductor layer 41a~41c overlap. 当从z轴方向俯视观察时,如图3所示,伪导体层41d〜41f与外部电极12b中的向底面S2折回的部分的末端Td重叠。 When viewed from the z-axis direction, as shown in FIG. 3, the external terminal electrodes 12b in the folded portion of the bottom surface S2 of the dummy conductor layer overlapping 41d~41f Td.

[0064] 然而,电子部件10为了抑制裂缝到达电容器导体层而减少伪导体层40、41的空孔量并增加覆盖度(coverage)。 [0064] However, the electronic component 10 in order to suppress crack reaching the capacitor conductor layer to reduce the amount of pores dummy conductor layers 40, 41 and increase the coverage (coverage). 伪导体层40、41的覆盖度优选在70%以上且100%以下。 Coverage of the dummy conductor layers 40, 41 is preferably 70% or more and 100% or less. 在具有多层伪导体层的情况下,优选为全部上述范围内。 In the case of a multi-layer dummy conductor layer, preferably in all of the above range. 并且,为了防止层叠体11的结构缺陷,电容器导体层30、31较薄,覆盖度优选在60%以上且70%以下。 In order to prevent structural defects in the laminate 11, the capacitor conductor layers 30 and 31 is thin, coverage is preferably 60% or more and 70% or less.

[0065] 当从z轴方向俯视观察电容器导体层30、31以及伪导体层40、41时,覆盖度是从100%减去形成于电容器导体层30、31以及伪导体层40、41的空孔的面积相对于电容器导体层30、31以及伪导体层40、41的面积的比例的值。 [0065] When viewed from a plan blank z-axis direction when the capacitor conductor layers 30, 31 and the dummy conductor layers 40, 41, 100% coverage is subtracted from the capacitor formed conductive layers 30, 31 and the dummy conductor layers 40, 41 and the area of ​​the hole with respect to the value proportional to the area of ​​the conductor layer 40, 41 of the dummy capacitor conductor layer 30, 31. 在具有多层伪导体层的情况下为各层的平均值。 In the case of a multi-layer dummy conductor layer having an average value of each layer. 覆盖度的测定由以下的顺序进行。 Determination of coverage is performed by the following procedure.

[0066] 首先,剥离电子部件10的陶瓷层17而使电容器导体层30、31以及伪导体层40、41露出,并利用SEM进行拍摄。 [0066] First, the peeling layer 10 of the ceramic electronic component 17 and the dummy capacitor conductor layers 30, 31 are exposed conductor layers 40, 41, and shot by SEM. 对由SEM得到的图像实施二进制编码(二值化)处理,来求出从电容器导体层30、31以及伪导体层40、41的间隙(空孔)观察到的陶瓷层17的面积。 SEM images obtained by the binary encoding embodiment (binarization) process, to determine the area of ​​the ceramic layer 17 is viewed from the capacitor 30, 31 and the conductor layers (voids) 40 and 41 of the dummy gap to the conductor layer. 然后,从100%减去将从电容器导体层30、31以及伪导体层40、41的间隙(空孔)观察的陶瓷层17的面积除以电容器导体层30、31以及伪导体层40、41的面积并乘以100的值。 Then, by subtracting from 100% from the capacitor conductor layer 30, 31 and the gaps (pores) of the area of ​​the dummy conductor layers 40, 41 of the ceramic layer 17 divided by the observation capacitor conductor layers 30, 31 and the dummy conductor layers 40, 41 area and multiplied by 100. 由此,计算出覆盖度。 Thus, the degree of coverage is calculated.

[0067](电子部件的制造方法) [0067] (Method of manufacturing electronic component)

[0068] 接着,对电子部件10的制造方法进行说明。 [0068] Next, a method for manufacturing the electronic component 10 will be described. 此外,附图引用图1〜图3。 In addition, reference to the accompanying drawings FIG. 1 ~ 3.

[0069] 首先,向BaTi03、Bi203、BaCO3的原料粉末添加聚乙烯醇缩丁醛系('J ^ 二> I' 7)粘合剂以及乙醇(工夕7 —> )等的有机溶剂并投入球磨机,进行湿式调和而 [0069] First, the raw material powder Bi203, BaCO3 is added to a polyvinyl butyral BaTi03 ( 'J ^ two> I' 7) binder, and ethanol (Tokyo station 7 ->) and the like into an organic solvent a ball mill, wet blending and

得到陶瓷浆。 To obtain a ceramic slurry. 原料粉末构成为以BaTiO3为100摩尔量(ΐ >部)、Bi203为3摩尔量、BaCO3为2摩尔量的比例混合。 BaTiO3 powder material configured in an amount of 100 mol (ΐ> portion), Bi203 to 3 molar amount, BaCO3 2 molar ratio of the amount of mixing. 利用刮片法将得到的陶瓷浆在载片(carrier sheet)上形成为片状并使其干燥,从而制成应成为陶瓷层17的陶瓷生料薄片(ceramic green sheet)。 Using a doctor blade method to obtain a ceramic slurry is formed on a carrier sheet (carrier sheet) into a sheet and dried to prepare a green sheet to be the ceramic (ceramic green sheet) 17 of the ceramic layer. 应成为陶瓷层17的陶瓷生料薄片的厚度为例如6 μ m。 Be the ceramic green sheet 17, for example, the ceramic layer has a thickness 6 μ m.

[0070] 接着,利用丝网印刷法在应成为陶瓷层17的陶瓷生料薄片上涂敷由导电性材料构成的糊剂,由此形成电容器导体层30、31以及伪导体层40、41。 [0070] Next, a screen printing method using the paste should be the ceramic layers of the ceramic green sheet 17 made of a coated conductive material, thereby forming conductive layers 30, 31 and the dummy capacitor conductor layers 40, 41. 由导电性材料构成的糊剂是通过向金属粉末添加有机粘合剂以及有机溶剂而得到的。 A paste conductive material is obtained by adding an organic binder and an organic solvent to the obtained metal powder. 金属粉末是Al、Cu、Ni。 Metal powder is Al, Cu, Ni. 电容器导体层30、31的厚度在O.1 μ m以上且2. O μ m以下。 The thickness of the conductor layers 30, 31 in the capacitor O.1 μ m or more and 2. O μ m or less. 伪导体层40、41的厚度在O.1 μ m以上且10. Ομπι以下。 The thickness of the conductor layer 40, 41 in the dummy O.1 μ m or more and less 10. Ομπι.

[0071] 接着,层叠应成为陶瓷层17的陶瓷生料薄片而得到未烧制的母层叠体。 [0071] Next, the laminated ceramic green sheet to be the ceramic layer 17 to obtain a mother laminate unfired. 然后,利用静水压冲压对未烧制的母层叠体实施压焊。 Then, the mother laminate hydrostatic press unsintered embodiment bonding.

[0072] 接着,将未烧制的母层叠体切成规定尺寸而得到多个未烧制的层叠体11。 [0072] Subsequently, the unfired mother laminate is cut into a predetermined size to obtain a plurality of unfired laminate 11. 然后,对层叠体11的表面实施滚轮(/S' P :barrel)研磨加工等的研磨加工。 Then, the roller embodiment (/ S 'P: barrel) on the surface of the laminate 11 of the grinding polishing processing.

[0073] 接着,在大气环境中将未烧制的层叠体11加热至270°C,并使未烧制的层叠体11中的粘合剂燃烧。 [0073] Next, the atmosphere in the unfired laminate 11 was heated to 270 ° C, the adhesive 11 and the unfired laminate combustion. 进而烧制未烧制的层叠体U。 Further firing unfired laminate U. 烧制温度为例如650°c。 The firing temperature is, for example 650 ° c.

[0074] 接着,在层叠体11形成外部电极12。 [0074] Next, the external electrodes 12 are formed in the stacked body 11. 具体地说,利用公知的浸泡法、狭缝方法(工法)等,在层叠体11的表面涂敷含有Bi2O3-SiO2-BaO系玻璃料的Ag糊剂。 Specifically, a known immersion method, a slit method (working method), the laminate 11 is applied to the surface containing Ag paste Bi2O3-SiO2-BaO-based glass frit. 然后,在大气中以600〜900°C对Ag、Cu、Ni糊剂进行烧上彩花(焼付(t ),由此形成外部电极12。根据以上的工序,电子部件10完成。 Then, in the atmosphere of Ag, Cu, Ni paste to be 600~900 ° C on flower color burning (firing pay (T), thereby forming the external electrode 12. The above steps, the electronic component 10 is completed.

[0075](效果) [0075] (Effects)

[0076] 根据以上的电子部件10,如以下说明那样,由于覆盖度高、空孔少、且覆盖度大,SP使在层叠体11形成裂缝,也能够利用伪导体层来抑制裂缝到达电容器导体层附近,因不侵入水分而使得电容器可靠性提高。 [0076] According to the above electronic component 10, as described below, due to the high degree of coverage, fewer pores, and a large coverage, SP cracks formed in the laminate 11, the conductive layer can be suppressed using a pseudo crack reaches the capacitor conductor nearby layer, so that moisture does not enter because of the capacitor to improve the reliability.

[0077] 在电子部件10中,伪导体层40d〜40f、41d〜41f分别设置于陶瓷层171〜17η的表面上,该陶瓷层171〜17η位于比设置有电容器导体层30a〜30d、31a〜31c的陶瓷层17e〜17k更靠近底面S2的位置。 [0077] In the electronic component 10, the dummy conductor layer 40d~40f, 41d~41f are disposed on the surface of the ceramic layer 171~17η, 171~17η positioned over the ceramic layer is provided with a conductor layer capacitor 30a~30d, 31a~ 31c 17e~17k ceramic layers closer to the bottom surface S2. 另外,当从ζ轴方向俯视观察时,如图3所示,伪导体层40d〜40f与外部电极12a中的向底面S2折回的部分的末端Tb重叠。 Further, when viewed from a plan ζ axis direction in FIG. 3, the external terminal electrodes 12a and Tb in the folded portion of the bottom surface S2 dummy conductor layer 40d~40f overlap. 当从ζ轴方向俯视观察时,如图3所示,伪导体层41d〜41f与外部电极12b中的向底面S2折回的部分的末端Td重叠。 When viewed from a plan view ζ axis direction in FIG. 3, the external terminal electrodes 12b in the folded portion of the bottom surface S2 of the dummy conductor layer overlapping 41d~41f Td. 另外,伪导体层40、41的ζ轴方向的厚度比电容器导体层30、31的ζ轴方向的厚度大。 Further, the thickness of the ζ-axis direction dummy conductor layer 40, 41 is larger than ζ-axis direction of the capacitor conductor layer 30, 31 thickness. 由此,当进行基板分割工序时,在电子部件10以及电路基板产生变形而导致外部电极12a、12b被拉伸,由此即使裂缝从末端Tb、Td向ζ轴方向的正方向侧延伸而产生,由于伪导体层40、41的厚度大(S卩,覆盖度高),也能抑制该裂缝自伪导体层40f、41f向ζ轴方向的正方向侧扩展。 Thus, when the step of dividing the substrate, deformation in the electronic component and the circuit board 10 and the external lead electrodes 12a, 12b are stretched, whereby even if the crack extends from the end of Tb, Td ζ-axis positive direction side is generated Since the thickness of the layers 40, 41 of the large dummy conductor (S Jie, high coverage), the crack can be suppressed from the dummy conductor layer 40f, 41f positive direction of the ζ-axis direction side expansion. 其结果是,抑制在层叠体11形成到达电容器导体层30、31的程度的裂缝。 As a result, inhibition of the formation of the laminate 11 reaches the level of the capacitor conductive layers 30, 31 of the cracks.

[0078] 另外,在电子部件10中,伪导体层40、41较厚地形成,而电容器导体层30、31非较厚地形成。 [0078] Further, in the electronic component 10, the dummy conductor layers 40, 41 are formed thick, and the capacitor conductive layers 30, 31 are formed non thick. 因此,能够防止层叠体11的结构缺陷。 Accordingly, it is possible to prevent structural defects in the laminate 11.

[0079] 另外,对外部电极12a、12b实施电镀处理。 [0079] Further, the external electrodes 12a, 12b plating process. 因此,当实施电镀处理时,电镀液有可能侵入层叠体11内。 Therefore, when the plating process, the plating solution may have intruded within the laminate 11. 然而,在电子部件10中,由于伪导体层40、41的覆盖度高,因此能够抑制电镀液侵入层叠体11内。 However, in the electronic component 10, since the dummy conductor layer 40, 41 has a high coverage, it is possible to suppress the intrusion of the plating solution 11 laminate.

[0080] 另外,陶瓷层17的破坏韧性(靭性)值为3MPav「m〜7MPav「m。另一方面,覆盖度高的伪导体层40、41的破坏韧性值在陶瓷层7的破坏韧性值的10倍以上。由此,在电子部件10中,在容易破损的末端Tb、Td附近设置伪导体层40、41,由此抑制层叠体11的破损。 [0080] Further, the ceramic layer fracture toughness (toughness) values ​​3MPav 17 "m~7MPav" m. On the other hand, high fracture toughness value dummy covering conductor layer 40, 41 in the fracture toughness value of the ceramic layers 7 more than 10 times. thus, in the electronic component 10, is easily broken at the end of Tb, dummy conductor layers 40, 41 disposed near Td, thereby suppressing breakage of the stacked body 11.

[0081] 另外,在电子部件10中,外部电极12a、12b的末端Ta〜Td与伪导体层40、41处于相同电位,并且,伪导体层40、41的覆盖度变高,因此能抑制从外部电极12a、12b的末端Ta〜Td流通的泄漏电流向电容器导体层30、31输入。 [0081] Further, in the electronic component 10, the external electrodes 12a, 12b of the end Ta~Td dummy conductor layers 40, 41 at the same potential, and the coverage of the dummy conductor layers 40, 41 is increased, can be suppressed from external electrodes 12a, 12b of the tip leakage flow Ta~Td current input to the capacitor conductor layer 30, 31.

[0082](仿真结果) [0082] (simulation result)

[0083] 本申请的发明人为了更明确电子部件10起到的效果,进行以下说明的仿真。 [0083] The inventors of the present application in order to more clearly the effect of the electronic component 10 functions, the simulation will be described below. 图4是比较例所使用的电子部件Iio的剖面结构图。 FIG 4 is a cross-sectional structural view of an electronic component Iio Comparative Example used.

[0084] 本申请的发明人制成具有电子部件10的结构的第一模型以及具有电子部件110的结构的第二模型。 [0084] The inventors of the present application is made to have a first model of a structure of the electronic component 10 and a second model of the structure of the electronic component 110. 第一模型与第二模型之间的不同点在于伪导体层40、41的有无。 A different point between the first model and the second model is that the presence or absence of the dummy conductor layers 40, 41. 然后,对第一模型以及第二模型中在外部电极12b的末端Td所产生的裂缝的扩展进行解析。 Then, the first model and the second model is extended at the end of the external electrode 12b Td generated cracks resolution. 图5是示出解析结果的图表。 FIG 5 is a graph illustrating the analysis result. 横轴表示χ坐标,纵轴表示z坐标。 The horizontal axis represents the coordinates χ, the vertical axis represents the z-coordinate. χ坐标的原点为端面S3, z坐标的原点为上表面SI。 χ coordinate origin end surface S3, z coordinate origin on the surface SI.

[0085] 根据图5,知晓第二模型通过在第一模型设置有伪导体层41的位置而向z轴方向的正方向侧扩展。 [0085] According to FIG. 5, the second model is provided in its first position where the model dummy conductor layer 41 and the positive direction of the z-axis direction side expansion. 另一方面,知晓在第一模型中,裂缝在设置有伪导体层41的位置停止向z轴方向的正方向侧的行进,而沿着伪导体层41向χ轴方向的正方向侧行进,即裂缝在残留应力高的部分延伸(進行)。 On the other hand, in its first model, the cracks at a position where the dummy conductor layer 41 is stopped traveling direction of the positive z-axis direction side, and the positive direction of the χ axis 41 side in the direction along the travel dummy conductor layer, i.e., the fracture extending in a high residual stress in portion (be). 根据本仿真,知晓通过设置有覆盖度高且厚度大的伪导体层40、41,而使残留应力变高,从而能够控制大裂缝的扩展方向。 According to the present simulation is provided with a cover by its large thickness and a high dummy conductor layers 40, 41, the residual stress becomes high, so that the direction of expansion can be controlled in large cracks.

[0086](第一变形例) [0086] (First Modification)

[0087] 以下,参照附图对第一变形例所涉及的电子部件IOa进行说明。 [0087] Hereinafter, with reference to the accompanying drawings of the electronic component IOa first modification will be described. 图6是第一变形例所涉及的电子部件IOa的剖面结构图。 FIG 6 is a cross-sectional structural view of the electronic component IOa according to a first modification.

[0088] 如图6所示,伪导体层40、41也可以设置于上表面SI以及底面S2的附近。 As shown in [0088] FIG. 6, the dummy conductor layers 40, 41 may be provided near the surface of the bottom surface SI and S2 are on. 即,伪导体层40、41以与电容器导体层30、31分离的方式设置。 That is, dummy conductor layers 40, 41 to the capacitor conductor layers 30, 31 separated manner. 由此,能抑制在伪导体层40、41与电容器导体层30、31之间产生静电电容。 This suppresses an electrostatic capacitance between the conductive layers 40, 41 and the dummy capacitor conductor layer 30, 31. 其结果是,在电子部件IOa中,用于得到目标的静电电容值的设计变得容易。 As a result, in the electronic component IOa, for obtaining the electrostatic capacitance values ​​of the target can be easily designed.

[0089] 另外,当伪导体层40、41与电容器导体层30、31分离时,由于在伪导体层40、41与电容器导体层30、31之间产生的静电电容变小,因此即使在伪导体层40、41产生累积偏移(f Λ ),该静电电容的变动值小亦可。 [0089] Further, when dummy conductor layers 40, 41 30, 31 separated from the conductive layer of the capacitor, since the capacitance produced between 30 and 31 becomes smaller dummy conductor layers 40, 41 and the capacitor conductor layer, even if the dummy conductive layers 40, 41 have a cumulative offset (f Λ), change in the capacitance value is small also. 其结果是,在电子部件IOa中,用于得到目标的静电电容值的设计变得容易。 As a result, in the electronic component IOa, for obtaining the electrostatic capacitance values ​​of the target can be easily designed.

[0090](第二变形例) [0090] (Second Modification)

[0091] 以下,参照附图对第二变形例所涉及的电子部件IOb进行说明。 [0091] Hereinafter, with reference to the accompanying drawings of the electronic component IOb second modification will be described. 图7是第二变形例所涉及的电子部件IOb的剖面结构图。 FIG. 7 is a cross-sectional structural view of an electronic component IOb second modification example of the invention.

[0092] 如图7所示,伪导体层40、41也可以设置于电容器导体层30、31的附近。 [0092] As shown in FIG. 7, the dummy conductor layers 40, 41 may be provided in the vicinity of the conductor layers 30, 31 of the capacitor. S卩,伪导体层40、41以与上表面SI以及底面S2分离的方式设置。 S Jie, dummy conductor layers 40, 41 to separate the upper surface of the bottom surface SI and S2 provided. 由此,伪导体层40、41不位于层叠体11的ζ轴方向的两端。 Thus, no dummy conductor layers 40, 41 located at both ends of the axial direction ζ laminate 11. 其结果是,能抑制层叠体11中在伪导体层40、41与陶瓷层17之间产生相关剥离。 As a result, the laminate can be suppressed peeling generate a correlation between the dummy conductor 11 in layers 40, 41 and the ceramic layer 17.

[0093](第三变形例以及第四变形例) [0093] (third modification and fourth modification)

[0094] 以下,参照附图对第三变形例所涉及的电子部件IOc以及第四变形例所涉及的电子部件IOd进行说明。 [0094] Hereinafter, with reference to the accompanying drawings of the electronic component IOd IOc electronic component according to a modification of the third and a fourth modification will be described. 图8是第三变形例所涉及的电子部件IOc的剖面结构图。 FIG 8 is a cross-sectional structural view of an electronic component according to a third modification of IOc. 图9是第四变形例所涉及的电子部件IOd的剖面结构图。 9 is a cross-sectional structural view of an electronic component according to a fourth modification of IOd.

[0095] 如图8以及图9所示,伪导体层40、41的χ轴方向的端部也可以不对齐。 As shown in [0095] FIGS. 8 and 9, the end portion of the axial direction χ dummy conductor layers 40, 41 may not be aligned. 此外,当从ζ轴方向的正方向侧俯视观察时,在电子部件IOc中,与外部电极12a、12b的末端Ta〜Td重叠的伪导体层为伪导体层40c、40d、41c、41d。 Further, when the plan view from the positive ζ-axis direction side, in the electronic component IOc, the external electrodes 12a, 12b of the end Ta~Td dummy conductor layer overlapping the dummy conductor layers 40c, 40d, 41c, 41d. 同样地,当从ζ轴方向的正方向侧俯视观察时,在电子部件IOd中,与外部电极12a、12b的末端Ta〜Td重叠的伪导体层为伪导体层40a、40f、41a、41f。 Likewise, when viewed from the axial direction from the positive direction ζ side, in the electronic component in IOd, the external electrodes 12a, 12b of the end Ta~Td dummy conductor layer overlapping the dummy conductor layers 40a, 40f, 41a, 41f.

[0096](第五变形例以及第六变形例) [0096] (Fifth modification example and a sixth modification)

[0097] 以下,参照附图对第五变形例所涉及的电子部件IOe以及第六变形例所涉及的电子部件IOf进行说明。 [0097] Hereinafter, with reference to the accompanying drawings of the electronic component IOf IOe electronic component according to a fifth modification, and a sixth modification will be described. 图10是第五变形例所涉及的电子部件IOe的内部俯视图。 FIG 10 is an internal plan view of the electronic component IOe according to a fifth modification. 图11是第六变形例所涉及的电子部件IOf的内部俯视图。 FIG 11 is an internal plan view of the electronic component IOf sixth modification example of the invention.

[0098] 如图10以及图11所示,伪导体层40不仅与形成于外部电极12a的端面S3的部分连接,还与形成于外部电极12a的侧面S5、S6的部分连接。 [0098] FIGS. 10 and 11, the dummy conductor layer 40 is connected not only to the end surface portion S3 is formed on the external electrode 12a is also formed on the external electrode 12a of the side surface S5, S6 connecting portion. 同样地,伪导体层41不仅与形成于外部电极12b的端面S4的部分连接,还与形成于外部电极12b的侧面S5、S6的部分连接。 Similarly, dummy conductor layer 41 is not formed in the portion of the external electrode 12b is connected to the end surface S4, also, S6 side surface portion S5 is connected to the external electrode 12b is formed.

[0099] 在具有以上那样的结构的电子部件10e、10f中,伪导体层40、41的y轴方向的宽度变宽。 [0099] In the electronic component having the above structure as 10e, 10f, the y-axis direction width of the dummy conductor layer 40, 41 is widened. 由此,即使侧面S5或者侧面S6被用作安装面且电子部件10e、10f安装于电路基板,也能够抑制在层叠体11产生裂缝。 Accordingly, even if the side surface S5 or S6 is used as the mounting surface side and the electronic component 10e, 10f mounted on the circuit board, it is possible to suppress generation of cracks in the laminate 11.

[0100](第七变形例以及第八变形例) [0100] (Seventh and Eighth Modification Modification)

[0101] 以下,参照附图对第七变形例所涉及的电子部件IOg以及第八变形例所涉及的电子部件IOh进行说明。 [0101] Hereinafter, with reference to the accompanying drawings of the electronic component IOh IOg electronic component according to a seventh modification and an eighth modification will be described. 图12是第七变形例所涉及的电子部件IOg的内部俯视图。 FIG 12 is an electronic component according to a seventh modification IOg internal plan view. 图13是第八变形例所涉及的电子部件IOh的内部俯视图。 FIG 13 is an internal plan view of the electronic component IOh an eighth modification example of the invention.

[0102] 如图12以及图13所示,伪导体层40、41也可以被分割为多个。 [0102] FIGS. 12 and 13, the dummy conductor layers 40, 41 may be divided into a plurality.

[0103](第九变形例) [0103] (Ninth Modification)

[0104] 以下,参照附图对第九变形例所涉及的电子部件IOi进行说明。 [0104] Hereinafter, with reference to the accompanying drawings of the electronic component IOi ninth modification will be described. 图14是第九变形例所涉及的电子部件IOi的剖面结构图。 FIG 14 is a cross-sectional structural view of an electronic component IOi a ninth modification example of the invention. 图15是第九变形例所涉及的电子部件IOi的内部俯视图。 FIG 15 is an electronic component according to a ninth modification IOi internal plan view.

[0105] 如图14以及图15所示,伪导体层40、41也可以不与外部电极12a、12b连接。 [0105] FIGS. 14 and 15, the dummy conductor layers 40, 41 may not be the external electrodes 12a, 12b are connected.

[0106] 如上所述,伪导体层40、41不与外部电极12a、12b连接,由此伪导体层40、41的面积变小。 [0106] As described above, the dummy layers 40, 41 is not the external conductor electrodes 12a, 12b are connected, whereby the area of ​​the dummy conductor layers 40, 41 becomes small. 其结果是,能抑制在设置有伪导体层40、41的陶瓷层17之间产生层间剥离。 As a result, the interlayer peeling can be suppressed is provided between the dummy conductor layer 17 of the ceramic layers 40, 41.

[0107] 另外,伪导体层40、41不与外部电极12a、12b连接,由此伪导体层40、41不在层叠体11的端面S3、S4以及侧面S5、S6露出。 [0107] Further, the dummy conductor layers 40, 41 is not the external electrodes 12a, 12b are connected, whereby the end surface S3 dummy body 11 is not laminated conductive layers 40, 41, S4, and side surfaces S5, S6 are exposed. 因此,能抑制在进行层叠体11的切除、滚轮(レル)时,在设置有伪导体层40、41的陶瓷层17之间产生层间剥离。 Thus, it can be suppressed during removal of the stacked body 11, when the roller (Hikaru Toray), provided with a delamination occurs between the dummy conductor layer 17 of the ceramic layers 40, 41. 另外,能抑制水分从设置有伪导体层40、41的陶瓷层17之间侵入。 Further, water can be suppressed from invasion provided between the dummy conductor layer 17 of the ceramic layers 40, 41.

[0108](第十变形例) [0108] (Tenth Modification)

[0109] 以下,参照附图对第十变形例所涉及的电子部件10J进行说明。 [0109] Hereinafter, with reference to the accompanying drawings of the electronic component 10J tenth modification will be described. 图16是第十变形例所涉及的电子部件10j的剖面结构图。 FIG 16 is a cross-sectional structure view of an electronic component according to a tenth modification of 10j.

[0110] 如图16所示,伪导体层40、41也可以设置于上表面SI以及底面S2的附近。 As shown in [0110] FIG. 16, the dummy conductor layers 40, 41 may be provided on the bottom surface near the surface SI and S2. 由此,与第一变形例所涉及的电子部件1Oa相同地,在电子部件1Oj中,用于得到目标静电电容值的设计变得容易。 Thus, the first modification of the electronic component 1Oa the same manner, in the electronic component 1Oj, for obtaining a target value of the electrostatic capacitance can be easily designed.

[0111](第十一变形例) [0111] (Eleventh Modification)

[0112] 以下,参照附图对第十一变形例所涉及的电子部件1Ok进行说明。 [0112] Hereinafter, with reference to the accompanying drawings of the electronic component 1Ok an eleventh modification will be described. 图17是第十一变形例所涉及的电子部件IOk的剖面结构图。 FIG 17 is a cross-sectional structural view of an electronic component IOk an eleventh modification example of the invention.

[0113] 如图17所示,伪导体层40、41也可以设置于电容器导体层30、31的附近。 [0113] 17, the dummy conductor layers 40, 41 may be provided in the vicinity of the conductor layers 30, 31 of the capacitor. 由此,与第二变形例所涉及的电子部件IOb相同地,在电子部件1Ok中,能抑制层叠体11中在伪导体层40、41与陶瓷层17之间产生相关剥离。 Thus, the electronic component IOb second modified example of the same, in the electronic component 1Ok, the laminate can be suppressed peeling generate a correlation between the dummy conductor 11 in layers 40, 41 and the ceramic layer 17.

[0114](第十二变形例以及第十三变形例) [0114] (Modification twelfth and thirteenth modified embodiment)

[0115] 以下,参照附图对第十二变形例所涉及的电子部件101以及第十三变形例所涉及的电子部件IOm进行说明。 [0115] Hereinafter, with reference to the accompanying drawings of an electronic component according to a twelfth modification IOm electronic component 101 and a thirteenth modification will be described. 图18是第十二变形例所涉及的电子部件101的内部俯视图。 FIG 18 is an internal plan view of an electronic component according to a twelfth modification 101. 图19是第十三变形例所涉及的电子部件IOm的内部俯视图。 FIG 19 is an internal plan view of the electronic component IOm a thirteenth modification example of the invention.

[0116] 如图18以及图19所示,伪导体层40也可以仅与形成于外部电极12a的侧面S5、S6的部分连接。 [0116] FIG. 18 and FIG. 19, the dummy conductor layer 40 may be formed only on the side surface S5 12a of the external electrode, the connecting portion S6. 同样地,伪导体层41也可以仅与形成于外部电极12b的侧面S5、S6的部分连接。 Similarly, dummy conductor layer 41 may be formed only on the side surface 12b of the external electrodes S5, S6 connecting portion.

[0117](第十四的变形例以及第十五变形例) [0117] (Fourteenth and fifteenth modification modification)

[0118] 以下,参照附图对第十四的变形例所涉及的电子部件IOn以及第十五变形例所涉及的电子部件IOo进行说明。 [0118] Hereinafter, with reference to the accompanying drawings IOo electronic component and the electronic component IOn fifteenth modification of the fourteenth embodiment of the modification according to the will be described. 图20是第十四的变形例所涉及的电子部件IOn的内部俯视图。 FIG 20 is a modified embodiment of an electronic component according to the fourteenth IOn internal plan view. 图21是第十五变形例所涉及的电子部件1Oo的内部俯视图。 FIG 21 is an electronic component according to a fifteenth modification of the interior 1Oo plan view.

[0119] 如图20以及图21所示,伪导体层40、41也可以分割为多个。 As shown in [0119] FIG. 20 and FIG. 21, the dummy conductor layers 40, 41 may be divided into a plurality.

[0120](其它的实施方式) [0120] (Other Embodiments)

[0121] 以上述方式构成的电子部件并不局限于所述实施方式所涉及的电子部件10、IOa〜10ο,在其主旨的范围内能够变更。 [0121] In the electronic component described above is not limited to the configuration of the embodiment related to the electronic component embodiment 10, IOa~10ο, within its spirit can be changed.

[0122] 在电子部件10的制造方法中,虽然伪导体层40、41由印刷法形成,但也可以由其他方法形成。 [0122] In the manufacturing method of the electronic component 10, although the dummy conductor layers 40, 41 formed by the printing method, but may be formed by other methods. 其他方法可以举出:例如,将金属箔粘贴于陶瓷生料薄片而形成伪导体层40、41的方法、通过注射模塑成形来形成伪导体层40、41的方法等。 Other methods include: for example, a metal foil bonded to the ceramic green sheet and a pseudo conductive layer 40, 41 is formed by injection molding method or the like to form the dummy conductor layer 40, 41.

[0123] 首先,对将金属箔粘贴于陶瓷生料薄片而形成伪导体层40、41的方法进行说明。 [0123] First, a method dummy conductor layers 40, 41 of metal foil bonded to the ceramic green sheet is formed will be described.

[0124] 利用静电将金属箔粘贴于薄膜(film)。 [0124] The metal foil is attached to a thin film (film) using an electrostatic. 接着,向形成陶瓷生料薄片的伪导体层40,41的部分印刷粘合剂。 Subsequently, the dummy conductor portion of the printed adhesive layer is formed of a ceramic green sheet 40, 41. 使粘贴有金属箔的薄膜与陶瓷生料薄片贴合,仅将薄膜从陶瓷生料薄片剥离。 The joining of thin metal foil and bonded ceramic green sheet, only the film was peeled off from the ceramic green sheet. 由此,形成伪导体层40、41。 Thus, a dummy conductor layer 40, 41.

[0125] 另外,将金属箔粘贴于陶瓷生料薄片而形成伪导体层40、41的方法,也可以由以下的注射模塑成形来实现。 [0125] Further, a metal foil bonded to the ceramic green sheet and the method of forming the dummy conductor layers 40, 41, may be realized by the injection molding.

[0126] 具体地说,在陶瓷生料薄片的形成伪导体层40、41的部分印刷并层叠进行了渗碳(力一# >Λ·9 )的陶瓷糊剂,并进行切割、烧制。 [0126] Specifically, the dummy conductor layer portion formed by printing a ceramic green sheet and laminate 40, 41 carburized (a force #> Λ · 9) of the ceramic paste, cut and fired. 进行了渗碳的部分上涂敷陶瓷糊剂后的部分烧失而成为空洞。 Partial carburization carried out on the coated portion of the ceramic paste is burnt out and become empty. 通过向该空洞注入金属糊剂来形成伪导体层40、41。 Dummy conductor layers 40 are formed by metal paste is injected to the cavity.

[0127] 工业上的可利用性 [0127] INDUSTRIAL APPLICABILITY

[0128] 如上所述,本实用新型对于电子部件是有用的,特别是在能够抑制裂缝越过伪导体层而到达电容器导体附近的点上优异。 [0128] As described above, the present invention is useful for an electronic component, in particular over the dummy conductor layer can suppress crack reaches a point near the capacitor conductor is excellent.

Claims (8)

1. 一种电子部件,其特征在于, 具备: 长方体状的层叠体,其由层叠多个电介质层而成,并具有位于层叠方向的两端且相互对置的上表面和底面、相互对置的两个侧面、以及相互对置的两个端面; 电容器导体层,其设置于所述电介质层上并构成电容器; 外部电极,其覆盖所述端面,并且折回到所述上表面以及所述底面;以及伪导体层,其被设置在位于比设置有所述多个电容器导体的所述电介质层更靠近所述底面的位置的所述电介质层上,并且从层叠方向俯视观察时,该伪导体层与所述外部电极中的折回到所述底面的部分的末端重叠, 所述伪导体层的厚度比所述电容器导体层的厚度大。 An electronic component comprising: a rectangular parallelepiped-shaped laminate comprising a laminate made of a plurality of dielectric layers, the stacking direction and having two ends and mutually opposed upper and bottom surfaces, and opposed to each other the two side surfaces, two end faces and mutually opposed; capacitor conductor layer disposed on said dielectric layer and forming a capacitor; external electrode covering the end surface, said upper surface and folded back and the bottom surface ; and a dummy conductor layer, which is disposed when located on the plurality of capacitors are provided over the dielectric layer conductor closer to the position of the bottom surface of the dielectric layer, and a plan viewed from the lamination direction, the dummy conductor the outer layer and folded back to the bottom surface of the electrode end portion of the overlap, the thickness of the dummy conductor layer is larger than the thickness of the conductive layer of the capacitor.
2.根据权利要求1所述的电子部件,其特征在于, 所述伪导体层的覆盖度在70 %以上且100 %以下。 2. The electronic component according to claim 1, wherein the dummy conductor layer coverage of 70% or more and 100% or less.
3.根据权利要求2所述的电子部件,其特征在于, 当从层叠方向俯视观察所述伪导体层时,覆盖度是从100%减去形成于该伪导体层的空孔的面积相对于该伪导体层的面积的比例的值。 The electronic component according to claim 2, wherein, when viewed from the stacking direction of the observation dummy conductor layer, coverage is formed by subtracting from 100% to the area of ​​the pores with respect to the dummy conductor layer value proportional to the area of ​​the dummy conductor layer.
4.根据权利要求1至3中任一项所述的电子部件,其特征在于, 所述伪导体层与所述外部电极连接。 An electronic component according to any one of claims 1 to 3, wherein the dummy conductor layer and the external electrode.
5.根据权利要求1至3中任一项所述的电子部件,其特征在于, 所述伪导体层不与所述外部电极连接。 An electronic component according to any one of claims 1 to 3, wherein the dummy conductor layer is not connected to the external electrode.
6.根据权利要求1至3中任一项所述的电子部件,其特征在于, 所述外部电极折回到两个所述侧面。 An electronic component according to any one of claims 1-3, wherein said external electrodes of said two sides folded back.
7.根据权利要求4所述的电子部件,其特征在于, 所述外部电极折回到两个所述侧面。 7. The electronic component as claimed in claim 4, wherein said external electrodes of said two sides folded back.
8.根据权利要求5所述的电子部件,其特征在于, 所述外部电极折回到两个所述侧面。 The electronic component as claimed in claim 5, wherein said external electrodes of said two sides folded back.
CN 201220540807 2011-10-24 2012-10-22 Electronic part CN202855551U (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011233106A JP5482763B2 (en) 2011-10-24 2011-10-24 Electronic Components
JP2011-233106 2011-10-24

Publications (1)

Publication Number Publication Date
CN202855551U true CN202855551U (en) 2013-04-03

Family

ID=47986722

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 201220540807 CN202855551U (en) 2011-10-24 2012-10-22 Electronic part

Country Status (2)

Country Link
JP (1) JP5482763B2 (en)
CN (1) CN202855551U (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130104338A (en) * 2012-03-13 2013-09-25 삼성전기주식회사 Multi-layered ceramic electronic component and manufacturing method of the same
US9378891B2 (en) * 2012-12-13 2016-06-28 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic device
JP2014165492A (en) * 2013-02-26 2014-09-08 Samsung Electro-Mechanics Co Ltd Multilayer ceramic device
KR101994710B1 (en) * 2013-04-18 2019-07-01 삼성전기주식회사 Multilayer ceramic capacitor
KR101504015B1 (en) * 2013-07-09 2015-03-18 삼성전기주식회사 Multi-layered ceramic capacitor and mounting circuit board thereof
KR101525666B1 (en) 2013-07-11 2015-06-03 삼성전기주식회사 Multi-layered ceramic capacitor and manufacturing method the same
KR101565651B1 (en) 2013-10-08 2015-11-03 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
US20150310991A1 (en) * 2014-04-29 2015-10-29 Apple Inc. Multi-layered ceramic capacitors
KR20150125335A (en) 2014-04-30 2015-11-09 삼성전기주식회사 Multi-layered ceramic electronic component
KR20150132972A (en) 2014-05-19 2015-11-27 삼성전기주식회사 Multi-layered ceramic electronic component and board having the same mounted thereon
KR101598297B1 (en) * 2014-10-06 2016-02-26 삼성전기주식회사 Multi-layered ceramic electronic component and mounting circuit thereof
KR101630068B1 (en) 2014-10-06 2016-06-13 삼성전기주식회사 Multi-layered ceramic electronic component and mounting circuit thereof
KR20160044338A (en) 2014-10-15 2016-04-25 삼성전기주식회사 Chip component
KR20160099881A (en) 2015-02-13 2016-08-23 삼성전기주식회사 Multi-layered ceramic electronic part and board having the same
KR20160099880A (en) 2015-02-13 2016-08-23 삼성전기주식회사 Multi-layered ceramic electronic part and board having the same
KR101933416B1 (en) 2016-12-22 2019-04-05 삼성전기 주식회사 Capacitor Component
JP2018198326A (en) * 2018-08-21 2018-12-13 太陽誘電株式会社 Multilayer capacitor
JP2018198327A (en) * 2018-08-21 2018-12-13 太陽誘電株式会社 Multilayer capacitor and method of manufacturing the same

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000353636A (en) * 1999-04-06 2000-12-19 Matsushita Electric Ind Co Ltd Laminated ceramic part
JP2002015941A (en) * 2000-06-28 2002-01-18 Matsushita Electric Ind Co Ltd Chip-type electronic component
JP2005167290A (en) * 2005-03-11 2005-06-23 Murata Mfg Co Ltd Method of manufacturing laminated ceramic electronic component
JP2011151224A (en) * 2010-01-22 2011-08-04 Murata Mfg Co Ltd Laminated ceramic capacitor, and method of manufacturing the same

Also Published As

Publication number Publication date
JP2013093374A (en) 2013-05-16
JP5482763B2 (en) 2014-05-07

Similar Documents

Publication Publication Date Title
JP5884653B2 (en) Mounting structure
JP5777302B2 (en) Method for manufacturing ceramic electronic component, ceramic electronic component and wiring board
JP4929487B2 (en) Multilayer ceramic electronic components
KR101173420B1 (en) Ceramic electronic component
CN102610388A (en) Ceramic electronic component
TW201205612A (en) Capacitor and method for manufacturing the same
EP2819134A3 (en) Laminated chip electronic component, board for mounting the same, and packing unit thereof
CN102394174A (en) The ceramic electronic component
CN1832069A (en) Multi-terminal type laminated capacitor and manufacturing method thereof
CN102005297B (en) Ceramic electronic component and method for producing same
JP2003031435A (en) Laminated ceramic electronic component with multiple terminals
JP5699819B2 (en) Ceramic electronic components
JP6439551B2 (en) Multilayer ceramic capacitor
KR101141402B1 (en) A multilayer ceramic capacitor and a method for manufactuaring the same
JP2006186316A (en) Ceramic electronic component and laminated ceramic capacitor
US8773839B2 (en) Multilayer ceramic electronic component
JP5998724B2 (en) Multilayer ceramic capacitor
CN102683015A (en) Multilayer ceramic capacitor and method of manufacturing the same
JP2012253338A (en) Multilayer ceramic electronic component
JP2012004480A (en) Method for manufacturing electronic component and electronic component
CN102347315B (en) Ceramic electronic component and wiring board
KR20130024530A (en) Ceramic electronic component and method for manufacturing the same
US20100202098A1 (en) Ceramic electronic part
JP5271377B2 (en) Multilayer ceramic capacitor
TWI541846B (en) Multilayer ceramic capacitor

Legal Events

Date Code Title Description
C14 Granted