CN202617075U - High-frequency phase shifting signal generating circuit based on programmable ECL (Emitter Coupled Logic) logic device - Google Patents

High-frequency phase shifting signal generating circuit based on programmable ECL (Emitter Coupled Logic) logic device Download PDF

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CN202617075U
CN202617075U CN 201220203695 CN201220203695U CN202617075U CN 202617075 U CN202617075 U CN 202617075U CN 201220203695 CN201220203695 CN 201220203695 CN 201220203695 U CN201220203695 U CN 201220203695U CN 202617075 U CN202617075 U CN 202617075U
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frequency
electric capacity
pin
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许素安
陈乐�
孙坚
钟绍俊
富雅琼
黄艳岩
谢敏
徐红伟
何京徽
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China Jiliang University
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China Jiliang University
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Abstract

The utility model discloses a kind of high-frequency phase shift signal generating circuits based on programmable ECL logical device. Existing HF signal generator is expensive and hardware circuit is complicated. The utility model includes quick comparator, PLL frequency multiplier, ECL signal clock distributor, pulse suppressor, the first digital frequency divider and the second digital frequency divider. External timing signal is converted square-wave signal by quick comparator, PLL may be programmed frequency multiplier for the square wave signal frequency multiplication, ECL signal clock distributor distributes the frequency-doubled signal to two-way, frequency-doubled signal is directly divided via the first digital frequency divider all the way, another way frequency-doubled signal is inhibited after the phase shift of 2 π by pulse suppressor by the second digital frequency divider, and the frequency dividing multiple of the first digital frequency divider and the second digital frequency divider is
Figure DEST_PATH_IMAGE002
, the output signal of the first digital frequency divider has with respect to the output signal of the second digital frequency divider
Figure DEST_PATH_IMAGE004
Phase shift. The utility model circuit design principle is simple, and reproducibility is strong.

Description

A kind of high-frequency phase shift signal generating circuit based on programmable ECL logical devices
Technical field
The utility model is related to a kind of high-frequency phase shift signal generating circuit, and in particular to a kind of high-frequency phase shift signal generating circuit based on programmable ECL logical devices.
Background technology
With the development of electronic technology, high-frequency phase shift signal is more and more extensive in the application of precision engineering, electronics, biomedicine, communication science research, existing common HF signal generator often shows as jitter, or precision is not high, and high-performance high-frequency signal generator is expensive, for general user and non-best choice.
Circuit occur for traditional phase shift signalling constitute address generator using phaselocked loop and counter to realize in different pieces of information memory data of going down, the phase shift of signal is realized by the storage location of change data, this method output is flexible, but it is due to the limitation of phase-lock-ring output frequency, it is suitable for below 1MHz low frequency signal application field, and constituting the easy circuit structure out of hand and relative complex of the pith counter of phaselocked loop is difficult to ensure that the reliability of whole circuit.The HF signal generator based on direct digital synthesizer DDS technology developed in recent years, can realize that frequency is exported in more than 40MHz phase shift signalling, phase shift resolution ratio can reach 0.01 °, but such product does not provide phase shift unstability index.In addition, such HF signal generator is external product monopolization, it is expensive, and hardware circuit is complicated, volume is larger, not portable.Therefore independent development is portable, high stable, low signal-to-noise ratio, the high-frequency phase shift signal generator of low cost have important technical innovation value.
The notification number of Chinese invention patent bulletin is a kind of CN102055428A digital phase shifter of patent disclosure, and the frequency domain of such phase shifter is wide, can be 6~18GHz, manufacturing process is easy, and high yield rate, Phase shift precision is high, can phase shift step value be confined to 11.25 °.The notification number of Chinese invention patent bulletin is a kind of CN101355350A phase-shift circuit of patent disclosure, and such phase-shift circuit has a characteristic of low intrinsic delay, can announce in do not refer to frequency domain.
The content of the invention
The purpose of this utility model be provide that a kind of circuit topological structure based on programmable ECL logical devices is simple, frequency domain is wide, the high-frequency phase shift circuit that signal stabilization, small phase noise, low cost, circuit area are small.
The utility model technical solution adopted for solving the technical problem：
The utility model includes quick comparator, PLL frequency multipliers, ECL signal clocks distributor, pulse suppressor, the first digital frequency divider and the second digital frequency divider.External timing signal is converted into square-wave signal by quick comparator, PLL may be programmed frequency multiplier by the square wave signal frequency multiplication, ECL signal clocks distributor distributes the frequency-doubled signal to two-way, frequency-doubled signal is directly divided via the first digital frequency divider all the way, and another road frequency-doubled signal is divided after suppressing 2 π phase shift by pulse suppressor by the second digital frequency divider.
The beneficial effects of the utility model are：1st, circuit design principle is simple, and reproducibility is strong；2nd, circuit small volume；3rd, phase shift signalling noise is small；4th, phase shift signalling is stable；5th, Phase shift precision is high；6th, strong antijamming capability；7th, low cost.
Brief description of the drawings
Fig. 1 is that circuit phase shift generation schematic diagram occurs for the utility model high-frequency phase shift.
Fig. 2 is the structural representation that circuit occurs for the utility model high-frequency phase shift.
Fig. 3 is that the utility model pulse suppression ripple produces principle schematic.
Fig. 4 is the circuit theory diagrams that comparator in circuit occurs for the utility model high-frequency phase shift.
Fig. 5 is the circuit theory diagrams that PLL frequency multipliers in circuit occur for the utility model high-frequency phase shift.
Fig. 6 is the circuit theory diagrams that ECL signal clock distributors in circuit occur for the utility model high-frequency phase shift.
Fig. 7 be the utility model high-frequency phase shift occur circuit in TTL signal to ECL signal adapters circuit theory diagrams.
Fig. 8 is the circuit theory diagrams that synchronizer trigger in circuit occurs for the utility model high-frequency phase shift.
Fig. 9 is the circuit theory diagrams that the first delayer and the second delayer in circuit occur for the utility model high-frequency phase shift.
Figure 10 is the circuit theory diagrams that XOR gate in circuit occurs for the utility model high-frequency phase shift.
Figure 11 is the circuit theory diagrams that the 3rd delayer in circuit occurs for the utility model high-frequency phase shift.
Figure 12 is the circuit theory diagrams that the first frequency divider and the second frequency divider in circuit occur for the utility model high-frequency phase shift.
Figure 13 is the utility model embodiment stable output signal test experiments result figure.
Embodiment
The utility model is further illustrated below in conjunction with accompanying drawing.
The utility model includes quick comparator, PLL frequency multipliers, ECL signal clocks distributor, pulse suppressor, frequency divider.Quick comparator is inverted for square-wave signal by external timing signal, PLL may be programmed frequency multiplier by the square wave signal frequency multiplication, ECL signal clocks distributor distributes the frequency-doubled signal to two-way, is directly divided via digital frequency divider 1 all the way, and another road frequency-doubled signal suppresses a pulse by pulse suppressor（Corresponding phase shift is 2 π）Divided afterwards by digital frequency divider 2, the frequency dividing multiple of digital frequency divider 1 and digital frequency divider 2 is
Figure 201220203695X100002DEST_PATH_IMAGE002
（P is integer）, then the output signal of digital frequency divider 1 have with respect to the output signal of digital frequency divider 2
Figure 201220203695X100002DEST_PATH_IMAGE004
Phase shift；Phase shift principle figure is as shown in figure 1, frequency isf HFHigh frequency digital logic ECL signals, a pulse is suppressed with ECL logical devices, then the phase shift that should mutually have 2 π is produced, and after the signal two divided-frequency, phase-shift phase is π, is because ECL signal frequencies can be dividedTimes, then it is in frequency
Figure 201220203695X100002DEST_PATH_IMAGE008
Signal at there is the value to be
Figure DEST_PATH_IMAGE010
Phase shift signalling produce.
As shown in Figure 2.External clock source signal SCLKSquare-wave signal is converted into through quick comparator, PLL frequency multipliers are by the square wave signal frequency multiplication, if frequency multiplication multiple is N, then the output signal frequency of frequency multiplier isf HF（
Figure DEST_PATH_IMAGE012
）The frequency-doubled signal is distributed to two-way by ECL signal clock distributors, ECL frequency-doubled signals are directly distributed to frequency divider 1 all the way, the output signal of frequency divider 1 is S1, another road ECL frequency-doubled signals are distributed to pulse suppressor, and some pulse of pulse suppressor to the ECL frequency-doubled signals suppresses, and is sent by the ECL frequency-doubled signals after pulse suppression to frequency divider 2, the output signal of frequency divider 2 is S2, and the frequency dividing multiple of frequency divider 1 and frequency divider 2 is
Figure 589260DEST_PATH_IMAGE002
, then signal S2 relative signals S1 phase-shift phase be
Figure DEST_PATH_IMAGE014
, signal S1 and signal S2 frequency is
Figure DEST_PATH_IMAGE016
。
With reference to Fig. 2 and Fig. 3, pulse suppressor of the present utility model is made up of TTL to ECL signaling conversion circuits, synchronizer trigger, delayer 1, delayer 2, NOR gate circuit, delayer 3.
It is pulse suppressor structured flowchart in dotted line frame in Fig. 2, pulse suppression triggers the inverted circuit conversion of TTL signal into ECL signals, and the ECL signals are via synchronizer trigger and PLL frequency-doubled signals SHFIt is synchronous.With frequency-doubled signal SHFSynchronous ECL signals are sent to delayer 1 and delayer 2, the postpones signal S that the output amount of delay of delayer 1 is t1 simultaneouslyt1, the postpones signal S that the output amount of delay of delayer 2 is t2t2, its waveform is as shown in figure 3, signal St1With signal St2Via XOR gate XOR, XOR gate is output as pulse suppression signal, and the pulse width of the pulse suppression signal is equal to frequency-doubled signalS HFCycle, i.e.,
Figure DEST_PATH_IMAGE018
.As shown in figure 3, the edge of outer triggering signal triggers a pulsewidth and is every timeT HFSuppression signal, the suppression signal suppresses frequency-doubled signal by delayer 3S HF, so as to realize 2 π phase shift.
The schematic diagram of quick comparator can be found in shown in Fig. 4, including the first electric capacity C1, the second electric capacity C2, quick comparator AD8598.Comparator AD8598 input pin INA- connection external clock source signals Sclk；Comparator AD8598 input pin INA+, INB+, INB-, GND, V- ground connection, comparator AD8598 output pin QA output signals Sa；Comparator AD8598 pin V+, the first electric capacity C1 one end, the second electric capacity C2 one end are connected with 5V；The other end of first electric capacity, the other end of the second electric capacity are grounded；Comparator AD8598 remaining pin is hanging.
First electric capacity C1 capacitances are that 100nF, the second electric capacity C2 capacitances are that 10nF plays power supply filter action in high-frequency circuit.
The schematic diagram of PLL frequency multipliers can be found in shown in Fig. 5, including first resistor R1, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6.
Frequency multiplier MC12349 input pin PREF_EXT connection comparators AD8598 output signal Sa;Frequency multiplier MC12349 output pin FOUT,
Figure DEST_PATH_IMAGE020
Difference output signal Sb and signal
Figure DEST_PATH_IMAGE022
；Frequency multiplier MC12349 pin S_CLOCK, S_DATA, S_LOAD, PWR-DOWN, GND ground connection；Frequency multiplier MC12349 pin OE,
Figure DEST_PATH_IMAGE024
It is connected with the 3rd electric capacity C3 one end with+5V；Frequency multiplier MC12349 pin Vcc and the 4th electric capacity C4 one end are connected with 5V；Frequency multiplier MC12349 pin PLL-Vcc and first resistor R1 one end, the 5th electric capacity C5, the 6th electric capacity C6 one end connection；Frequency multiplier MC12349 pin N [1], N [0], M [6], M [5], M [4], M [3], M [2], M [1], M [0] are connected with switching SWITCH 11,2,3,4,5,6,7,8,9 terminal respectively；Frequency multiplier MC12349 pin XTAL1, XTAL2, NC, XTAL_SEL, TEST is hanging；Switch SWITCH-1 10,11,12,13,14,15,16,17,18 terminal ground；3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6 other end ground connection, first resistor R1 another termination+5V.
3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5 capacitance are 10nF, the 6th electric capacity C6 value strobes in circuit for 22nF, and the value of first resistor plays a part of to maintain frequency multiplier MC12349 pins PLL_Vcc voltage in circuit for 15 Ω.
PLL frequency multipliers MC12439 output frequency is adjustable.The scope of frequency multiplier MC12349 output frequency is 50 to 800MHz, and incoming frequency scope is 10 to 20MHz, output frequency FOUTWith incoming frequency FXTALRelation be
Figure DEST_PATH_IMAGE026
, M and N value can change by changing the value of connecting valve.
The schematic diagram of ECL clock distributors can be found in shown in Fig. 6, including the 7th electric capacity C7, the 8th electric capacity C8, second resistance R2,3rd resistor R3, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7, the 8th resistance R8, the 9th resistance R9, clock distributor MC10EL15.Clock distributor MC10EL15 input pin CLK connection input signal Sb and the 6th resistance R6, the 7th resistance R7 one end；Clock distributor MC10EL15 input pin
Figure DEST_PATH_IMAGE028
Connect input signal
Figure DEST_PATH_IMAGE030
With the 8th resistance R8, the 9th resistance R9 one end；Clock distributor MC10EL15 pin, SCLK, SEL, VEE ground connection；Clock distributor MC10EL15 pin Vcc connects+5V and the 7th electric capacity C7, the 8th electric capacity C8 one end；Clock distributor MC10EL15 output pin Q1 meets output signal Sc, output pin Q2 and connects output signal Sd, output pin
Figure DEST_PATH_IMAGE034
Connect output signal, output pin Q3 meet output signal Se；Clock distributor MC10EL15 output pin
Figure DEST_PATH_IMAGE038
Connect second resistance R2,3rd resistor R3 one end；MC10EL15 output pin
Figure DEST_PATH_IMAGE040
Connect the 4th resistance R4, the 5th resistance R5 one end；3rd resistor R3, the 5th resistance R5, the 7th resistance R7, the 9th resistance R9, the 7th electric capacity C7, the 8th electric capacity C8 other end ground connection；Second resistance R2, the 4th resistance R4, the 6th resistance R6, the 8th resistance R8 another termination+5V；Clock distributor MC10EL15 pin Q0,
Figure DEST_PATH_IMAGE042
, VBB it is hanging.
7th electric capacity C7 capacitances are that 10nF, the 8th electric capacity C8 capacitances are that 100nF plays power supply filter action in high-frequency circuit；Second resistance R2, the 4th resistance R4, the 6th resistance R6, the 8th resistance R8 resistance are 86 Ω, 3rd resistor R3, the 5th resistance R5, the 7th resistance R7, the 9th resistance R9 resistance and are 118 Ω, the dc-couple needs for being chosen for meeting the input of PECL signals and output of these resistance values.
The schematic diagram of TTL-ECL signal adapters can be found in shown in Fig. 7, including the 9th electric capacity C9, the tenth electric capacity C10, the tenth resistance R10, the 11st resistance R11, signal adapter MC10ELT20.Signal adapter MC10ELT20 input pin D0 connections input signal Scomm, input signal Scomm is external trigger TTL signal；Signal adapter MC10ELT20 output pin Q connection output signals Sf；Signal adapter MC10ELT20 output pin
Figure DEST_PATH_IMAGE044
Connect the tenth resistance R10 one end, the 11st resistance R11 one end；Signal adapter MC10ELT20 pin VCC connection power supplys+5V, the 9th electric capacity C9 one end, the tenth electric capacity C10 one end；Signal adapter MC10ELT20 pin GND ground connection；Signal adapter MC10ELT20 remaining pin is hanging；Tenth resistance R10 another termination+5V, the 11st resistance R11 other end ground connection, the 9th electric capacity C9 other end, the tenth electric capacity C10 other end ground connection.
9th electric capacity C9 capacitance is that 10nF, the tenth electric capacity C10 capacitance are that 100nF plays power supply filter action in high-frequency circuit；Tenth resistance R10 resistance is that 86 Ω, the 11st resistance R11 resistance are 118 Ω, the dc-couple needs for being chosen for meeting the input of PECL signals and output of these resistance values.
The schematic diagram of synchronizer trigger is as shown in figure 8, including the 11st electric capacity C11, the 12nd electric capacity C12, the 12nd resistance R12, the 13rd resistance R13, the 14th resistance R14, the 15th resistance R15, synchronizer trigger MC10EP31.Synchronizer trigger MC10EP31 input pin CLK meets input signal Sc（Signal Sc is signal distributor MC10EL15 output signal）, the 14th resistance R14 one end, the 15th resistance R15 one end；Synchronizer trigger MC10EP31 input pin D meets input signal Sf（Signal Sf is signal adapter MC10ELT20 output signal）, the 12nd resistance R12 one end, the 13rd resistance R13 one end；Synchronizer trigger MC10EP31 pin
Figure 755668DEST_PATH_IMAGE044
Connect output signal；Synchronizer trigger MC10EP31 pin Q connection output signals Sg；The synchronizer trigger MC10EP31 electric capacity C11 of pin VCC connections the 11st one end, the 12nd electric capacity C12 one end；Synchronizer trigger MC10EP31 pin VEE, RST, SET ground connection.
11st electric capacity C11 capacitances are that 10nF, the 12nd electric capacity C12 capacitances are that 100nF plays power supply filter action in high-frequency circuit；12nd resistance R12, the 14th resistance R14 resistance are 86 Ω, the 13rd resistance R13, the 15th resistance R15 resistance and are 118 Ω, the dc-couple needs for being chosen for meeting the input of PECL signals and output of these resistance values.
Delayer circuit theory diagrams can be found in shown in Fig. 9, including the 13rd electric capacity C13, the 14th electric capacity C14, the 15th electric capacity C15, the 16th electric capacity C16, the 16th resistance R16, the 17th resistance R17, the 18th resistance R18, the 19th resistance R19, the 20th resistance R20, the 21st resistance R21, the 22nd resistance R22, the 23rd resistance R23, the first delayer MC10EP195-1, the second delayer MC10EP195-2.
First delayer MC10EP195-1 pin IN connection input signals Sg, the 17th resistance R17 one end, the 16th resistance R16 one end；First delayer MC10EP195-1 pin
Figure DEST_PATH_IMAGE048
Connect input signal
Figure 597722DEST_PATH_IMAGE046
, the 18th resistance R18 one end, the 19th resistance R19 one end；First delayer MC10EP195-1 output pin
Figure 992932DEST_PATH_IMAGE044
Connect output signal
Figure DEST_PATH_IMAGE050
；First delayer MC10EP195-1 output pin Q connection output signals Sh；First delayer MC10EP195-1 pin VCC connections+5V, the 13rd electric capacity C13 one end, the 14th electric capacity C14 one end；First delayer MC10EP195-1 pin SETMAX, SETMIN, LEN, VEE ground connection；First delayer MC10EP195-1 pin VCF and pin VEF short circuits, the first delayer MC10EP195-1 pin D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 connect switch SWITCH-2 pin 18,17,16,15,14,13,12,11,10 and switch SWITCH-3 pin 4 and 3 respectively；First delayer MC10EP195-1 remaining pin is hanging.
The 16th resistance R16 other end, the 17th resistance R18 another termination+5V；The 17th resistance R17 other end, the 19th resistance R19 other end ground connection；The 13rd electric capacity C13 other end, the 14th electric capacity C14 other end ground connection；The pin 1,2,3,4,5,6,7,8,9 for switching SWITCH-2 and the pin 1 and 2 for switching SWITCH-3 meet+5V.
Second delayer MC10EP195-2 pin IN connection input signals Sg, the 21st resistance R21 one end, the 20th resistance R20 one end；Second delayer MC10EP195-2 pin
Figure 430473DEST_PATH_IMAGE048
Connect input signal
Figure 252935DEST_PATH_IMAGE046
, the 22nd resistance R22 one end, the 23rd resistance R23 one end；Second delayer MC10EP195-2 output pin
Figure 706919DEST_PATH_IMAGE044
Connect output signal
Figure DEST_PATH_IMAGE052
；Second delayer MC10EP195-2 output pin Q connection output signals Si；Second delayer MC10EP195-2 pin VCC connections+5V, the 15th electric capacity C15 one end, the 16th electric capacity C16 one end；Second delayer MC10EP195-2 pin SETMAX, SETMIN, LEN, VEE ground connection；Second delayer MC10EP195-1 pin VCF and pin VEF short circuits, the second delayer MC10EP195-2 pin D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 connect switch SWITCH-4 pin 18,17,16,15,14,13,12,11,10 and switch SWITCH-5 pin 4 and 3 respectively；Second delayer MC10EP195-2 remaining pin is hanging.
The 20th resistance R20 other end, the 21st resistance R21 another termination+5V；The 22nd resistance R22 other end, the 23rd resistance R23 other end ground connection；The 15th electric capacity C15 other end, the 16th electric capacity C16 other end ground connection；The pin 1,2,3,4,5,6,7,8,9 for switching SWITCH-4 and the pin 1 and 2 for switching SWITCH-5 meet+5V.
13rd electric capacity C13, the 15th electric capacity C15 capacitance are 10nF, the 14th electric capacity C14, the 16th electric capacity C16 capacitance and are 100nF and power supply filter action is played in high-frequency circuit；12nd resistance R12, the 14th resistance R14 resistance are 86 Ω, the 17th resistance R17, the 19th resistance R19, the 21st resistance R21, the 23rd resistance R23 resistance and are 118 Ω, the dc-couple needs for being chosen for meeting the input of PECL signals and output of these resistance values.
NOR gate circuit schematic diagram is as shown in Figure 10, including the 24th resistance R24, the 25th resistance R25, the 26th resistance R26, the 27th resistance R27, the 28th resistance R28, the 29th resistance R29, the 30th resistance R30, the 31st resistance R31, the 32nd resistance R32, the 33rd resistance R23, the 17th electric capacity C17, the 18th electric capacity C18, XOR gate MC10EP08.XOR gate MC10EP08 input pin
Figure DEST_PATH_IMAGE054
Connect input signal
Figure 469601DEST_PATH_IMAGE050
, the 24th resistance R24 one end, the 25th resistance R25 one end；XOR gate MC10EP08 input pin D1 connection input signals Sh, the 26th resistance R26 one end, the 27th resistance R27 one end；XOR gate MC10EP08 input pinConnect input signal
Figure 325431DEST_PATH_IMAGE052
, the 26th resistance R28 one end, the 27th resistance R29 one end；XOR gate MC10EP08 input pin D0 connections input signal Si, the 30th resistance R30 one end, the 31st resistance R31 one end；XOR gate MC10EP08 pin VCC connects+5V, the 17th electric capacity C17 one end, the 18th electric capacity C18 one end；XOR gate MC10EP08 pin VEE ground connection；XOR gate MC10EP08 output pin
Figure 256477DEST_PATH_IMAGE044
Connect the 32nd resistance R32 one end, the 33rd resistance R33 one end；XOR gate MC10EP08 output pin Q connection output signals Sj.
The 17th electric capacity C17 other end, the 18th electric capacity C18 other end ground connection；The 24th resistance R24 other end, the 26th resistance R26 other end, the 28th resistance R28 other end, the 30th resistance R30, the 32nd resistance R32 another termination+5V；The 25th resistance R25 other end, the 27th resistance R27 other end, the 29th resistance R29 other end, the 31st resistance R31 other end ground connection.
17th electric capacity C17 capacitance is 10nF, the 18th electric capacity C18 capacitance plays power supply filter action for 100nF in high-frequency circuit；24th resistance R24, the 26th resistance R26, the 28th resistance R28, the 30th resistance R30 resistance are 86 Ω, the 25th resistance R25, the 27th resistance R27, the 29th resistance R29, the 31st resistance R31 resistance and are 118 Ω, the dc-couple needs for being chosen for meeting the input of PECL signals and output of these resistance values.
Realize that the pulse suppression schematic diagram of frequency-doubled signal is as shown in figure 11 by delayer 3, including the 18th electric capacity C18, the 19th electric capacity C19, the 34th resistance R34, the 35th resistance R35, the 36th resistance R36, the 37th resistance R37, the 38th resistance R38, the 39th resistance R39, the 3rd delayer MC10EP195-3.
3rd delayer MC10EP195-3 pin
Figure 696293DEST_PATH_IMAGE048
Connect input signal, one end of the 34th resistance R34, the 35th resistance R35 one end；3rd delayer MC10EP195-3 pin IN connection input signals Sd, the 36th resistance R36 one end, the 37th resistance R37 one end；3rd delayer MC10EP195-3 output pin
Figure 81324DEST_PATH_IMAGE044
Connect the 38th resistance R38 one end, the 39th resistance R39 one end；3rd delayer MC10EP195-3 output pin Q connection output signals Sk；3rd delayer MC10EP195-3 pin VCC connections+5V, the 19th electric capacity C19 one end, the 20th electric capacity C20 one end；3rd delayer MC10EP195-3 pin SETMAX, SETMIN, LEN, VEE ground connection；3rd delayer MC10EP195-3 pin VCF and pin VEF short circuits, the 3rd delayer C10EP195-3 pin D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10 are grounded；Device MC10EP195-3 remaining pin is hanging during the 3rd delay.
The other end of 34th resistance R34, the 36th resistance R36 other end, the 38th resistance R38 another termination+5V；The 35th resistance R35 other end, the 37th resistance R37 other end, the 39th resistance R39 other end ground connection；The 19th electric capacity C19 other end, the 20th electric capacity C20 other end ground connection.
19th electric capacity C19 capacitance is 10nF, the 20th electric capacity C20 capacitance is 100nF and power supply filter action is played in high-frequency circuit；34th resistance R34, the 36th resistance R36, the 38th resistance R38 resistance are 86 Ω, the 35th resistance R35, the 37th resistance R37, the 39th resistance R39 resistance and are 118 Ω, the dc-couple needs for being chosen for meeting the input of PECL signals and output of these resistance values.
3rd delayer MC10EP195-3 is different from the first delayer MC10EP195-1 and the second delayer MC10EP195-2 delay function, and D0~D10 ends of the 3rd delayer are grounded, and time delay is 0, and its specific function is pulse-triggered, and its course of work is：The high-frequency signal Sd/ that XOR signal Sj is exported with frequency-doubled signal device
Figure 448851DEST_PATH_IMAGE036
Send simultaneously to the 3rd delayer MC10EP195-3, MC10EP195-3 Enable Pin connection XOR signal Sj, input connects frequency multiplier output signal, its characteristic is when enabling termination high level, MC10EP195-3 is output as low level, when Enable Pin is low level, output signal is input signal, because the pulsewidth of XOR signal is a high-frequency signal cycle（High level lasting time is a high-frequency signal cycle）, therefore the 3rd delayer is output as the high-frequency signal after a pulse suppression.
The schematic diagram of frequency divider can be found in shown in Figure 12, including the 21st electric capacity C21, 22nd electric capacity C22, 23rd electric capacity C23, 24th electric capacity C24, 25th electric capacity C25, 26th electric capacity C26, 27th electric capacity C27, 28th electric capacity C28, 29th electric capacity C29, 30th electric capacity C30, 40th resistance R40, 41st resistance R41, 42nd resistance R42, 43rd resistance R43, 44th resistance R44, 45th resistance R45, 46th resistance R46, 47th resistance R47, 48th resistance R48, 49th resistance R49, first digital frequency divider SP8402-1, second digital frequency divider SP8402-2.
First digital frequency divider SP8402-1 two input pin CLKIN short circuits and connection input signal Sk, the 40th resistance R40 one end, the 41st resistance R41 one end；First digital frequency divider SP8402-1 two input pins
Figure DEST_PATH_IMAGE058
Short circuit and the 21st electric capacity C21 of connection one end, the 22nd electric capacity C22 one end；First digital frequency divider SP8402-1 output pinConnect the 42nd resistance R42 one end；The first digital frequency divider SP8402-1 electric capacity C25 of output pin OUTPUT connections the 25th one end, the 43rd resistance R43 one end；First digital frequency divider SP8402-1 pin VCC is all connected with+5V, the 23rd electric capacity C23 one end, the 24th electric capacity C24 one end；First digital frequency divider SP8402-1 pin GND ground connection；First digital frequency divider SP8402-1 pin S0, S1, S2 difference connecting valve SWITCH-6 3,2,1 pin；The 21st electric capacity C21 other end, the 22nd electric capacity C22 other end, the 23rd electric capacity C23 other end, the 24th electric capacity C24 other end ground connection；40th resistance R40 other end connection+5V；Switch SWITCH-6 4,5,6 pins meet+5V；The 25th electric capacity C25 other end, a 44th resistance R44 termination output signal S1；The 41st resistance R41 other end, the 42nd resistance R42 other ends, the 43rd resistance R43 other ends, the 44th resistance R44 other end ground connection.
21st electric capacity C21, the 23rd electric capacity C23 capacitance are 10nF；22nd electric capacity C22, the 24th electric capacity C24 capacitance play power supply filter action for 100nF in high-frequency circuit；40th resistance R40 resistance is that 86 Ω, the 41st resistance R41 resistance are 118 Ω, and the 42nd resistance R42 resistance is that 330 Ω, the 43rd resistance R43 resistance are that 330 Ω, the resistance of the 44th resistance are 50 Ω；The dc-couple needs for being chosen for meeting the input of PECL signals and output of these resistance values.
Second digital frequency divider SP8402-2 two input pin CLKIN short circuits and connection input signal Se, the 45th resistance R45 one end, the 46th resistance R46 one end；Second digital frequency divider SP8402-2 two input pins
Figure 503526DEST_PATH_IMAGE058
Short circuit and the 26th electric capacity C26 of connection one end, the 27th electric capacity C27 one end；Second digital frequency divider SP8402-2 output pin
Figure 716332DEST_PATH_IMAGE060
Connect the 47th resistance R47 one end；The second digital frequency divider SP8402-2 electric capacity C30 of output pin OUTPUT connections the 30th one end, the 48th resistance R48 one end；Second digital frequency divider SP8402-2 pin VCC is all connected with+5V, the 28th electric capacity C28 one end, the 29th electric capacity C29 one end；Second digital frequency divider SP8402-2 pin GND ground connection；Second digital frequency divider SP8402-2 pin S0, S1, S2 difference connecting valve SWITCH-7 3,2,1 pin；The 26th electric capacity C26 other end, the 27th electric capacity C27 other end, the 28th electric capacity C28 other end, the 29th electric capacity C29 other end ground connection；45th resistance R45 other end connection+5V；Switch SWITCH-7 4,5,6 pins meet+5V；The 30th electric capacity C30 other end, a 49th resistance R49 termination output signal S2；The 46th resistance R46 other end, the 47th resistance R47 other end, the 48th resistance R48 other ends, the 49th resistance R49 other end ground connection.
26th electric capacity C26, the 28th electric capacity C28 capacitance are 10nF；27th electric capacity C27, the 29th electric capacity C29 capacitance play power supply filter action for 100nF in high-frequency circuit；45th resistance R45 resistance is that 86 Ω, the 46th resistance R46 resistance are 118 Ω, and the 47th resistance R47 resistance is that 330 Ω, the 48th resistance R48 resistance are that 330 Ω, the 49th resistance R49 resistance are 50 Ω；The dc-couple needs for being chosen for meeting the input of PECL signals and output of these resistance values.
The utility model is short using ECL signals rising edge and trailing edge time（
Figure DEST_PATH_IMAGE062
), working frequency it is big（）, the small advantage of phase noise and ECL PLD input/output signal programmable frequencies characteristic, the high-frequency phase shift circuit frequency domain of realization is wide, output signal frequency programming is adjustable, and stable output signal, phase-stepping value is adjustable and circuit area is small, low cost.
The rate-adaptive pacemaker scope of PLL frequency multipliers is 50 to 800MHz in the utility model high-frequency phase shift circuit（fHZ=50~800MHz）, the frequency dividing multiple of frequency divider is
Figure DEST_PATH_IMAGE066
(p=1~8), high-frequency phase shift occur circuit rate-adaptive pacemaker value be
Figure DEST_PATH_IMAGE068
, corresponding phase-stepping value is
Figure DEST_PATH_IMAGE070
, then the rate-adaptive pacemaker scope that circuit occurs for high-frequency phase shift is 0.2 ~ 400MHz, and achievable phase shift step value is respectively：
Figure DEST_PATH_IMAGE072
、
Figure DEST_PATH_IMAGE074
、
Figure DEST_PATH_IMAGE076
、
Figure DEST_PATH_IMAGE078
、
Figure DEST_PATH_IMAGE080
、
Figure DEST_PATH_IMAGE082
、
Figure DEST_PATH_IMAGE084
、
Figure DEST_PATH_IMAGE086
。
Embodiment of the present utility model is the phase-shift value that high-frequency phase shift circuit produces that step value is 2 π/32, and output frequency is 20MHz.External clock source signal Sclk frequency is 10MHz, and frequency multiplier frequency multiplication multiple is set to 64, then the high-frequency signal of frequency multiplier output is 640MHz；The time delay t1 of delayer 1 is 2200ps, and the time delay t2 of delayer 2 is 3760ps, then t2-t1=1560ps=1/640MHz, frequency dividing multiple is set to 1/32.Figure 13 is the test experiments result figure of the present embodiment.We test the stability that the 20MHz frequency signals that circuit is produced occur for phase shift.The acquisition time of signal frequency is about 12 hours, and the time of integration measured every time is 1s.After relative Alan's variance is carried out to experimental data and is calculated, draw the time of integration for 1s to 1000s, Alan's standard deviation square valueLess than 10-9.It may be said that it is insignificant that the swinging of signal of phase shift generation circuit is qualitative.

Claims (1)

1. a kind of high-frequency phase shift signal generating circuit based on programmable ECL logical devices, including quick comparator, PLL frequency multipliers, ECL signal clocks distributor, pulse suppressor, the first digital frequency divider and the second digital frequency divider, it is characterised in that：External timing signal is converted into square-wave signal by quick comparator, PLL may be programmed frequency multiplier by the square wave signal frequency multiplication, ECL signal clocks distributor distributes the frequency-doubled signal to two-way, frequency-doubled signal is directly divided via the first digital frequency divider all the way, and another road frequency-doubled signal is divided after suppressing 2 π phase shift by pulse suppressor by the second digital frequency divider.
CN 201220203695 2012-05-08 2012-05-08 High-frequency phase shifting signal generating circuit based on programmable ECL (Emitter Coupled Logic) logic device Expired - Fee Related CN202617075U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109634026A (en) * 2019-01-07 2019-04-16 中国科学院合肥物质科学研究院 A kind of implementation method of high speed optical shutter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109634026A (en) * 2019-01-07 2019-04-16 中国科学院合肥物质科学研究院 A kind of implementation method of high speed optical shutter

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