CN206517424U

CN206517424U - A kind of clock synchronization apparatus

Info

Publication number: CN206517424U
Application number: CN201720211832.7U
Authority: CN
Inventors: 卢铁
Original assignee: Nanjing Information Technology Co Ltd Butch
Current assignee: Nanjing Information Technology Co Ltd Butch
Priority date: 2017-03-06
Filing date: 2017-03-06
Publication date: 2017-09-22
Anticipated expiration: 2027-03-06

Abstract

The utility model discloses a kind of clock synchronization apparatus, aim to provide it is a kind of can be to the clock synchronization apparatus of signal synchronism output, its drip irrigation device is to include signal input part, signal output part, synchronous clock generator is connected between the signal input part and signal output part, believe code regeneration circuit, the synchronous clock generator utilizes external interrupt port generation synchronizing clock signals to receive the signal of signal input part, the letter code regeneration circuit switchs to input signal synchronous data signal to receive the signal and the synchronizing clock signals of signal input part.

Description

A kind of clock synchronization apparatus

Technical field

The utility model is related to a kind of clock synchronization apparatus.

Background technology

In the circuit system of digital communication, commonly using to clock synchronization apparatus, clock signal first was entering some After circuit, there are some time delays, easily cause the inconsistent of input signal and output signal clock, can digital communication system Effectively work, it is correctly synchronous dependent on originator and receiving end to a large extent.The bad of synchronization will cause communication The decline of quality, or even can not work completely.

Therefore, for clock synchronization apparatus, it is that stable clock signal is provided by clock crystal oscillator generally to set, but number Easily be interfered according in transmitting procedure, it is therefore desirable to design for circuit ensure that the stable of clock signal is transmitted, with Ensure that data input and output keep synchronous.

Utility model content

In view of the deficienciess of the prior art, be to provide can be to the clock of signal synchronism output for the purpose of this utility model Sychronisation.

Above-mentioned technical purpose of the present utility model technical scheme is that：A kind of clock is synchronously filled Put, including signal input part, signal output part, it is connected with synchronised clock between the signal input part and signal output part Device, letter code regeneration circuit, the synchronous clock generator are produced to receive the signal of signal input part using external interrupt port Raw synchronizing clock signals, the letter code regeneration circuit comes to receive the signal and the synchronizing clock signals of signal input part Input signal is switched to synchronous data signal.

By above-mentioned setting, synchronous data signal can be converted to by what data-signal was more stablized, by outside Interruptive port, determines the length of input signal code element, that is, the cycle information of extracted clock.When the trailing edge of external input signal is arrived When coming, synchronous clock generator produces interruption, performs clocking capability, until next trailing edge arrives, obtains a time value. So in the range of certain time, as long as external input signal is with the presence of " 101 " form, it is possible to it is determined that to be extracted clock Cycle；And ensure that extracted clock is synchronous with external input signal.When the rising edge of external input signal arrives（Or delay Certain time）, synchronous clock generator is to start to produce and export synchronised clock.

Can be preferably as concrete scheme of the present utility model：The data-signal of the signal input part is anti-by first Phase device input to synchronous clock generator first in the broken ends of fractured bone, the data-signal is defeated by the first phase inverter and the second phase inverter Enter to the broken ends of fractured bone in the second of synchronous clock generator and letter code regeneration circuit.

By above-mentioned setting, the stability of signal input can be improved, some noise jamming are removed.

Can be preferably as concrete scheme of the present utility model：The letter code regeneration circuit includes the first d type flip flop, the 2-D trigger, NOR gate circuit, the output end of first d type flip flop connect the output end of the second d type flip flop, the first D triggerings The output end of device and the output end of the second d type flip flop connection NOR gate circuit, NOR gate circuit connection signal output part.

By above-mentioned setting, data signal can be regenerated, relative input signal, the then data signal exported has same The information representation of step and signal stabilization is higher.

Can be preferably as concrete scheme of the present utility model：The synchronous clock generator includes single-chip microcomputer, clock Crystal oscillating circuit, the clock crystal oscillator circuit connects single-chip microcomputer to provide reference clock signal.

By above-mentioned setting, using the reference clock signal of clock crystal oscillator circuit with stable, single-chip microcomputer can be caused to need The reference clock wanted keeps stable, and can carry out outside with changing according to the demand of user, to use different size frequency Clock crystal oscillator circuit.

Can be preferably as concrete scheme of the present utility model：Reset circuit is additionally provided with the single-chip microcomputer, it is described Reset circuit is to produce reset signal to single-chip microcomputer.

By above-mentioned setting, in order to initialize to single-chip microcomputer in use, then need to enter by reset circuit Row external trigger reset signal is to single-chip microcomputer.

Can be preferably as concrete scheme of the present utility model：The reset circuit includes button, the 3rd capacitor, the One resistance, the button and first resistor series connection and both tie point offer reset signals, the 3rd capacitor are connected in parallel on On button.

By above-mentioned setting, reset signal is triggered by button so that single-chip microcomputer can be initialized, then carry out follow-up Work, the effect of the 3rd electric capacity can eliminate mechanical shaking of the button in trigger process, so that it is guaranteed that the stabilization of reset signal Input.

Can be preferably as concrete scheme of the present utility model：The synchronous clock generator is also connected by tongue tube Supply unit, the tongue tube connects power supply to induced magnetism.

By above-mentioned setting, the break-make of supply unit is controlled using tongue tube, so that this device is effectively switched Control, is controlled by way of magnetic induction, so as to avoid the touching of staff's hand, employs Untouched control, is risen To good protective effect.

In summary, the utility model has the advantages that：, can be by data-signal with stable signal output The synchronous clock signal of matching is carried out, stable data signal is exported, the function of data transfer is completed, convenient, user is controlled Just.

Brief description of the drawings

Fig. 1 is the structured flowchart of the present embodiment；

Fig. 2 is the signal waveforms of the present embodiment；

Fig. 3 is the circuit connection diagram of the present embodiment.

1, signal input part in figure；2nd, signal output part；3rd, synchronous clock generator；4th, code regeneration circuit is believed；U1, first Phase inverter；U2, the second phase inverter；U3, the first d type flip flop；U4, the second d type flip flop；U5, NOR gate circuit；U0, single-chip microcomputer； 31st, clock crystal oscillator circuit；32nd, reset circuit；AN1, button；C3, the 3rd capacitor；R1, first resistor；GH, tongue tube；5th, it is electric Source device.

Embodiment

The utility model is described in further detail below in conjunction with accompanying drawing.

Embodiment：A kind of clock synchronization apparatus, as shown in figure 1, including signal input part 1, signal output part 2, signal is defeated Enter to be connected with synchronous clock generator 3, letter code regeneration circuit 4 between end 1 and signal output part 2, synchronous clock generator 3 is used to The signal for receiving signal input part 1 produces synchronizing clock signals using external interrupt port, and letter code regeneration circuit 4 is to receive letter The signal and synchronizing clock signals of number input 1 switch to input signal synchronous data signal.

Physical circuit is as shown in figure 3, the data-signal of signal input part 1 inputs to synchronised clock by the first phase inverter U1 The broken ends of fractured bone in the first of generator 3, data-signal inputs to synchronised clock by the first phase inverter U1 and the second phase inverter U2 The broken ends of fractured bone and letter code regeneration circuit 4 in the second of device 3.Synchronous clock generator 3 includes single-chip microcomputer U0, clock crystal oscillator circuit 31, Clock crystal oscillator circuit 31 connects single-chip microcomputer U0 to provide reference clock signal.Single-chip microcomputer U0 can use model AT89C51, INT1 and INT2 are respectively two interrupting input end.RST is single-chip microcomputer U0 reset terminal.P1.4 is defeated for synchronizing clock signals Go out end, synchronizing clock signals are represented with TCLK.In figure 3, data-signal DATA is also inputted in addition to inputing to single-chip microcomputer U0 Give letter code regeneration circuit 4.

Believe that code regeneration circuit 4 includes the first d type flip flop U3, the second d type flip flop U4, NOR gate circuit U5, the first d type flip flop U3 the second d type flip flop U4 of output end connection output end, the first d type flip flop U3 output end and the second d type flip flop U4's is defeated Go out end connection NOR gate circuit U5, NOR gate circuit U5 connections signal output part 2.

Its middle port TP705, TP706, TP707, the detection port as signal can carry out display letter by oscillograph Number figure, as shown in Fig. 2 its signal detected is all different.Port TP705 is the data-signal of input, and it has Clutter, port TP706 is the synchronizing clock signals TCLK of output, and port TP707 is the data signal of corresponding output, and it is substantially The data content of carrying is consistent with input data signal content, but more stablizes.

Said structure can be converted to synchronous data signal by what data-signal was more stablized, pass through external interrupt end Mouthful, determine the length of input signal code element, that is, the cycle information of extracted clock.When the trailing edge of external input signal arrives When, synchronous clock generator 3 produces interruption, performs clocking capability, until next trailing edge arrives, obtains a time value. So in the range of certain time, as long as external input signal is with the presence of " 101 " form, it is possible to it is determined that to be extracted clock Cycle；And ensure that extracted clock is synchronous with external input signal.When the rising edge of external input signal arrives（Or delay Certain time）, synchronous clock generator 3 is to start to produce and export synchronised clock.

Data signal can be regenerated, relative input signal, the then data signal exported has synchronous information representation And signal stabilization is higher.

Stable reference clock signal is provided using clock crystal oscillator circuit 31, when can cause the benchmark of single-chip microcomputer U0 needs Clock keeps stable, and can carry out outside with changing according to the demand of user, to use the clock crystal oscillator of different size frequency Circuit 31.

In addition, as shown in figure 3, being additionally provided with reset circuit 32 on single-chip microcomputer U0, reset circuit 32 resets letter to produce Number give single-chip microcomputer U0.Reset circuit 32 includes button AN1, the 3rd capacitor C3, first resistor R1, button AN1 and first resistor R1 is connected and both tie points provide reset signal, and the 3rd capacitor C3 is connected in parallel on button AN1.

In order to which single-chip microcomputer U0 initialization can be given in use, then need to carry out external trigger by reset circuit 32 Reset signal gives single-chip microcomputer U0.Reset signal is triggered by button AN1 so that single-chip microcomputer U0 can be initialized, after then carrying out Continuous work, the effect of the 3rd electric capacity can eliminate mechanical shakings of the button AN1 in trigger process, so that it is guaranteed that reset signal Stable input.

Synchronous clock generator 3 is also by tongue tube GH connections supply unit 5, and tongue tube GH is connected to induced magnetism Power supply.Supply unit 5 can use switching power circuit or other batteries to power to provide circuit required voltage Vcc.The break-make of supply unit 5 is controlled using tongue tube GH, so that this device carries out effective switch control, passes through magnetic induction Mode be controlled, so as to avoid the touching of staff's hand, employ Untouched control, play well protection make With.

This specific embodiment is only to explain of the present utility model, and it is not to limitation of the present utility model, ability Field technique personnel can make the modification without creative contribution to the present embodiment as needed after this specification is read, but As long as all being protected in right of the present utility model by Patent Law.

Claims

1. a kind of clock synchronization apparatus, including signal input part (1), signal output part (2), it is characterised in that：The signal is defeated Enter to be connected with synchronous clock generator (3), letter code regeneration circuit (4) between end (1) and signal output part (2), when described synchronous Clock generator (3) utilizes external interrupt port generation synchronizing clock signals, the letter to receive the signal of signal input part (1) Code regeneration circuit (4) switchs to input signal to receive the signal and the synchronizing clock signals of signal input part (1) Synchronous data signal.

2. clock synchronization apparatus according to claim 1, it is characterised in that：The data-signal of the signal input part (1) The broken ends of fractured bone in the first of synchronous clock generator (3) is inputed to by the first phase inverter (U1), the data-signal is anti-by first Phase device (U1) and the second phase inverter (U2) input to synchronous clock generator (3) second in the broken ends of fractured bone and letter code regeneration circuit (4)。

3. clock synchronization apparatus according to claim 2, it is characterised in that：The letter code regeneration circuit (4) includes the first D Trigger (U3), the second d type flip flop (U4), NOR gate circuit (U5), the output end connection second of first d type flip flop (U3) The output end of d type flip flop (U4), the output end of the first d type flip flop (U3) and the output end connection XOR of the second d type flip flop (U4) Gate circuit (U5), NOR gate circuit (U5) connection signal output part (2).

4. clock synchronization apparatus according to claim 1, it is characterised in that：The synchronous clock generator (3) includes single Piece machine (U0), clock crystal oscillator circuit (31), clock crystal oscillator circuit (31) the connection single-chip microcomputer (U0) is to provide reference clock Signal.

5. clock synchronization apparatus according to claim 4, it is characterised in that：Reset is additionally provided with the single-chip microcomputer (U0) Circuit (32), the reset circuit (32) gives single-chip microcomputer (U0) to produce reset signal.

6. clock synchronization apparatus according to claim 5, it is characterised in that：The reset circuit (32) includes button (AN1), the 3rd capacitor (C3), first resistor (R1), the button (AN1) and first resistor (R1) series connection and both connections Point provides reset signal, and the 3rd capacitor (C3) is connected in parallel on button (AN1).

7. clock synchronization apparatus according to claim 1, it is characterised in that：The synchronous clock generator (3) also passes through Tongue tube (GH) connection supply unit (5), the tongue tube (GH) connects power supply to induced magnetism.