CN109361500A - A method of the plesiochronous external pulse of self-correcting based on chip - Google Patents
A method of the plesiochronous external pulse of self-correcting based on chip Download PDFInfo
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- CN109361500A CN109361500A CN201811253142.3A CN201811253142A CN109361500A CN 109361500 A CN109361500 A CN 109361500A CN 201811253142 A CN201811253142 A CN 201811253142A CN 109361500 A CN109361500 A CN 109361500A
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- timer
- calibration
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- pulse
- self
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
Abstract
The invention discloses a kind of methods of plesiochronous external pulse of the self-correcting based on chip, complete calibration: step 1 as follows: exporting calibration pulse by impulse generator；Step 2: the calibration pulse in monitoring step one, monitoring result are rising edge or failing edge；Step 3: execution event is carried out according to first timer and second timer of the monitoring result of step 2 to chip interior.Advantages of the present invention: the synchronous microsecond error of clock is promoted to nanosecond rank, the synchronous application of the high efficiency that is more suitable；And the self-calibration mode using closed loop is synchronized in clock, real-time Microsecond grade synchronous error is able to carry out and eliminates.
Description
Technical field
The present invention relates to chip field, in particular to the method for the plesiochronous external pulse of a kind of self-correcting based on chip.
Background technique
The radiofrequency signal switching unit of the dispatching communication of base station is 1 millisecond, is building simulation multi-user's radiofrequency signal switching
When platform, calibration clock signal of the chip used using 10 millisecond pulses that base station exports as chip obtains 10 in chip
When millisecond pulse rising edge carries out internal clocking calibration again, 10 millisecond pulses are compared by oscillograph and timer internal responds
To the high level of GPIO pin, there are the delays of 4-5 microsecond.The switching that this delay will lead to base station radio-frequency signal generates larger
The bit error rate.
Summary of the invention
The technical problem to be solved in the present invention is to provide it is a kind of can be effectively reduced chip response delay based on chip
The method of the plesiochronous external pulse of self-correcting.
In order to solve the above-mentioned technical problem, the technical solution of the present invention is as follows: a kind of plesiochronous outside of self-correcting based on chip
The method of pulse completes calibration as follows:
Step 1: by impulse generator export calibration pulse, it is described calibration pulse period be T, the T be greater than
Natural number equal to 2；
Step 2: the calibration pulse in monitoring step one, monitoring result are rising edge or failing edge；
Step 3: it is executed according to first timer and second timer of the monitoring result of step 2 to chip interior
Event, the period of the first timer are t, and the t is the natural number for being less than or equal to T greater than 1, the week of the second timer
Phase is 1 millisecond；
Execution event is arranged to, and when being detected as rising edge, then enters rising edge interrupt event, initializes and starts the
One timer, by first timer interrupt initialization second timer starting counter value be Nt, the t be greater than 0 from
So number starts second timer, switches the low and high level of GPIO output pin in second timer；
When detecting as failing edge, then the failing edge event of Edge check interruption is triggered, current second timer is read
Corresponding starting counter value Qt is synchronously completed if Qt=0；If Qt ≠ 0, second timer starting counter value Nt+ next time
1=Nt+M-Qt；Wherein, 0≤Nt≤M, the M=G*5*10-3- 1, the G are chip refresh frequency；
Step 4: it repeats step 1 to step 3 and realizes calibration.
Further, further include calibration result monitoring step after the step 3, pulse is calibrated into the response of chip interior
High level time with calibration impulse wave generation time compare, obtain calibration result.
Further, the end loop when calibration result is less than 40 nanosecond.
Further, the duty ratio of the calibration pulse is 0.1.
By adopting the above technical scheme, the synchronous microsecond error of clock is promoted to nanosecond rank, the high efficiency that is more suitable is same
The application of step；And the self-calibration mode using closed loop is synchronized in clock, it is synchronous to be able to carry out real-time Microsecond grade
Error concealment.
Detailed description of the invention
Fig. 1 is flow chart of the method for the present invention.
Specific embodiment
Specific embodiments of the present invention will be further explained with reference to the accompanying drawing.It should be noted that for
The explanation of these embodiments is used to help understand the present invention, but and does not constitute a limitation of the invention.In addition, disclosed below
The each embodiment of the present invention involved in technical characteristic can be combined with each other as long as they do not conflict with each other.
Referring to Fig. 1, present embodiment discloses a kind of method of plesiochronous external pulse of the self-correcting based on chip, leads to
It crosses following steps and completes calibration:
Step 1: by impulse generator export calibration pulse, it is described calibration pulse period be T, the T be greater than
Natural number equal to 2；
Step 2: the calibration pulse in monitoring step one, monitoring result are rising edge or failing edge；
Step 3: it is executed according to first timer and second timer of the monitoring result of step 2 to chip interior
Event, the period of the first timer are t, and the t is the natural number for being less than or equal to T greater than 1, the week of the second timer
Phase is 1 millisecond；
Execution event is arranged to, and when being detected as rising edge, then enters rising edge interrupt event, initializes and starts the
One timer, by first timer interrupt initialization second timer starting counter value be Nt, the t be greater than 0 from
So number starts second timer, switches the low and high level of GPIO output pin in second timer；
When detecting as failing edge, then the failing edge event of Edge check interruption is triggered, current second timer is read
Corresponding starting counter value Qt is synchronously completed if Qt=0；If Qt ≠ 0, second timer starting counter value Nt+ next time
1=Nt+M-Qt；Wherein, 0≤Nt≤M, the M=G*5*10-3- 1, the G are chip refresh frequency；
Step 4: it repeats step 1 to step 3 and realizes calibration.
It preferably, further include calibration result monitoring step in other specific embodiments of the invention, after the step 3
Suddenly, the high level time by the response calibration pulse of chip interior is compared with calibration impulse wave generation time, is calibrated
As a result.
Preferably, it can be set in another embodiment of the invention, when calibration result is less than 40 nanosecond
End loop.The synchronous microsecond error of clock is promoted to nanosecond rank, the synchronous application of the high efficiency that is more suitable；And when
Clock synchronizes the self-calibration mode using closed loop, is able to carry out real-time Microsecond grade synchronous error and eliminates.
It is feasible, by taking STM32F4 chip as an example, by process as shown in Figure 1, passing through the output of STM32F4 chip base station
The rising edge of 10 millisecond pulses (duty ratio 0.1) initializes the first timer of STM32F4 chip interior, passes through the first timing
The corresponding execution event of device initializes the starting counter value Time_CNT (value of the second timer of STM32F4 chip interior
Range is 0-41999), the starting counter value of second timer can make its first timing cycle length there was only 995 microseconds, from
And guarantee that second millisecond moment point of second timer is synchronous with the failing edge of external 10 millisecond pulses (duty ratio 0.1).
The method of chip synchronization external pulse needs the side using 10 millisecond pulse reference signal of base station, STM32F4 chip
Along interruption detection, two timers and GPIO pin.Synchronous method implementation are as follows: external 10 millisecond pulse signals access
Chip Edge check pin monitors 10 millisecond pulse edge transition situations, if being detected as rising edge, enters rising edge and interrupts
Event initializes and starts 10 milliseconds of timers, the starting of 1 millisecond of timer is initialized by 10 milliseconds of timer interruptions
Counting Time_CNT value is Nt (t is the natural number greater than 0, and expression repeats number, wherein N1=0) and 1 millisecond of starting fixed
When device, in 1 millisecond of timer switch GPIO output pin low and high level.As fruit chip detects that 10 millisecond pulses decline
The failing edge event of Edge check interruption is then triggered on edge, reads the corresponding Time_CNT numerical value Qt of current 1 millisecond of clock.If Qt
=0, then it synchronously completes；If Qt ≠ 0,1 millisecond of timer starting counter value Nt+1=Nt+M-Qt next time；Simultaneously by 10 millis
Pulse per second (PPS) and GPIO pin signal access oscillograph check the two synchronous waveform situation.It, can be with by the self-correcting quasi-synchronous method
Check the two final synchronous error of waveform within 40 nanoseconds by oscillograph.
In conjunction with attached drawing, the embodiments of the present invention are described in detail above, but the present invention is not limited to described implementations
Mode.For a person skilled in the art, in the case where not departing from the principle of the invention and spirit, to these embodiments
A variety of change, modification, replacement and modification are carried out, are still fallen in protection scope of the present invention.
Claims (2)
1. a kind of method of the plesiochronous external pulse of self-correcting based on chip, which is characterized in that complete calibration as follows:
Step 1: calibration pulse is exported by impulse generator, the period of the calibration pulse is T, and the T is more than or equal to 2
Natural number；
Step 2: the calibration pulse in monitoring step one, monitoring result are rising edge or failing edge；
Step 3: execution thing is carried out according to first timer and second timer of the monitoring result of step 2 to chip interior
Part, the period of the first timer are t, and the t is the natural number for being less than or equal to T greater than 1, the period of the second timer
It is 1 millisecond；
Execution event is arranged to, and when being detected as rising edge, then enters rising edge interrupt event, initializes and starts first and determines
When device, be Nt by the starting counter value that first timer interrupts initialization second timer, the t is natural number greater than 0,
Start second timer, switches the low and high level of GPIO output pin in second timer；
When detecting as failing edge, then the failing edge event of Edge check interruption is triggered, it is corresponding to read current second timer
Starting counter value QtIf Qt=0, then it synchronously completes；If Qt≠ 0, then second timer starting counter value N next timet+1=Nt+
M-Qt；Wherein, 0≤Nt≤ M, the M=G*5*10-3- 1, the G are chip refresh frequency；
Step 4: it repeats step 1 to step 3 and realizes calibration.
2. a kind of method of the plesiochronous external pulse of self-correcting based on chip according to claim 1, which is characterized in that institute
Stating after step 3 further includes calibration result monitoring step, by the high level time and calibration arteries and veins of the response calibration pulse of chip interior
It rushes wave generation time to compare, obtains calibration result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811253142.3A CN109361500A (en) | 2018-10-25 | 2018-10-25 | A method of the plesiochronous external pulse of self-correcting based on chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811253142.3A CN109361500A (en) | 2018-10-25 | 2018-10-25 | A method of the plesiochronous external pulse of self-correcting based on chip |
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| CN109361500A true CN109361500A (en) | 2019-02-19 |
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| CN201811253142.3A Pending CN109361500A (en) | 2018-10-25 | 2018-10-25 | A method of the plesiochronous external pulse of self-correcting based on chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112448715A (en) * | 2019-08-28 | 2021-03-05 | 珠海格力电器股份有限公司 | Method and system for calibrating HIRC (high impedance remote control) by utilizing PES (polyether sulfone) signal |
| CN113009899A (en) * | 2019-12-20 | 2021-06-22 | 金卡智能集团股份有限公司 | RTC (real time clock) calibration method for high-precision timing of metering instrument |
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| CN102298095A (en) * | 2011-06-27 | 2011-12-28 | 中国国土资源航空物探遥感中心 | Method for ensuring accurate measurement on pulse width in multi-task singlechip system and device |
| EP2416474A2 (en) * | 2010-08-04 | 2012-02-08 | Macroblock, Inc. | Circuit regulator and synchronous timing pulse generation circuit thereof |
| CN104316775A (en) * | 2014-10-29 | 2015-01-28 | 上海大学 | Pulse signal cycle and duty ratio continuous measurement method |
| CN105469591A (en) * | 2016-01-04 | 2016-04-06 | 西安交通大学 | Portable infrared remote control pulse signal generator and pulse width correction method |
| CN106569032A (en) * | 2016-10-17 | 2017-04-19 | 长沙开元仪器股份有限公司 | Signal frequency and duty ratio prediction method based on embedded microcontroller |
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2018
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2416474A2 (en) * | 2010-08-04 | 2012-02-08 | Macroblock, Inc. | Circuit regulator and synchronous timing pulse generation circuit thereof |
| CN102298095A (en) * | 2011-06-27 | 2011-12-28 | 中国国土资源航空物探遥感中心 | Method for ensuring accurate measurement on pulse width in multi-task singlechip system and device |
| CN104316775A (en) * | 2014-10-29 | 2015-01-28 | 上海大学 | Pulse signal cycle and duty ratio continuous measurement method |
| CN105469591A (en) * | 2016-01-04 | 2016-04-06 | 西安交通大学 | Portable infrared remote control pulse signal generator and pulse width correction method |
| CN106569032A (en) * | 2016-10-17 | 2017-04-19 | 长沙开元仪器股份有限公司 | Signal frequency and duty ratio prediction method based on embedded microcontroller |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112448715A (en) * | 2019-08-28 | 2021-03-05 | 珠海格力电器股份有限公司 | Method and system for calibrating HIRC (high impedance remote control) by utilizing PES (polyether sulfone) signal |
| CN112448715B (en) * | 2019-08-28 | 2023-12-08 | 珠海格力电器股份有限公司 | Method and system for calibrating HIRC by using PES (PES) signal |
| CN113009899A (en) * | 2019-12-20 | 2021-06-22 | 金卡智能集团股份有限公司 | RTC (real time clock) calibration method for high-precision timing of metering instrument |
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Application publication date: 20190219 |
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