CN104182202B - There is circuit in the true random number of a kind of oscillator and its composition - Google Patents
There is circuit in the true random number of a kind of oscillator and its composition Download PDFInfo
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- CN104182202B CN104182202B CN201310192755.1A CN201310192755A CN104182202B CN 104182202 B CN104182202 B CN 104182202B CN 201310192755 A CN201310192755 A CN 201310192755A CN 104182202 B CN104182202 B CN 104182202B
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Abstract
There is circuit in the true random number of a kind of oscillator and its composition in the invention discloses IC design field.Oscillator uses new structure, the structure that major loop is used can be the structures such as quadrangle, octagon, dodecagon, that is 4n sides shape structure, wherein n is the integer more than zero, and true random number occurs circuit includes fast oscillator, slow oscillator, XOR circuit, clock circuit, system clock circuit and sample circuit.Oscillator provides stochastic source for true random number occurs circuit, constitute fast oscillator and slow oscillator and controlled by two outside signal a and b of enabling, the primary random number seed of output end signal phase XOR output of fast oscillator and slow oscillator, clock circuit and system clock circuit control sample circuit carry out double sampling to primary random number seed, produce true random number sequence, the true random number occurs circuit and solves that true random number sequence randomness is poor, periodicity produced problem.
Description
Technical field
The invention belongs to IC design field, it is related to the true random number of a kind of oscillator and its composition that circuit occurs,
The true random number sequence that the circuit is produced has height random, may apply to need the various safety encryption necks of true random number
Domain, such as high safety RFID label tag.
Background technology
With the development of radio communication, information security is more and more important, and communication system needs encryption and decryption technology to come real
Existing secure communication, this just be unable to do without random number.Random number includes pseudo random number and true random number, and pseudo random number is calculated by mathematics
Method realizes that, when the Seed Sequences of its input determine that algorithm determines, its output signal is just determined.Pseudo random number has random
The characteristics of property, but output signal is periodic signal, is easily cracked, and security is poor.True random number is by physical features come real
Existing, common implementation method directly amplifies thermal noise method, vibration sampling method, discrete time chaos and realizes method in circuit design
With metastable state circuit realiration method, vibration sampling method using oscillator phase noise and shake as stochastic source, phase noise by
In oscillator caused by the thermal noise of metal-oxide-semiconductor, shake metastable state present in circuit, competition and risk are caused, so producing
The randomness of raw random number is preferable.Because there is circuit realiration procedure structure simply in the true random number based on vibration sampling method,
Required area is few, low in energy consumption, so widely being used in encryption, decryption system and near-field communication etc..
The content of the invention
The present invention provides a kind of oscillator and its true random number of composition occurs circuit, its object is to solve random number with
The problem of machine difference, making the true random number sequence of generation has unpredictable and unduplicated feature.
A kind of oscillator that the present invention is provided, 2n+1 stable loop and 4n oscillation circuit are made up of 8n phase inverter,
Wherein n is the integer more than zero, and each described stable loop includes 1 major loop and 2n cross coupling inverter circuit, should
Major loop is 4n sides shape, is made up of the described phase inverter cascades of 4n, and each phase inverter be located at respectively 4n in of shape on,
The 2n cross coupling inverter circuit is made up of remaining 4n phase inverter, each described cross coupling inverter electricity
The phase inverters that two cascades of route constitute loops are constituted, and on each symmetry axis of 4n sides shape two points with
Two points on one cross coupling inverter circuit are connected；Each described oscillation circuit is constituted by 2n+1 cascade
The reverser in loop is constituted, and in the middle of this 2n+1 phase inverter, 2n phase inverter is located on the major loop, and 1 anti-
Phase device is located on the cross coupling inverter circuit.
There is circuit in the true random number that is made up of the oscillator that the present invention is provided, including fast oscillator, shake at a slow speed
Swing device, XOR circuit, clock circuit, system clock circuit and sample circuit；
Enable signal a outside with two and enable signal b's input of fast oscillator and slow oscillator are connected respectively
Connect, the output end of fast oscillator and slow oscillator is connected with the input of XOR circuit, outside enables signal c and clock
Circuit input end is connected, and clock circuit output end, XOR circuit output end and system clock circuit output end are electric with sampling
The different inputs on road are connected, and the output end of sample circuit is true random number sequence output end；
When enable signal a and enable signal b simultaneously for " 1 " when, fast oscillator and slow oscillator starting of oscillation, quick oscillation
Device produces high-frequency signal, slow oscillator to produce low frequency signal, produce primary random number seed behind the door by XOR；Enable
When signal c is " 1 ", clock circuit produces fixed frequency signal, the signal that the signal and system clock circuit are produced to primary with
The several sons of machine are sampled respectively, and true random number sequence is produced after double sampling.
The fast oscillator is oscillator of the major loop using above-mentioned 4n sides shape structure with slow oscillator, by regulation
The size of metal-oxide-semiconductor realizes the output of different frequency, and to ensure the randomness of true random number, frequency of oscillation is in clock circuit frequency
10 times or so, quick oscillation frequency is more than 10 times of clock circuit frequencies, and frequency of oscillation is less than 10 times of clock frequencies at a slow speed.
The XOR circuit is made up of the exclusive or logic gate of two inputs, realizes XOR function.
The clock circuit is used to provide clock signal to sample circuit, and primary sampling is carried out to primary random number seed,
So as to produce primary random number sequence.The concrete structure of the clock circuit cascades the phase inverter (S for constituting loop by five25、
S26、S27、S28、S29) composition, each inverter input point or exit pointWith over the ground
(GND) metal-oxide-semiconductor electric capacity (M1、M2、M3、M4、M5) be connected, delay feature is realized, and realize by adjusting metal-oxide-semiconductor capacitor size
Required output frequency.
The system clock circuit provides clock signal by broadcast algorithm logical timer, and broadcast algorithm logical timer is numeral
The low-frequency clock of circuit realiration, for being sampled to primary random number sequence, true random number sequence needed for producing.
The sample circuit includes primary sampling d type flip flop and secondary sampling d type flip flop, XOR circuit output and sampling electricity
The input of the primary sampling d type flip flop in road is connected, and the output end of clock circuit accesses the clock signal of primary sampling d type flip flop
Input, primary sampling is carried out to XOR circuit output end signal；It is secondary in primary sampling d type flip flop output end and sample circuit
The input of level sampling d type flip flop is connected, and the output end of system clock circuit accesses the clock signal of secondary sampling d type flip flop
Input, so as to the output signal to primary sampling d type flip flop is sampled, the output end of secondary sampling d type flip flop is very
Random number sequence output end.
The present invention passes through using the fast oscillator and slow oscillator of larger phase noise and shake is possessed as stochastic source
Multiple repairing weld improves randomness, devises a kind of true random number based on vibration sampling method and circuit occurs, and solves random number random
Property difference problem, the true random number sequence of generation has unpredictable and unduplicated feature.Specifically, it is of the invention with it is existing
Technology is compared to following technique effect：
(1) in the present invention, oscillator is used to produce one to receive phase noise and the larger frequency of effect of jitter.Oscillator one
Electric just fast start-up in denier, the advantage of oscillating circuit is to forgive a plurality of loop, and stable loop is mutually nested with oscillation circuit, electricity
" 0 " and " 1 " signal in road ceaselessly overturns, and this causes to be full of line and logical sum race hazard mechanism in circuit, so as to cause
Output frequency is unstable.In addition, this circuit is very sensitive to supply voltage and external noise interference, disturbed when existing in working environment
When, output signal will produce larger amount of jitter, and this further increases truly random number sequence for there is circuit to true random number
The randomness of row.
(2) oscillator major loop of the invention is adopted as the oscillator of quadrangle, octagon, dodecagon etc., and signal is competing
Strive risk seriously, phase noise and the big frequency of shake can be produced；Wherein, major loop is shaking for octagon, dodecagon etc.
Device is swung compared with oscillator of the major loop for quadrangle, and stable loop and oscillation circuit increase, and signal race hazard is more serious, from
And phase noise and the bigger frequency of shake can be produced.
(3) due to true random number occur circuit be using oscillator as stochastic source, and oscillator randomness in itself be by
Phase noise and shake in physical characteristic cause, and it is unpredictable and unduplicated that this allows for true random number generation circuit generation
True random number sequence.
Brief description of the drawings
Fig. 1 is the oscillator circuit structure schematic diagram with quadrangle as major loop；
Fig. 2 is the oscillator circuit structure schematic diagram with octagon as major loop；
Fig. 3 is the structural representation that true random number occurs circuit；
Fig. 4 is the waveform diagram that true random number occurs circuit；
Fig. 5 is the clock circuit structural representation that loop is constituted with five phase inverter cascades.
Specific embodiment
There is circuit in the true random number that a kind of oscillator and its composition are analyzed according to accompanying drawing, following to be merely exemplary
Illustrate, the application that oscillator and true random number occur circuit is not limited in any way.Invention described below each reality
As long as involved technical characteristic does not constitute conflict and can just be mutually combined each other in applying mode.
Fig. 1 is the oscillator circuit structure schematic diagram with quadrangle as major loop, in the middle of the topological structure of the oscillator,
It is respectively that 1., 2., 3., 4., node passes through phase inverter (S with node comprising 4 nodes1、S2、S3、S4、S5、S6、S7、S8) connection.
Oscillator agent structure is 3 stable loops and 4 oscillation circuits.There are 1 major loop and 2 cross-couplings in the middle of stable loop
Inverter circuit, major loop for 1. → 2. → 3. → 4. → 1., cross coupling inverter circuit for 1. → 3. → 1. and 2. → 4.
→②.Oscillation circuit is that the cascade of 3 phase inverters constitutes loops, 4 oscillation circuits be respectively 1. → 2. → 3. → 1., 2. → 3. →
④→②、③→④→①→③、④→①→②→④.By setting metal-oxide-semiconductor size, different output frequencies are obtained, soon
Fast oscillator frequency is more than slow oscillator output frequency.
Fig. 2 is the oscillator circuit structure schematic diagram with octagon as major loop, and the topological structure of oscillator is in Fig. 1
Circuit structure is improved the new departure for putting forward, and its bigger phase noise and shake improve the random of true random number sequence
Property.Topological structure include 8 nodes, be respectively 5., 6., 7., 8., 9., 10.,Node passes through phase inverter with node
(S9、S10、S11、S12、S13、S14、S15、S16) connection.Oscillator agent structure is 5 stable loops and 8 oscillation circuits.Stabilization
There are 1 major loop and 4 cross coupling inverter circuits in the middle of loop, major loop is Cross coupling inverter circuit for 5. → 9. → 5., 6. → 10. → 6., Oscillation circuit is that 5 grades of phase inverter cascades constitute loop, and 8 oscillation circuits are respectively
The oscillator major loop can be not only quadrilateral structure, can also be the structures such as octagon, dodecagon, i.e.,
It is 4n sides shape structure, n is the integer more than zero, and 4n phase inverter cascade constitutes a stable loop, and each phase inverter is on 4n sides
On each side of shape.Two points on the shape symmetry axis of 4n sides are connected with two points on a cross coupling inverter circuit
Connect, cross coupling inverter circuit cascades the phase inverter (S for constituting loop by two17、S18Or S19、S20Or S21、S22Or S23、
S24) constituted, have 2n cross coupling inverter circuit.
Fig. 3 be true random number occur circuit structural representation, including fast oscillator, slow oscillator, XOR circuit,
Clock circuit, system clock circuit and sample circuit, two outside enable signal a and enable signal b respectively with fast oscillator
It is connected with the input of slow oscillator, the output end of fast oscillator and slow oscillator and the input phase of XOR circuit
Connection, outside enables signal c and is connected with clock circuit input, clock circuit output end, XOR circuit output end and system
Clock circuit output end is connected from the different inputs of sample circuit, and the output end of sample circuit is true random number sequence
Output end.
Fig. 4 is the waveform diagram that true random number occurs circuit, fast oscillator and slow oscillator use major loop for
The topological structure of quadrangle, its course of work is as follows,
Step 1：It is electric on fast oscillator and slow oscillator, when signal a is enabled and enable signal b is simultaneously " 1 ", soon
Fast oscillator and slow oscillator starting of oscillation, fast oscillator produce high-frequency signal, and slow oscillator produces low frequency signal, by different
Or primary random number seed is produced after gate.
Step 2：Electricity on clock circuit, it is " 1 " signal to enable signal c, and clock circuit starting of oscillation simultaneously gives primary sampling d type flip flop
Clock signal is provided, primary random number seed is sampled, the primary random number sequence of output.
Step 3：Primary random number sequence enters secondary sampling d type flip flop, and system clock circuit is started working, and to primary
Random number sequence carries out double sampling, true random number sequence needed for producing.
Whole process is from enable signal a and enables signal b while being that " 1 " is t to true random number sequence elapsed-time standards is generated,
Should be noted to enable signal a and enable signal b if not enabling simultaneously, will result in fast oscillator and slow oscillator it
Between uncertain phase difference, so as to increase the otherness between double sampling, this can improve the random of true random number sequence
Property.
Fig. 5 is the clock circuit structural representation that loop is constituted with 5 phase inverter cascades, and loop includes 5 nodes, respectively
ForNode passes through phase inverter (S with node25、S26、S27、S28、S29) connection, oscillation circuit
ForEach node has accessed a metal-oxide-semiconductor electric capacity (M over the ground1、M2、M3、
M4、M5), when it is " 1 " to enable signal c, once upper electricity just starts vibration, regulation metal-oxide-semiconductor size obtains different output frequencies,
So as to carry out primary sampling by the primary random number seed that XOR is produced behind the door to fast oscillator and slow oscillator.
The preferred embodiment of the present invention is the foregoing is only, the specific embodiment of the invention is not limited by this, to being familiar with
The scientific research of the technical field and technical staff can do some after know-why of the invention and specific embodiment are announced to it
Modification and replacement, should all cover this invention protection domain in, therefore, this invention protection domain with claim
Scope is defined.
Claims (5)
1. a kind of oscillator, it is characterised in that it is made up of 2n+1 stable loop and 4n oscillation circuit 8n phase inverter, its
Middle n is the integer more than 1, and each described stable loop includes 1 major loop and 2n cross coupling inverter circuit, and the master returns
Road is 4n sides shape, is made up of the described phase inverter cascades of 4n, and each phase inverter be located at respectively 4n in of shape on, it is described
2n cross coupling inverter circuit is made up of remaining 4n phase inverters, each described cross coupling inverter circuit by
The phase inverters that two cascades constitute loops are constituted, and on each symmetry axis of 4n sides shape two points with one
Two points on the cross coupling inverter circuit are connected；Each described oscillation circuit constitutes loop by 2n+1 cascade
The phase inverter constituted, in the middle of this 2n+1 phase inverter, 2n phase inverter is located on the major loop, 1 phase inverter
On the cross coupling inverter circuit.
2. there is circuit in a kind of true random number being made up of oscillator described in claim 1, it is characterised in that the true random number is sent out
Raw circuit includes fast oscillator, slow oscillator, XOR circuit, clock circuit, system clock circuit and sample circuit；Quickly
Oscillator is oscillator of the major loop using the 4n sides shape structure with slow oscillator；
Enable signal a outside with two and enable signal b's input of fast oscillator and slow oscillator are connected respectively, soon
The output end of fast oscillator and slow oscillator is connected with the input of XOR circuit, and outside enables signal c and clock circuit
Input is connected, clock circuit output end, XOR circuit output end and system clock circuit output end with sample circuit
Different inputs are connected, and the output end of sample circuit is true random number sequence output end；
When enable signal a and enable signal b simultaneously for " 1 " when, fast oscillator and slow oscillator starting of oscillation, fast oscillator are produced
Raw high-frequency signal, slow oscillator produces low frequency signal, produces primary random number seed behind the door by XOR；Enable signal
When c is " 1 ", clock circuit produces fixed frequency signal, and the signal that the signal and system clock circuit are produced is to primary random number
Seed is sampled respectively, and true random number sequence is produced after double sampling；
The sample circuit includes primary sampling d type flip flop and secondary sampling d type flip flop, the output of XOR circuit and sample circuit
The input of primary sampling d type flip flop is connected, and the output end of clock circuit accesses the clock signal of primary sampling d type flip flop
Input, primary sampling is carried out to XOR circuit output end signal；It is secondary in primary sampling d type flip flop output end and sample circuit
The input of level sampling d type flip flop is connected, and the output end of system clock circuit accesses the clock signal of secondary sampling d type flip flop
Input, so as to the output signal to primary sampling d type flip flop is sampled, the output end of secondary sampling d type flip flop is very
Random number sequence output end；
The system clock circuit provides clock signal by broadcast algorithm logical timer, and broadcast algorithm logical timer is digital circuit
The low-frequency clock of realization, for being sampled to primary random number sequence, true random number sequence needed for producing；
The clock circuit is cascaded by five and constitutes the phase inverter in loop and constitute, each inverter input point or exit point with
Metal-oxide-semiconductor electric capacity over the ground is connected, and realizes delay feature, and realizes required output frequency by adjusting metal-oxide-semiconductor capacitor size.
3. there is circuit in true random number according to claim 2, it is characterised in that quick oscillation frequency is more than 10 times of clocks
Channel frequency, frequency of oscillation is less than 10 times of clock frequencies at a slow speed.
4. there is circuit in true random number according to claim 2, it is characterised in that the XOR circuit is different by two inputs
Or gate composition, realize XOR function.
5. there is circuit in true random number according to claim 2, it is characterised in that the clock circuit is used to give sampling electricity
Road provides clock signal, primary sampling is carried out to primary random number seed, so as to produce primary random number sequence.
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| CN201310192755.1A CN104182202B (en) | 2013-05-22 | 2013-05-22 | There is circuit in the true random number of a kind of oscillator and its composition |
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| CN106209099B (en) * | 2016-06-28 | 2019-06-04 | 中国电子科技集团公司第二十四研究所 | Production line analog-digital converter dynamic compensating device based on true random number sequence |
| CN106325814B (en) * | 2016-08-12 | 2018-11-20 | 西安电子科技大学 | True Random Number Generator based on double-ring coupled oscillating circuit |
| CN107506174B (en) * | 2017-08-14 | 2020-07-14 | 深圳大学 | Starvation current ring oscillator-based true random number generator |
| CN111352608B (en) * | 2020-02-28 | 2022-08-02 | 电子科技大学 | Low-overhead FPGA (field programmable Gate array) basic true random number generation system |
| CN113377337B (en) * | 2021-07-07 | 2022-11-04 | 山东方寸微电子科技有限公司 | True random number generator and chip |
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2013
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Effective date of registration: 20200709 Address after: 215000 Jinmao Road 888, Zhoushi Town, Kunshan City, Suzhou City, Jiangsu Province Patentee after: Taixin Intelligent Technology (Kunshan) Co.,Ltd. Address before: 430074 Hubei Province, Wuhan city Hongshan District Luoyu Road No. 1037 Patentee before: HUAZHONG University OF SCIENCE AND TECHNOLOGY |