CN106708471A - True random number generator achieved by full-digital logic circuit - Google Patents
True random number generator achieved by full-digital logic circuit Download PDFInfo
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- CN106708471A CN106708471A CN201710176666.6A CN201710176666A CN106708471A CN 106708471 A CN106708471 A CN 106708471A CN 201710176666 A CN201710176666 A CN 201710176666A CN 106708471 A CN106708471 A CN 106708471A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
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Abstract
The invention discloses a true random number generator achieved by a full-digital logic circuit. The true random number generator comprises N (N>/=1) paths of combinational logic oscillation ring modules, a XOR logic module and a sampling processing logic module, wherein the combinational logic oscillation rings are formed by serially connecting combinational logic units with an odd-power reverse logic function and used for generating irregular high-frequency oscillation signals; the high-frequency signals output by the N paths of unrelated combinational logic oscillation rings are subjected to two-two XOR treatment by the XOR logic module and combined into an irregular high-frequency oscillation signal, and the irregular high-frequency oscillation signal is transmitted to the sampling processing module; the sampling processing module is formed by time sequence logic (triggers or latches) driven by externally-input sampling clock signals and used for sampling the irregular high-frequency oscillation signal generated by the XOR logic module, performing randomness balance and time sequence synchronization on the irregular high-frequency oscillation signal and then outputting the irregular high-frequency oscillation signal. The irregular high-frequency oscillation signal is characterized in that all functional modules are built by digital integrated circuit standard logic units.
Description
Technical field
The invention mainly relates to information security integrated circuit fields, a kind of real random number generator technology is refered in particular to.
Background technology
With the high speed development of computer, informationization technology and Internet of Things, information turns into a kind of valuable wealth.Letter
Breath safety and its safeguard measure turn into an important research topic.Information security is launched based on password theory, and
Randomizer（Abbreviation RNG）It is an indispensable important component of password theory, in encryption, digital signature
It is required for using random number Deng multiple links.Specifically, randomizer is used to produce uncertain random number sequence,
For the realization of the information security technology based on cryptography provides basic module.
Randomizer is generally divided into two classes：Pseudorandom number generator and real random number generator.Pseudo random number occurs
Device is a kind of random number sequence of the determination obtained with the computing rule for determining, if pseudorandom number generator can be got
Computing rule and its key parameter can then predict the random number that will be produced.The good pseudo random number of offered is generally used for calculate
Rule, the encryption occasion of point-to-point exchange information.Real random number generator then need it is uncontrollable, it is unpredictable, it is not reproducible
Enchancement factor is participated in, and produces uncertain random number sequence completely；True random number is more widely applied, be cryptography must
Want part.
With integrated circuit（Integrated Circuit, abbreviation IC or chip）The high speed development of technology, is integrated in core
Real random number generator inside piece turns into study hotspot.At present, occurred based on the true random number for being integrated in chip internal realization
The basic ideas of device scheme are realized using analog circuit, for example, directly amplify noise, simulation chaos algorithm, or frequency
Sampling.These schemes have the following disadvantages：1, analog circuit is realized needing engineer's artificial circuit, artificial craft Butut, and
After the completion of be unfavorable for the multiplexing of multiple projects（The particularly project of different process）, so designed that this is of a relatively high；2, simulation
Circuit implementations can only be integrated into a local location of chip, and its random noise source Relatively centralized may influence random
Property；3, because simulation domain is easily identified in the chips, many attacks for information security chip are to find random number hair
The position of raw device, using the broken ring random number circuit of various means.For example using FIB equipment cut-out random number power supply or
Signal output, causes security to reduce.
Need a kind of low cost, the real random number generator of high safety.
The content of the invention
The present invention solves the technical problem of the real random number generator that a kind of digital logic unit of offer is realized,
By extremely low cost, easily implement in the way of, realize a kind of true random number sequence generation device with anti-attack ability higher.
The present invention for solve the problems, such as the technical scheme that described in technical background, is used for：
The real random number generator that a kind of digital logic unit is realized, such as Fig. 1, including：N roads（N is more than or equal to 1）Combinational logic
Oscillation rings module, XOR module and sampling processing logic module.Combinational logic oscillation rings are by reverse with odd-times
The combinatorial logic unit of logic function is in series, for producing irregular high-frequency oscillation signal；N roads are unconnected each other
The high-frequency signal of combinational logic oscillation rings output is by after XOR module two-by-two XOR, merging and producing irregular height all the way
Frequency oscillator signal, send sampling processing module afterwards；Sampling processing module is driven by from the sampled clock signal of outside input
Sequential logic（Trigger or latch）Composition, for the irregular high-frequency signal of XOR module generation of sampling, and to it
Randomness equilibrium and sequential synchronization process are carried out, is exported afterwards.Feature is that all functional modules are all by digital integrated electronic circuit mark
Quasi- logic unit builds, and it realizes that circuit can be dispersed among Integrated circuit digital logic domain, and this hair is obtained with this
Bright three advantages：1, full logic realization, cost is extremely low；2, the noise that Digital Logical Circuits is produced when working can influence combination to patrol
Collect the output characteristics of oscillation rings, it is ensured that randomness higher；3, realizing each standard block of circuit, to be dispersed in chip whole
Among body Digital Logic, it is difficult to it is identified, substantially increase anti-attack ability, it is ensured that security higher.
The real random number generator that described a kind of digital logic unit is realized, wherein：
N roads combinational logic oscillation rings module is in parallel relationship, and its N roads signal output all delivers to XOR module, XOR
N roads signal is merged into signal output all the way by module in XOR mode, send sampling processing module.I.e. N roads combinational logic shakes
It is in series relationship with XOR module and sampling processing module after swinging ring wired in parallel.
N roads combinational logic oscillation rings are all made up of the standard gate cell of Digital Logic, including but not limited to, inverter module
The standard gate cells with logic reversal function such as INV, NAND gate unit NAND, nor gate unit NOR, and delay unit BUF,
With gate cell AND, OR gate unit OR, XOR gate cell XOR, final election device gate cell MUX etc..Wrapped per road combinational logic oscillation rings
Standard gate cell type, quantity and its connected mode for containing are not quite similar.As Fig. 2 illustrates, combinational logic oscillation rings include one
Standard and gate cell AND（21）, several standard reversed phase device units INV（22）And a final election device unit MUX（23）.Its
In, connected with gate cell AND, inverter module INV and final election device unit, and the output of final election device is connected to and gate cell AND
（21）Input, form an end to end combinational logic ring.With gate cell AND（21）In addition all the way input with it is outer
The enable signal of portion's input connects.When it is logic 1 to enable control signal, combinational logic ring is started working, and exports vibration letter
Number, on the contrary, when enabling signal for logical zero, combinational logic ring does not work, export constant logic.Final election device unit MUX（23）
Under the control of its switch-over control signal, the number for changing the phase inverter INV connected on combinational logic ring.Phase inverter INV's
Number needs to meet condition：No matter which final election device selects, and the standard gate cell on combinational logic ring forms odd-times altogether
The number of times that logic reversal is formed in logic reversal, and combinational logic ring must be more than or equal to 3 times, to improve quality of random numbers, combination
The number of times that logic reversal is formed on logic box is prime number.
Combinational logic oscillation rings comprising the series connection of odd number logic reversal unit can export the vibration of certain nominal frequency f0
Signal, signal frequency f0 determines by the time delay sum t of standard gate cell on combinational logic ring in unit, f0=2/t.By choosing
Select the number of suitable standard gate cell so that the scope of t should be as far as possible small, frequency of oscillation f0 tries one's best height, and the minor variations of t can
Cause the larger change of f0.When side circuit is realized, loop time delay t by chip technology deviation, circuit parasitic, operating temperature,
The factors such as operating voltage, operating current influence and random change；Further, since the standard gate cell for forming time delay is dispersed in
Among Digital Logic, Digital Logic overturns the circuit noise to be formed and can directly affect loop time delay t.So as to be patrolled per combination all the way
It is not constant to collect the actual frequency f of oscillation rings output signal, but the change at random around nominal frequency f0；Various combination
Logic oscillation rings, by the difference of standard block type, quantity and connected mode for being included, residing condition of work is different,
The actual frequency change of output signal is separate without association.
As Fig. 3 illustrates, by the high-frequency signal of the separate combinational logic oscillation rings output in N roads, by XOR mould
Block carries out XOR treatment two-by-two, and signal all the way is exported after every two-way XOR, then these output signals are carried out into XOR treatment two-by-two,
By that analogy.Finally, the signal of N roads combinational logic oscillation rings output becomes by exporting frequency accidental all the way after XOR module
The signal of change.Suitable N values are selected, and per combinational logic oscillation rings all the way, designs suitable nominal frequency, combined N roads and patrol
Oscillation rings output signal is collected by after XOR treatment, obtaining signal actual frequency randomness preferable.The above, XOR mould
Block, is made up of Digital Logic standard gate cell, including but not limited to, XOR gate cell XOR.
Sample logic module is made up of Digital Logic standard gate cell and standard D flip-flop, as shown in figure 4, including：One
For the standard D flip-flop sampled（41）, several standard D flip-flops composition sequential processing circuit（42）, one for same
Walk the standard D flip-flop of output（43）, and the logic processing circuit being made up of Digital Logic standard gate cell（44,45）.Outward
The sampled clock signal of portion's input drives the clock end of all of standard D flip-flop.
The sampling D for being admitted to sample logic module from the high-frequency signal of the frequency accidental change of XOR module output is touched
Hair device（41）Data terminal, signal and the sequential processing circuit of the output end output of d type flip flop of sampling（42）One group of letter of output
Number by logical process（45,44）After feed back to sequential processing circuit（42）D type flip flop group data terminal.Sequential processing circuit
Output signal is by logic processing circuit（45）After produce signal all the way to send synchronism output d type flip flop（43）, synchronism output D triggerings
The data output end of device, output meets the true random number sequence of desired randomness distribution.
In presented above, circuit realiration of the sequential processing circuit comprising Processing Algorithm, Processing Algorithm can be, but not
It is limited to a kind of hash algorithm（Famous hashing algorithm）, such as MD5, SHA, SM3 etc., or a kind of symmetric encipherment algorithm, for example
DES, AES, SM4 etc., or other lightweight algorithms, such as LFSR, CRC etc..
In presented above, the actual frequency f of sample clock frequency fs and the high-frequency signal from the output of combinational logic oscillation rings
Between relation meet following relation：Percentage value of the percentage value of fs/f less than sample clock frequency precision.I.e. such as
The precision of fruit sample clock frequency fs is 1%, then the average value f of high-frequency signal have to be larger than 100 times of fs.
The advantage of the invention is that：
1, real random number generator scheme of the present invention is completely real in chip with digital integrated circuit logic standard block
It is existing, can be automatically obtained by hardware description language and digital back-end treatment eda tool, cost is extremely low；
2, scheme realizes that all circuit parts are both dispersed among chip overall digital logic, when Digital Logical Circuits works
The noise of generation can cause the output frequency randomized jitter of combinational logic oscillating loop, it is ensured that program randomness higher；
3, scheme realizes that all circuit parts all disperse to be hidden among chip overall digital logic, it is extremely difficult to identified, greatly
Improve anti-attack ability greatly, it is ensured that security higher.
Brief description of the drawings：
Fig. 1 is the principle scheme of the real random number generator that a kind of digital logic unit of the present invention is realized
Fig. 2 is that combinational logic oscillation rings inside modules of the present invention constitute structure chart
Fig. 3 is that XOR inside modules of the present invention constitute structure chart
Fig. 4 is that sample logic inside modules of the present invention constitute structure chart
Fig. 5 is a kind of circuit realiration of the real random number generator that a kind of digital logic unit of the present invention is realized
Specific implementation：
To enable the above objects, features and advantages of the present invention more obvious understandable, below in conjunction with the accompanying drawings to tool of the invention
Body implementation method is described in detail.
A kind of circuit realiration of the real random number generator that a kind of digital logic unit of the present invention is realized referring to
Fig. 5.Two-way combinational logic oscillation rings are employed, wherein route standard and a gate cell（51）, 7 standard reversed phase device units and
Individual final election device unit（54）Connect and join end to end composition；Another route standard and gate cell（55）, 13 standard reversed phase device lists
Unit and a final election device unit（58）Connect and join end to end composition.Final election device unit in first via combinational logic oscillation rings（54）
Switching control end by the second road combinational logic oscillation rings final election device unit（58）Output end output signal control, the second tunnel
Final election device unit in combinational logic oscillation rings（58）Switching control end by first via combinational logic oscillation rings final election device unit
（54）Output end output signal control.Two-way combinational logic oscillation rings are multiplexed an enable control signal.
The output signal of two-way combinational logic oscillation rings is sent and is connected to by a standard XOR gate cell（59）The XOR of composition
Logic.
The signal of XOR gate output terminal output is connected to the sample trigger driven by sampling clock（60）, sample trigger is defeated
Go out to hold output signal to send an aes algorithm module driven by sampling clock（61）, aes algorithm module output signal sent by sampling
Clock-driven output synchronizer trigger（62）.Synchronizer trigger output end output signal is random number sequence.
Claims (9)
1. a kind of real random number generator of digital logic realization, including, N roads（N is more than or equal to 1）Combinational logic oscillation rings mould
Block, XOR module and sampling processing logic module, it is characterised in that all built-up sections of randomizer are complete
All realized by the standard gate cell and standard register unit of digital integrated electronic circuit in portion.
2. according to claim 1, it is characterised in that combinational logic oscillation rings module, including but not limited to, inverter module
INV, NAND gate unit NAND, nor gate unit NOR, delay unit BUF and gate cell AND, OR gate unit OR, XOR gate list
The standard combination logic gates such as first XOR, final election device gate cell MUX；Per the standard combination that road combinational logic oscillation rings are included
Logic gate type, quantity and its connected mode are not quite similar.
3. according to claim 2, further, it is characterised in that the combinational logic oscillation rings module, by some grades of marks
Quasi- combinational logic gate cell is in series, and the output termination first order combinational logics of afterbody combinational logic gate cell are single
The input of unit, forms a combinational logic loop.
4. according to claim 3, further, it is characterised in that in the combinational logic oscillation rings module, by some levels
On the combinational logic loop that standard combination logic gate is formed, it is necessary to which the gate cell comprising N number of formation logic reversal, N is more than
Equal to 3, and N is odd number；Further, it is characterised in that N is prime number.
5. according to claim 2, further, it is characterised in that in the combinational logic oscillation rings module, by some levels
On the combinational logic loop that standard combination logic gate is formed, comprising a standard final election device gate cell, two of final election device
Input is connected on the diverse location on combinational logic loop respectively, and the output of final election device terminates next stage standard gate connected in series
Unit, the signal behavior end of final election device can be connected on it where combinational logic oscillation rings certain position, it is also possible to be connected on it
Certain position of its combinational logic oscillation rings, it is also possible to connect described in claim 1, other in real random number generator are any
One circuit position, it is also possible to as described in claim 1, real random number generator outside provides excitation.
6. according to claim 1, it is characterised in that the N roads signal feeding of N roads combinational logic oscillation rings module output has N
The XOR module of 1 output end of individual input, XOR module includes but is not limited to, standard XOR gate cell；
Further, it is characterised in that XOR module realizes the XOR two-by-two to the N roads signal being input into, to output result
Proceed XOR two-by-two, by that analogy, until all input signals of the route of input one participate in the signal of logical operation.
7. according to claim 1, it is characterised in that the feeding sample logic mould of signal all the way of XOR module output
Block, sample logic module includes an input sample trigger, an output synchronizer trigger, and an algorithm process sequential
Circuit.
8. according to claim 7, further, it is characterised in that the clock of all triggers in sample logic module
End is all as described in claim 1, the sampling clock that real random number generator outside provides drives；
Further, it is characterised in that the maximum frequency f of sample clock frequency fs and N roads combinational logic oscillation rings output signal it
Between relation meet following relation：Percentage value of the percentage value of fs/f less than sample clock frequency precision.
9. according to claim 7, further, it is characterised in that the algorithm process sequential electricity of sample logic inside modules
Road, involved algorithm can be, but be not limited to, MD5, SHA, the hash algorithm such as SM3, the symmetry algorithm such as DES, AES, SM4, and
LSFR, CRC etc..
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107193533A (en) * | 2017-07-31 | 2017-09-22 | 南京航空航天大学 | A kind of novel low-cost high-speed, true random-number generator |
| WO2019222866A1 (en) * | 2018-05-24 | 2019-11-28 | 太原理工大学 | True random number generation method and device having detection and correction functions |
| CN111258548A (en) * | 2018-11-30 | 2020-06-09 | 紫光同芯微电子有限公司 | True random number generator |
| CN112379858A (en) * | 2020-11-13 | 2021-02-19 | 北京灵汐科技有限公司 | Method and device for generating random number, electronic equipment and readable storage medium |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107193533A (en) * | 2017-07-31 | 2017-09-22 | 南京航空航天大学 | A kind of novel low-cost high-speed, true random-number generator |
| CN107193533B (en) * | 2017-07-31 | 2020-08-18 | 南京航空航天大学 | Low-cost high-speed true random number generator |
| WO2019222866A1 (en) * | 2018-05-24 | 2019-11-28 | 太原理工大学 | True random number generation method and device having detection and correction functions |
| CN111258548A (en) * | 2018-11-30 | 2020-06-09 | 紫光同芯微电子有限公司 | True random number generator |
| CN112379858A (en) * | 2020-11-13 | 2021-02-19 | 北京灵汐科技有限公司 | Method and device for generating random number, electronic equipment and readable storage medium |
| CN112379858B (en) * | 2020-11-13 | 2024-01-26 | 北京灵汐科技有限公司 | Random number generation method and device, electronic equipment and readable storage medium |
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Application publication date: 20170524 |