CN106325814B - True Random Number Generator based on double-ring coupled oscillating circuit - Google Patents
True Random Number Generator based on double-ring coupled oscillating circuit Download PDFInfo
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Abstract
The invention discloses a kind of True Random Number Generator based on double-ring coupled oscillating circuit, mainly solve the problems, such as that real random number generator output speed is low in the prior art and safety is poor.It includes oscillating circuit and Sample Logic.The oscillating circuit includes four XOR gate XOR and four same or door XNOR, there are three input port and an output ports for each XOR gate and each same or door, and there are two left neighbours, each XOR gate and it is each with or door its first input port connect with the output port of a left neighbours, second input port is connect with the output port of another left neighbour, and third input port is connect with the output port of itself.The Sample Logic, it is triggered using D and forward and backward four XOR gates in oscillating circuit is sampled respectively in rising edge clock and failing edge, output speed is the true random number of 100M or more rate, and the present invention is highly-safe, structure is simple, can be applied to information security field.
Description
Technical field
The invention belongs to digital circuit technique field more particularly to a kind of True Random Number Generators, can be used for secure communication.
Background technique
Random number has vital effect for cryptography, especially heavy in the encryption technology of various protection data
It wants.Existing many software algorithms can generate pseudo random number, but its unpredictability it is difficult to ensure that, wanted in some safeties
It asks in higher application program, pseudo random number cannot meet its requirement well.In order to generate true random number, many is ground
Study carefully using the noise source of simulation as random external source and constructs True Random Number Generator.
Li Shen, Zhao Jianling, Wang Chao, Qu Guang outstanding person Wu enable peace, the patent (patent publication No. of Zhang Feng：CN102637122B it) is based on
The parity of physical noise generates the method and its system of true random number, has invented the signal that a kind of pair of physical noise generates and has carried out
Analog-to-digital conversion generates random bit further according to the parity of number.
Patent (the patent publication No. of Liu little Ling, Qiao Aiguo, Qi Fan, Xie Shaobo：CN102693119B a kind of) true random number
Generation circuit and information security chip generate mixed noise signal by being modulated to random noise signal, then filter out wherein
DC component obtain high-frequency random noises component, generate corresponding true random number.
Japanese plum state, Wang Husen, Li Lijuan patent (patent publication No.：CN103049242A) digital true random number occurs
Device generates random number using by the full-digital circuit of clock control, then is biased correction to random number and obtains true random number.
Patent (the patent publication No. of Wang Qian, Zhang Donglai, Zhang Hua：CN103066956B) a kind of true random number triangular wave occurs
The oscillator signal that multiple high frequency oscillators generate is synchronized exclusive or, then controls triangle with obtained signal by method and device
Wave producer generates true random number.
These above-mentioned methods are due to using the stochastic source of external environment and using the very strong oscillation ring signal of correlation, thus
There are problems that attacker can manipulate generator by influencing noise source, to influence the safety of secret communication
And it is low to generate true random number rate.
Summary of the invention
It is an object of the invention to be directed to above-mentioned prior art deficiency, propose it is a kind of based on double-ring coupled oscillation it is true with
Machine number generator reduces oscillation rings signal correlation to protect the safety of positive secret communication, improves the speed for generating true random number
Rate.
To achieve the above object, the present invention includes：
Oscillating circuit and Sample Logic, the oscillating circuit are made of several digital logic gates, for generate have with
The Random Oscillation signal of machine phase offset；The Sample Logic, the Random Oscillation signal for generating to oscillating circuit carry out
Sampling, converts discrete random sequence for continuous random signal and exports, it is characterised in that：
All digital logic gates, including M/2 XOR gate XOR and M/2 same or door XNOR, wherein M is not less than 6
Even number；There are three input port and an output ports by these XOR gates XOR and same or door XNOR；
The identical XOR gate in every two position and same or Men Jun have identical two left neighbours, i.e. i-th of XOR gate XORi
With i-th of same or door XNORiThere is a XOR gate XOR of identical (i-1) mod (M/2)(i-1)mod(M/2)With (i-1) mod (M/2)
A same or door XNOR(i-1)mod(M/2), wherein i is 1 integer for arriving M/2；
For each logic gate, first input port is connect with the output port of one left neighbour, and second defeated
Inbound port is connect with another left neighbor output ports, and third input port is connect with the output port of itself.
Preferably, the N XOR gate, realized using the basic programmable logic cells of FPGA, the logic unit by
Exclusive or look-up table LUT and register group are at realizing XOR gate pure digi-tal logic by searching for table, pass through register and save digital shape
State.
Preferably, the N with or door, using FPGA basic programmable logic cells realize, the logic unit by
With or look-up table LUT and register group at, by searching for table realize with or door pure digi-tal logic, pass through register and save digital shape
State.
The invention has the advantages that as follows：
1. the true random number stability generated is strong, output speed is high.
The double-ring coupled oscillating circuit that the present invention constructs is to existing in circuit system due to not having random external source only
Thermal noise amplifies to generate very strong phase noise, so the extremely strong true random number of stability can be generated；
Simultaneously because the output signal of double-ring coupled oscillating circuit has high frequency of oscillation and very wide frequency spectrum, adopt
The sample frequency of sample logic circuit is up to 100MHZ, can pass through international random number industry examination criteria, that is, NIST statistic mixed-state packet
Detection, the true random number randomness of generation are strong.
2. the present invention is since entire randomizer is all realized by digital logic unit, used circuit resource pole
It is few, it is easily integrated into the chip applied to security fields.
3. the present invention is carried out due to the Sample Logic using double sampled pattern in rising edge clock and failing edge
It samples its result exclusive or to export again, the output ratio deviation of " 1 " bit He " 0 " bit can be reduced, improve the random number sequence of output
The quality of column eliminates subsequent post-processing step.
Detailed description of the invention
Fig. 1 is the principle of the present invention block diagram；
Fig. 2 is circuit structure diagram of the invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to embodiments, to the present invention
It is described in further detail.It should be appreciated that specific embodiment described herein is used only for explaining the present invention, it is not used to limit
The fixed present invention.
Referring to Fig.1, the present invention includes oscillating circuit, Sample Logic.Oscillating circuit R1 is for generating random signal；It adopts
Sample logic circuit is for sampling the oscillating circuit R1 random signal generated, and the output end of the sample logic is as truly random
The output end of number generator exports true random number sequence.
It is as follows to oscillating circuit of the invention and Sample Logic structure referring to Fig. 2：
The oscillating circuit, including including M/2 XOR gate XOR and M/2 same or door XNOR, wherein M is not less than 6
Even number, this example take M=8, i.e. four XOR gates are respectively：First XOR gate XOR1, the second XOR gate XOR2, third XOR gate
XOR3With the 4th XOR gate XOR4；Four with or door be respectively：First same or door XNOR1, second with or door XNOR2, third with or
Door XNOR3With the 4th same or door XNOR4。
The identical XOR gate in every two position and same or Men Jun have identical two left neighbours, wherein：
First XOR gate XOR1Two left neighbours be respectively the 4th XOR gate XOR4With the 4th same or door XNOR4；
First same or door XNOR1Two left neighbours be respectively the 4th XOR gate XOR4With the 4th same or door XNOR4；
Second XOR gate XOR2Two left neighbours be respectively the first XOR gate XOR1With the first same or door XNOR1；
Second same or door XNOR2Two left neighbours be respectively the first XOR gate XOR1With the first same or door XNOR1；
Third XOR gate XOR3Two left neighbours be respectively the second XOR gate XOR2With the second same or door XNOR2；
Third with or door XNOR3Two left neighbours be respectively the second XOR gate XOR2With the second same or door XNOR2；
4th XOR gate XOR4Two left neighbours be respectively third XOR gate XOR3With third with or door XNOR3；
4th same or door XNOR4Two left neighbours be respectively third XOR gate XOR3With third with or door XNOR3；
Each XOR gate and each same or door, there are three input port, i.e. first input ports, second input terminal
Mouth, third input port and an output port, first input port are connect with the output port of one left neighbour, the
Two input ports are connect with its another left neighbor output ports, and third input port is connect with the output port of itself.
Wherein：
First XOR gate XOR1First input port and the 4th XOR gate XOR4Output port connection, second is defeated
Inbound port and the 4th same or door XNOR4Output port connection, third input port connect with the output port of itself；
First same or door XNOR1First input port and the 4th XOR gate XOR4Output port connection, second is defeated
Inbound port and the 4th same or door XNOR4Output port connection, third input port connect with the output port of itself；
Second XOR gate XOR2First input port and the first XOR gate XOR1Output port connection, second is defeated
Inbound port and the first same or door XNOR1Output port connection, third input port connect with the output port of itself；
Second same or door XNOR2First input port and the first XOR gate XOR1Output port connection, second is defeated
Inbound port and the first same or door XNOR1Output port connection, third input port connect with the output port of itself；
Third XOR gate XOR3First input port and the second XOR gate XOR2Output port connection, second is defeated
Inbound port and the second same or door XNOR2Output port connection, third input port connect with the output port of itself；
Third with or door XNOR3First input port and the second XOR gate XOR2Output port connection, second is defeated
Inbound port and the second same or door XNOR2Output port connection, third input port connect with the output port of itself；
4th XOR gate XOR3First input port and third XOR gate XOR3Output port connection, second is defeated
Inbound port and third with or door XNOR3Output port connection, third input port connect with the output port of itself；
4th same or door XNOR3First input port and third XOR gate XOR3Output port connection, second is defeated
Inbound port and third with or door XNOR3Output port connection, third input port connect with the output port of itself.
The Sample Logic includes 8 trigger D1、D2、D3、D4、D5、D6、D7、D8With three XOR gate XOR5、
XOR6、XOR7, wherein：
First four d type flip flop D1、D2、D3、D4Respectively in oscillating circuit two XOR gates and with or door be connected, i.e., the
One trigger D1Input be the first XOR gate XOR1Output, the second trigger D2Input be second with or door XNOR2It is defeated
Out, third trigger D3Input be third XOR gate XOR3Output, the 4th trigger D4Input be the 4th with or door
XNOR4Output, four d type flip flop D1、D2、D3、D4Output as the 5th XOR gate XOR5Input；
Four d type flip flop D afterwards5、D6、D7、D8Be connected respectively with two XOR gates in oscillating circuit and same or door, i.e., the 5th
Trigger D5Input be first with or door XNOR1Output, the 6th trigger D6Input be the second XOR gate XOR2It is defeated
Out, the 7th trigger D7Input be third fellow disciple XOR3Output, the 8th trigger D8Input be the 4th XOR gate XOR4's
Output, four d type flip flop D5、D6、D7、D8Output as the 6th XOR gate XOR6Input, the 5th XOR gate XOR5It is defeated
Out with the 6th XOR gate XOR5Output as the 7th XOR gate XOR7Input, the 7th XOR gate XOR7Output as sampling
The output of logic circuit.
Eight d type flip flop D1、D2、D3、D4、D5、D6、D7、D8With three XOR gate XOR5、XOR6、XOR7By it is identical when
Clock controls, which is provided by external clock CLK, when external clock CLK is rising edge, controls first four d type flip flop D1、
D2、D3、D4Sampling, when external clock CLK be lower liter along when, four d type flip flop D after control5、D6、D7、D8Sampling.
Effect of the invention can be further illustrated by following testing result：
1, detection method：
Under the frequency driving that external clock is 100MHZ, the true random sequence of 1000 groups of 1M is generated；
The SP800-22 random number examination criteria provided using American National Standard and technical research institute NIST is to above-mentioned
The randomness of the true random sequence of 1000 groups of 1M is detected, which includes 15 detection contents, and each single item detection produces
It include a P-value value and a percent of pass Propotion value in raw testing result.When P-value value is not less than 0.001
And percent of pass value is not less than 0.9806, indicates that this detection content passes through.
2, testing result：
True random sequence to the 1000 groups of 1M generated with the present invention, is mentioned with American National Standard and technical research institute NIST
The SP800-22 random number examination criteria of confession is detected, as a result such as table 1：
1 test result of table
| StatisticalTest | P-value | Propotion | Result |
| Frequence | 0.579579 | 0.9900 | Pass |
| BlockFrequence | 0.619506 | 0.9900 | Pass |
| CumulativeSums | 0.345678 | 0.9860 | Pass |
| Runs | 0.231816 | 0.9900 | Pass |
| LongestRun | 0.268716 | 0.9860 | Pass |
| Rank | 0.715034 | 0.9840 | Pass |
| FFT | 0.563178 | 0.9860 | Pass |
| OverlappingTemplate | 0.267932 | 0.9900 | Pass |
| Universal | 0.133111 | 0.9879 | Pass |
| LinearComplexity | 0.435453 | 0.9900 | Pass |
| ApproximateEntropy | 0.353447 | 0.9840 | Pass |
| Serial | 0.227951 | 0.9880 | Pass |
| NonOverlappingTemplate | 0.192880 | 0.9867 | Pass |
| RandomExcursions | 0.189459 | 0.9902 | Pass |
| RandomExcursionsVariant | 0.277424 | 0.9967 | Pass |
As seen from Table 1, each index of the present invention generates true random sequence has reached the requirement standard of random number, shows
The random number that the present invention generates has good randomness.
Above-described embodiment only with specific implementation illustrate implementation method of the invention, on this basis can there are many deformation,
It is this to be all included in the scope of protection of the present invention based on structure change of the invention.
Claims (5)
1. based on the True Random Number Generator of double-ring coupled oscillating circuit, including：Oscillating circuit and Sample Logic, the oscillation
Circuit is made of several digital logic gates, for generating the Random Oscillation signal with random phase offset；Sample logic electricity
Road, the Random Oscillation signal for generating to oscillating circuit sample, and convert continuous random signal to discrete random
Sequence is exported, it is characterised in that：
All digital logic gates, including M/2 XOR gate XOR and M/2 same or door XNOR, wherein M is the idol not less than 6
Number；There are three input port and an output ports by these XOR gates XOR and same or door XNOR；
The identical XOR gate in every two position and same or Men Jun have identical two left neighbours, i.e. i-th of XOR gate XORiWith i-th
A same or door XNORiThere is a XOR gate XOR of identical (i-1) mod (M/2)(i-1)mod(M/2)It is a same with (i-1) mod (M/2)
Or door XNOR(i-1)mod(M/2), wherein i is 1 integer for arriving M/2；
For each logic gate, first input port is connect with the output port of one left neighbour, second input terminal
Mouth is connect with another left neighbor output ports, and third input port is connect with the output port of itself.
2. the True Random Number Generator as described in claim 1 based on double-ring coupled oscillating circuit, it is characterised in that：
The XOR gate XOR, using FPGA basic programmable logic cells realize, the logic unit by exclusive or look-up table
LUT and register group are at saving digital state by register by exclusive or look-up tables'implementation XOR gate pure digi-tal logic.
3. the True Random Number Generator according to claim 1 based on double-ring coupled oscillating circuit, it is characterised in that：
It is described with or door XNOR, using FPGA basic programmable logic cells realize, the logic unit by with or look-up table
LUT and register group at, by with or look-up tables'implementation with or door pure digi-tal logic, digital state is saved by register.
4. the True Random Number Generator according to claim 1 based on double-ring coupled oscillating circuit, it is characterised in that：
The Sample Logic includes 8 trigger D1、D2、D3、D4、D5、D6、D7、D8With three XOR gate XORM/2+1、
XORM/2+2、XORM/2+3, wherein：
First four d type flip flop D1、D2、D3、D4Respectively in oscillating circuit two XOR gates and with or door be connected, i.e., first trigger
Device D1Input be the first XOR gate XOR1Output, the second trigger D2Input be second with or door XNOR2Output,
Three trigger D3Input be third XOR gate XOR3Output, the 4th trigger D4Input be the 4th with or door XNOR4It is defeated
Out, four d type flip flop D1、D2、D3、D4Output as M/2+1 XOR gate XORM/2+1Input；
Four d type flip flop D afterwards5、D6、D7、D8Be connected respectively with two XOR gates in oscillating circuit and same or door, i.e. the 5th trigger
D5Input be first with or door XNOR1Output, the 6th trigger D6Input be the second XOR gate XOR2Output, the 7th
Trigger D7Input be third fellow disciple XOR3Output, the 8th trigger D8Input be the 4th XOR gate XOR4Output, should
Four d type flip flop D5、D6、D7、D8Output as M/2+2 XOR gate XORM/2+2Input, M/2+1 XOR gate XORM/2+1
Output and M/2+2 XOR gate XORM/2+2Output as M/2+3 XOR gate XORM/2+3Input, M/2+3 XOR gate
XORM/2+3Output of the output as Sample Logic.
5. the True Random Number Generator according to claim 4 based on double-ring coupled oscillating circuit, it is characterised in that：Eight
D type flip flop D1、D2、D3、D4、D5、D6、D7、D8With three XOR gate XORN+1、XORN+2、XORN+3It is controlled by identical clock, it should
Clock is provided by external clock CLK, when external clock CLK is rising edge, controls first four d type flip flop D1、D2、D3、D4It adopts
Sample, when external clock CLK be lower liter along when, four d type flip flop D after control5、D6、D7、D8Sampling.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001142682A (en) * | 1999-11-12 | 2001-05-25 | Sony Corp | Random number generator and random number generating method |
| CN1782987A (en) * | 2004-09-28 | 2006-06-07 | 迈克纳斯公司 | Random number generator and method for random number generation |
| CN104182202A (en) * | 2013-05-22 | 2014-12-03 | 华中科技大学 | Oscillator and true random number generating circuit formed by same |
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| JP4248950B2 (en) * | 2003-06-24 | 2009-04-02 | 株式会社ルネサステクノロジ | Random number generator |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001142682A (en) * | 1999-11-12 | 2001-05-25 | Sony Corp | Random number generator and random number generating method |
| CN1782987A (en) * | 2004-09-28 | 2006-06-07 | 迈克纳斯公司 | Random number generator and method for random number generation |
| CN104182202A (en) * | 2013-05-22 | 2014-12-03 | 华中科技大学 | Oscillator and true random number generating circuit formed by same |
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