CN110336536B - Circuit and device for true random number generator - Google Patents
Circuit and device for true random number generator Download PDFInfo
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- CN110336536B CN110336536B CN201910687908.7A CN201910687908A CN110336536B CN 110336536 B CN110336536 B CN 110336536B CN 201910687908 A CN201910687908 A CN 201910687908A CN 110336536 B CN110336536 B CN 110336536B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
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- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
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Abstract
The invention discloses a circuit and equipment of a true random number generator, which relates to the field of true random number generators, wherein the circuit comprises: the invention improves the noise extraction efficiency of a low-frequency oscillation signal by using the symmetrical output of a coupled ring oscillator as the high-frequency oscillation signal, reduces the requirement on the post-processing circuit from the whole of the true random number generator, realizes the circuit of the true random number generator which reduces the circuit resource consumption and the realization difficulty and simultaneously meets the requirements of the generation rate and the power consumption.
Description
Technical Field
The invention relates to the field of true random number generators, in particular to a circuit and equipment of a true random number generator.
Background
A true random number generator is one of the random number generators that operates on the principle of converting random physical phenomena (e.g. "thermal noise") in a circuit into an electrical signal to obtain a random bit stream (e.g. "01001110"). The implementation scheme of the existing true random number generator can be divided into the following steps: 1) The noise is directly amplified and then compared with a specific reference, and the scheme has higher requirements on the bandwidth and the precision of the amplifier and has relatively high implementation difficulty; 2) Based on the metastable state property conversion of the digital circuit, the scheme can realize higher random number generation speed, but is sensitive to the deviation of the semiconductor process, and a correction function is required to be added into the post-processing circuit to eliminate the deviation, so that the complexity of the post-processing circuit is increased; 3) The low-frequency oscillation signal samples the high-frequency oscillation signal, the implementation difficulty of the scheme is lower, but the relation between the frequencies of the two oscillation signals is limited greatly, and the inherent frequency constraint between the two oscillators can introduce periodicity to the output bit stream, so that the scheme has great requirements on a post-processing circuit.
Therefore, it is necessary to provide a circuit of a true random number generator which reduces the circuit resource consumption, reduces the implementation difficulty, and meets the requirements of the generation rate and the power consumption.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems in the related art to some extent. Therefore, the invention aims to provide a circuit of a true random number generator, which reduces the consumption of circuit resources, reduces the implementation difficulty and meets the requirements of generating speed and power consumption.
The technical scheme adopted by the invention is as follows:
in a first aspect, the present invention provides a circuit for a true random number generator, comprising: an entropy extraction circuit and a post-processing circuit;
the entropy extraction circuit generates an original bit stream and sends the original bit stream to the post-processing circuit, and the post-processing circuit outputs a true random number bit stream;
the entropy extraction circuit includes: the low-frequency current control type ring oscillator, the high-frequency coupling ring oscillator, the entropy extraction first D trigger, the entropy extraction second D trigger and the entropy extraction exclusive-OR gate circuit, wherein the low-frequency current control type ring oscillator generates a clock signal and sends the clock signal to the entropy extraction first D trigger and the entropy extraction second D trigger, the high-frequency coupling ring oscillator generates a first high-frequency signal and sends the first high-frequency signal to the entropy extraction first D trigger, and generates a second high-frequency signal and sends the second high-frequency signal to the entropy extraction second D trigger, the output ends of the entropy extraction first D trigger and the entropy extraction second D trigger are connected to serve as inputs of the entropy extraction exclusive-OR gate circuit, the entropy extraction exclusive-OR gate circuit outputs the original bit stream, and the clock signal serves as an entropy source;
the post-processing circuit is a multi-stage exclusive-or chain circuit.
Further, the low-frequency current control type ring oscillator also comprises a delay unit, wherein the output end of the low-frequency current control type ring oscillator is connected with the input end of the delay unit and is used for transmitting the clock signal to the delay unit, and the output end of the delay unit is connected with the input end of the multistage exclusive-or chain circuit.
Further, the low-frequency current control type ring oscillator is formed by connecting at least 5 current control type inverters with the same structure, and the current control type inverters comprise: the first field effect transistor, the second field effect transistor, the third field effect transistor and the fourth field effect transistor, and specifically:
the grid electrode of the first field effect tube is connected with a first bias voltage power supply, the source electrode of the first field effect tube is connected with a power supply, the drain electrode of the first field effect tube is connected with the source electrode of the second field effect tube, the drain electrode of the second field effect tube is connected with the drain electrode of the third field effect tube, the grid electrode of the second field effect tube is connected with the grid electrode of the third field effect tube, the source electrode of the third field effect tube is connected with the drain electrode of the fourth field effect tube, the grid electrode of the fourth field effect tube is connected with a second bias voltage power supply, the source electrode of the fourth field effect tube is grounded, the output end of the current control type inverter is the drain electrode of the second field effect tube, and the input end of the current control type inverter is the grid electrode of the second field effect tube;
the output end of the current control type inverter is used as the input end of the current control type inverter of the next stage;
the output end of the low-frequency current control type ring oscillator is the output end of the current control type inverter of the last stage and is connected with the input end of the current control type inverter of the first stage.
Further, the first field effect transistor and the second field effect transistor are P-type field effect transistors, and the third field effect transistor and the fourth field effect transistor are N-type field effect transistors.
Further, the high-frequency coupled ring oscillator is composed of 8 inverters, which are respectively: the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter specifically include:
the output end of the first inverter is respectively connected with the input end of the second inverter and the input end of the sixth inverter, the output end of the second inverter is connected with the input end of the third inverter and the input end of the seventh inverter, the output end of the seventh inverter is connected with the input end of the first inverter, the output end of the sixth inverter and the output end of the third inverter are respectively connected with the input end of the fourth inverter, the output end of the fourth inverter is respectively connected with the input end of the eighth inverter and the input end of the first inverter, the output end of the eighth inverter is connected with the input end of the third inverter, the output end of the sixth inverter is connected with the input end of the fifth inverter, and the output end of the fifth inverter is connected with the input end of the sixth inverter.
Further, the phase delay of the first high frequency signal and the second high frequency signal is 180 degrees.
Further, the multi-stage exclusive-or chain circuit includes: an input circuit and a plurality of single-stage exclusive-or circuits, the input circuit including a first D flip-flop, the plurality of single-stage exclusive-or circuits respectively including: the output end of the clock signal D trigger is connected with the first input end of the exclusive-OR circuit, the second input end of the exclusive-OR circuit is used as the input end of the current single-stage exclusive-OR circuit, and the output end of the exclusive-OR circuit is used as the output end of the current single-stage exclusive-OR circuit;
the output end of the low-frequency current control type ring oscillator is respectively connected with the clock signal input end of the first D trigger and the clock signal input ends of a plurality of clock signal D triggers; the output end of the first D trigger is connected with the input end of the first single-stage exclusive-or circuit, the output end of the current single-stage exclusive-or circuit is sequentially connected with the input end of the next single-stage exclusive-or circuit, and the output end of the last single-stage exclusive-or circuit is used as the output end of the multi-stage exclusive-or circuit and is used for outputting a true random number bit stream.
In a second aspect, the present invention also provides a device for generating a true random number using a circuit of a true random number generator as described in any one of the first aspects.
The beneficial effects of the invention are as follows:
the circuit of the true random number generator of the invention comprises: the device comprises an entropy extraction circuit and a post-processing circuit, wherein the entropy extraction circuit generates an original bit stream and sends the original bit stream to the post-processing circuit, the post-processing circuit outputs a true random number bit stream, and the entropy extraction circuit comprises: the low-frequency current control type ring oscillator and the high-frequency coupling ring oscillator, the low-frequency current control type ring oscillator generates a clock signal and sends the clock signal to the entropy extraction first D trigger and the entropy extraction second D trigger, the high-frequency coupling ring oscillator generates a first high-frequency signal and sends the first high-frequency signal to the entropy extraction first D trigger, and generates a second high-frequency signal and sends the second high-frequency signal to the entropy extraction second D trigger, the outputs of the entropy extraction first D trigger and the entropy extraction second D trigger serve as inputs of an exclusive-OR gate, the exclusive-OR gate outputs an original bit stream, the clock signal serves as an entropy source, and the post-processing circuit is a multi-stage exclusive-OR chain circuit. The invention improves the noise extraction efficiency of the low-frequency oscillation signal by using the symmetrical output of the coupled ring oscillator as the high-frequency oscillation signal, reduces the requirement on a post-processing circuit from the whole of the true random number generator, realizes the reduction of circuit resource consumption, reduces the realization difficulty and simultaneously meets the requirements of the generation rate and the power consumption.
Drawings
FIG. 1 is a block diagram of a circuit configuration of a true random number generator according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of an embodiment of a true random number generator according to the present invention;
FIG. 3 is a schematic diagram of a low frequency current controlled ring oscillator in accordance with one embodiment of the present invention;
FIG. 4 is a schematic diagram of a high frequency coupled ring oscillator in accordance with one embodiment of the present invention;
fig. 5 is a schematic diagram of a multi-stage xor chain circuit according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will explain the specific embodiments of the present invention with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the invention, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Embodiment one:
an embodiment of the present invention provides a circuit of a true random number generator, fig. 1 is a circuit block diagram of the true random number generator provided in the embodiment of the present invention, as shown in fig. 1, including: the device comprises an entropy extraction circuit and a post-processing circuit, wherein the entropy extraction circuit generates an original bit stream and sends the original bit stream to the post-processing circuit, and the post-processing circuit outputs a true random number bit stream.
Specifically, the entropy extraction circuit is mainly responsible for converting random jitter in the circuit into a changed level signal, the post-processing circuit converts the changed level signal into a bit stream on the basis of the random jitter, and meanwhile, the periodicity introduced by non-random factors such as process errors, flicker noise, non-random jitter and the like is reduced.
As shown in fig. 2, a specific circuit diagram of the true random number generator in this embodiment specifically includes: the device comprises an entropy extraction circuit, a delay unit and a post-processing circuit, wherein the post-processing circuit is a multi-stage exclusive-or chain circuit 30.
The entropy extraction circuit includes: the low-frequency current control type ring oscillator 10, the high-frequency coupled ring oscillator 11, the entropy extraction first D flip-flop 12, the entropy extraction second D flip-flop 13 and the exclusive-or gate circuit, the low-frequency current control type ring oscillator 10 generates a clock signal and sends the clock signal to the entropy extraction first D flip-flop 12 and the entropy extraction second D flip-flop 13, the high-frequency coupled ring oscillator 11 generates a first high-frequency signal and sends the first high-frequency signal to the entropy extraction first D flip-flop 12 and generates a second high-frequency signal and sends the second high-frequency signal to the entropy extraction second D flip-flop 13, the outputs of the entropy extraction first D flip-flop 12 and the entropy extraction second D flip-flop 13 serve as inputs of the entropy extraction exclusive-or gate circuit 14, the entropy extraction exclusive-or gate circuit 14 outputs an original bit stream, in this embodiment, the clock signal serves as an entropy source, and is input to the delay unit 20, the output of the delay unit 20 and the original bit stream serve as inputs of the multi-stage exclusive-or gate circuit 30, and the phase delay of the first high-frequency signal and the second high-frequency signal is 180 degrees.
In this embodiment, the entropy source is a clock signal generated by the low-frequency current-controlled ring oscillator 10, and the entropy source is not two paths of high-frequency signals generated by the high-frequency coupled ring oscillator 11, which is different from the concept of adopting two paths of signals as entropy sources in the prior art, and in this embodiment, the generated clock signal is sent to the post-processing circuit for the purpose of ensuring the consistency of output bits. For example, when the clock T1 arrives, the first high-frequency signal enters the entropy extraction first D flip-flop 12 and sequentially passes through the subsequent circuit, and then the clock T2 arrives, the second high-frequency signal enters the entropy extraction second D flip-flop 13 and sequentially passes through the subsequent circuit, and since the multi-stage exclusive-or circuit needs to exclusive-or adjacent bits of the original bit stream, the delay is caused by Cao Ang, in order to ensure that signals of the first high-frequency signal and the second high-frequency signal, which are output through the flip-flop and the post-processing circuit, can be normally output in the period of the clock T1 and the clock T2, the clock signal needs to be sent to the post-processing circuit through the delay unit 20, so that the post-processing circuit can normally work at the same frequency.
Referring to fig. 2, the working principle of the present embodiment is as follows: in the entropy extraction circuit, a clock signal generated by a low-frequency current control type ring oscillator 10 is directly connected to an entropy extraction first D trigger 12 and an entropy extraction second D trigger 13, meanwhile, the clock signal is connected to a multi-stage exclusive-or chain circuit 30 through a delay unit 20, a high-frequency coupling ring oscillator 11 generates a first high-frequency signal and a second high-frequency signal, the two signals have the same oscillation frequency and 180-degree phase difference, conventional sampling is realized through the entropy extraction first D trigger 12 and the entropy extraction second D trigger 13, random jitter is converted into high and low levels with an indefinite period, meanwhile, an entropy extraction exclusive-or gate circuit 14 carries out exclusive-or operation on the output of the two input triggers, the periodic correlation of the low-frequency signal and the high-frequency signal is eliminated, an original bit stream is output, and the original bit stream is obtained after passing through the multi-stage exclusive-or chain circuit 30.
The conventional single sampling inside the entropy extraction circuit is modified into symmetrical sampling, the essence of the symmetrical sampling is that two same-frequency signals with 180-degree phase difference are sampled through a single signal, the sampling result is in a fixed high level theoretically through the output of an exclusive-OR gate (because two sampled signals are in opposite phase, one sampling result is 1 and the other sampling result is 0, so that periodicity caused by non-random factors is eliminated, the sensitivity of the entropy extraction process to the frequency change of an oscillator is reduced, and the requirement of a true random number generator on a post-processing circuit is reduced.
Specific components in the entropy extraction circuit and the post-processing circuit of the present embodiment are further described below, and in addition, the present embodiment has no performance and functional requirements for the basic modules such as a common not-gate inverter, a D flip-flop, and an exclusive-or gate, so the specific structure thereof is not described in detail.
As shown in fig. 3, which is a specific circuit diagram of the low-frequency current-controlled ring oscillator in this embodiment, it can be seen that the low-frequency current-controlled ring oscillator 10 is formed by connecting at least 5-stage current-controlled inverters having the same structure, and the current-controlled inverter 101 includes: first fet 1011, second fet 1012, third fet 1013, and fourth fet 1014, in one embodiment, first fet 1011 and second fet 1012 are P-type fets, and third fet 1013 and fourth fet 1014 are N-type fets, the connection relationships of which are as follows:
the gate of the first fet 1011 is connected to a first bias voltage power supply (denoted vbiasp), the source of the first fet 1011 is connected to a power supply (denoted vdd), the drain of the first fet 1011 is connected to the source of the second fet 1012, the drain of the second fet 1012 is connected to the drain of the third fet 1013, the gate of the second fet 1012 is connected to the gate of the third fet 1013, the source of the third fet 1013 is connected to the drain of the fourth fet 1014, the gate of the fourth fet 1014 is connected to a second bias voltage power supply (denoted vbiasn), the source of the fourth fet 1014 is grounded, the output of the current controlled inverter 101 is the drain of the second fet 1012, and the input of the current controlled inverter 101 is the gate of the second fet 1012.
The output terminal of the current-controlled inverter 101 is used as the input terminal of the next-stage current-controlled inverter, as shown in the figure, the output terminal of the current-controlled inverter 101 is connected to the input terminal of the current-controlled inverter 102, the output terminal of the current-controlled inverter 102 is connected to the input terminal of the current-controlled inverter 103 by the connection …, and the output terminal of the last-stage current-controlled inverter (i.e., the current-controlled inverter 105) is used as the output terminal of the low-frequency current-controlled ring oscillator 10 and is connected to the input terminal of the first-stage current-controlled inverter (i.e., the current-controlled inverter 101).
More circuit resources, such as power consumption and chip area, are typically consumed in order to obtain a lower oscillation frequency, and therefore more inverters are typically required to cascade in order to obtain a low frequency signal if a common ring oscillator is used, which consumes more circuit resources. The current control type inverter is adopted for cascade connection, the grid voltage of the current source tube can be controlled to control the current passing through the current control type inverter so as to control the oscillation frequency, the chip area can be reduced, and the implementation scheme of sampling the high-frequency oscillation signal by the low-frequency oscillation signal takes random jitter of the oscillation signal as an entropy source, the jitter is in inverse proportion to the current flowing through the transistor, and compared with the current control type inverter, the current control type inverter is smaller in current and can display larger random jitter.
Referring to fig. 3, in the present embodiment, the low-frequency current controlled ring oscillator 10 is different from a general ring oscillator in that: the first bias voltage power supply and the second bias voltage power supply reduce the current flowing through the current control type inverter of the next stage, so that the lower oscillation frequency is achieved under the condition that the number of stages of the current control type inverter is smaller, and the random jitter of the oscillator is in inverse proportion to the current flowing through the current control type inverter and the frequency of the oscillator, so that the low-frequency current control type ring oscillator 10 is compared with a common ring oscillator, not only is the consumed circuit resource reduced, but also the random jitter is increased.
As shown in fig. 4, a circuit diagram of the high-frequency coupled ring oscillator in this embodiment is shown. As can be seen from the figure, the high-frequency coupled ring oscillator 11 is constituted by 8 not gate inverters, respectively: the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter are connected in the following manner:
the output end of the first inverter 1101 is connected to the input end of the second inverter 1102 and the input end of the sixth inverter 1106, the output end of the second inverter 1102 is connected to the input end of the third inverter 1103 and the input end of the seventh inverter 1107, the output end of the seventh inverter 1107 is connected to the input end of the first inverter 1101, the output end of the sixth inverter 1106 and the output end of the third inverter 1103 are connected to the input end of the fourth inverter 1104, the output end of the fourth inverter 1104 is connected to the input end of the eighth inverter 1108 and the input end of the first inverter 1101, the output end of the eighth inverter 1108 is connected to the input end of the third inverter 1103, the output end of the sixth inverter 1106 is connected to the input end of the fifth inverter 1106, and the output end of the fifth inverter 1105 is connected to the input end of the sixth inverter 1106.
Referring to fig. 4, the difference between the high-frequency coupled ring oscillator 11 and the general ring oscillator is that the high-frequency coupled ring oscillator can output four signals with the same frequency and 90 degrees phase difference at four nodes S1, S2, S3, and S4, which are respectively: 0 degrees, 90 degrees, 180 degrees, 270 degrees, the S3 signal is delayed 180 degrees from the S1 signal and the S4 signal is delayed 180 degrees from the S2 signal, as known from the circuit configuration.
Generally speaking, the natural frequency constraint between two oscillators introduces periodicity in the output bit stream, and the cost of eliminating the periodicity is that a more complex post-processing circuit is required, and if only a single low frequency signal samples a single high frequency signal, the output bit stream is easily interfered by the periodicity between the two signals, which is shown to have a certain degree of predictability.
Therefore, the embodiment adopts a symmetrical sampling scheme of sampling the double high-frequency signals by the single low-frequency signals, and the two high-frequency signals are mutually symmetrical due to 180 degrees of phase difference, and the periodic interference between the low-frequency signals and the high-frequency signals can be effectively eliminated after exclusive OR logic is carried out on the two paths of sampling results. Specifically, a group of signals with the same frequency and 180 degrees phase difference, such as (S1, S3) or (S2, S4), are randomly selected as the first high-frequency signal and the second high-frequency signal, and the phase delay is 180, so that symmetrical sampling can be realized.
Compared with the conventional single low-frequency oscillation signal sampling single high-frequency signal serving as the entropy extraction, the embodiment changes the conventional single sampling inside the entropy extraction circuit into symmetrical sampling so as to eliminate the inherent periodicity of the common single-channel oscillator sampling scheme on the output sequence, reduce the sensitivity of the entropy extraction process on the frequency change of the oscillator, reduce the requirement of the true random number generator on the post-processing circuit and improve the noise extraction efficiency of the low-frequency oscillation signal.
As shown in fig. 5, which is a specific circuit diagram of the multi-stage xor chain circuit in this embodiment, it can be seen that the multi-stage xor chain circuit 30 includes: an input circuit including a first D flip-flop 3011, and a plurality of single-stage exclusive-or circuits each including: the output end of the clock signal D trigger is connected with the first input end of the exclusive-OR circuit, the second input end of the exclusive-OR circuit is used as the input end of the current single-stage exclusive-OR circuit, and the output end of the exclusive-OR circuit is used as the output end of the current single-stage exclusive-OR circuit;
the output end (namely clock signal) of the low-frequency current control type ring oscillator is respectively connected with the clock signal input end of the first D trigger 3011 and the clock signal input ends of the plurality of clock signal D triggers; the output end of the first D flip-flop 3011 is connected to the input end of the first single-stage xor circuit 3021, the output end of the current single-stage xor circuit is sequentially connected to the input end of the next single-stage xor circuit, and the output end of the last single-stage xor circuit 3022 is used as the output end of the multi-stage xor circuit 30 for outputting the true random number bit stream.
In one embodiment, two single-stage exclusive OR circuits are selected as the post-processing circuits.
In the implementation, a single-stage exclusive-or circuit can be added on the basis of actual needs to form a longer multi-stage exclusive-or circuit, and adjacent bits of an original bit stream are exclusive-or processed by the multi-stage exclusive-or circuit, so that the statistical non-uniformity of the original bit stream caused by non-random factors can be regulated under the condition that an entropy source is not influenced, and the method is also used for eliminating the periodicity caused by the non-random factors. In this embodiment, the multi-stage exclusive-or circuit 30 is simple to implement, and can effectively improve the statistical properties of the bit stream without affecting entropy.
In this embodiment, from the perspective of the whole true random number generator, the requirement of the true random number generator on the post-processing circuit is reduced by symmetrical sampling, and the true random number generator can be realized without excessively considering the frequency constraint between the low-frequency signal and the high-frequency signal, in other words, the symmetrical sampling not only reduces the design difficulty of the whole circuit, but also does not consume more circuit resources, and meanwhile, the existing average level can be achieved in the aspects of the generation rate, the power consumption and the like.
In addition, the invention also provides a device for generating a true random number by using the circuit of the true random number generator according to any one of the embodiment.
The invention improves the noise extraction efficiency of the low-frequency oscillation signal by using the symmetrical output of the coupled ring oscillator as the high-frequency oscillation signal, reduces the requirement on a post-processing circuit from the whole of the true random number generator, realizes the reduction of circuit resource consumption, reduces the realization difficulty and simultaneously meets the requirements of the generation rate and the power consumption.
The above embodiments are only for illustrating the technical solution of the present invention, not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention, and are intended to be included within the scope of the appended claims and description.
Claims (7)
1. A circuit of a true random number generator, comprising: an entropy extraction circuit and a post-processing circuit;
the entropy extraction circuit generates an original bit stream and sends the original bit stream to the post-processing circuit, and the post-processing circuit outputs a true random number bit stream;
the entropy extraction circuit includes: the low-frequency current control type ring oscillator, the high-frequency coupling ring oscillator, the entropy extraction first D trigger, the entropy extraction second D trigger and the entropy extraction exclusive-OR gate circuit, wherein the low-frequency current control type ring oscillator generates a clock signal and sends the clock signal to the entropy extraction first D trigger and the entropy extraction second D trigger, the high-frequency coupling ring oscillator generates a first high-frequency signal and sends the first high-frequency signal to the entropy extraction first D trigger, and generates a second high-frequency signal and sends the second high-frequency signal to the entropy extraction second D trigger, the output ends of the entropy extraction first D trigger and the entropy extraction second D trigger are connected to serve as inputs of the entropy extraction exclusive-OR gate circuit, the entropy extraction exclusive-OR gate circuit outputs the original bit stream, and the clock signal serves as an entropy source;
the post-processing circuit is a multi-stage exclusive-or chain circuit, and the clock signal is connected with the input end of the multi-stage exclusive-or chain circuit;
the high-frequency coupled ring oscillator consists of 8 inverters, which are respectively: the first inverter, the second inverter, the third inverter, the fourth inverter, the fifth inverter, the sixth inverter, the seventh inverter and the eighth inverter specifically include:
the output end of the first inverter is respectively connected with the input end of the second inverter and the input end of the sixth inverter, the output end of the second inverter is connected with the input end of the third inverter and the input end of the seventh inverter, the output end of the seventh inverter is connected with the input end of the first inverter, the output end of the sixth inverter and the output end of the third inverter are respectively connected with the input end of the fourth inverter, the output end of the fourth inverter is respectively connected with the input end of the eighth inverter and the input end of the first inverter, the output end of the eighth inverter is connected with the input end of the third inverter, the output end of the sixth inverter is connected with the input end of the fifth inverter, and the output end of the fifth inverter is connected with the input end of the sixth inverter.
2. The circuit of claim 1, further comprising a delay unit, wherein an output terminal of the low-frequency current-controlled ring oscillator is connected to an input terminal of the delay unit, and is configured to transmit the clock signal to the delay unit, and an output terminal of the delay unit is connected to an input terminal of the multi-stage xor-link circuit.
3. The circuit of claim 1, wherein the low frequency current controlled ring oscillator is formed by connecting at least 5 current controlled inverters of identical structure, the current controlled inverters comprising: the first field effect transistor, the second field effect transistor, the third field effect transistor and the fourth field effect transistor, and specifically:
the grid electrode of the first field effect tube is connected with a first bias voltage power supply, the source electrode of the first field effect tube is connected with a power supply, the drain electrode of the first field effect tube is connected with the source electrode of the second field effect tube, the drain electrode of the second field effect tube is connected with the drain electrode of the third field effect tube, the grid electrode of the second field effect tube is connected with the grid electrode of the third field effect tube, the source electrode of the third field effect tube is connected with the drain electrode of the fourth field effect tube, the grid electrode of the fourth field effect tube is connected with a second bias voltage power supply, the source electrode of the fourth field effect tube is grounded, the output end of the current control type inverter is the drain electrode of the second field effect tube, and the input end of the current control type inverter is the grid electrode of the second field effect tube;
the output end of the current control type inverter is used as the input end of the current control type inverter of the next stage;
the output end of the low-frequency current control type ring oscillator is the output end of the current control type inverter of the last stage and is connected with the input end of the current control type inverter of the first stage.
4. The circuit of claim 3, wherein the first fet and the second fet are P-fets, and the third fet and the fourth fet are N-fets.
5. The circuit of claim 1, wherein the first high frequency signal and the second high frequency signal have a phase delay of 180 degrees.
6. The circuit of claim 1, wherein the multi-stage exclusive-or circuit comprises: an input circuit and a plurality of single-stage exclusive-or circuits, the input circuit including a first D flip-flop, the plurality of single-stage exclusive-or circuits respectively including: the output end of the clock signal D trigger is connected with the first input end of the exclusive-OR circuit, the second input end of the exclusive-OR circuit is used as the input end of the current single-stage exclusive-OR circuit, and the output end of the exclusive-OR circuit is used as the output end of the current single-stage exclusive-OR circuit;
the output end of the low-frequency current control type ring oscillator is respectively connected with the clock signal input end of the first D trigger and the clock signal input ends of a plurality of clock signal D triggers; the original bit stream is connected with the input end of the first D trigger, the output end of the first D trigger is connected with the input end of the first single-stage exclusive-OR circuit, the output end of the current single-stage exclusive-OR circuit is sequentially connected with the input end of the next single-stage exclusive-OR circuit, and the output end of the last single-stage exclusive-OR circuit is used as the output end of the multi-stage exclusive-OR circuit and is used for outputting the true random number bit stream.
7. Apparatus for a true random number generator, wherein a true random number is generated using a circuit of a true random number generator as claimed in any one of claims 1 to 6.
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