CN111338603A - True random number generator and electronic equipment - Google Patents
True random number generator and electronic equipment Download PDFInfo
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/58—Random or pseudo-random number generators
- G06F7/588—Random number generators, i.e. based on natural stochastic processes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/30—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator
- H03B5/32—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
Abstract
The embodiment of the application provides a true random number generator and electronic equipment, including: the circuit comprises a first up-sampling circuit, a first down-sampling circuit, a second up-sampling circuit and a second down-sampling circuit; the first up-sampling circuit outputs a first up-sampled signal; the first down-sampling circuit outputs a first down-sampled signal; the second up-sampling circuit outputs a second up-sampled signal; the second down-sampling circuit outputs a second down-sampled signal; and the post-processing circuit is used for carrying out XOR operation on one of the first up-sampling signal and the first down-sampling signal and one of the second up-sampling signal and the second down-sampling signal to generate and output a true random number signal, wherein the two signals which are subjected to XOR operation are signals obtained by sampling according to different high-frequency clock signals respectively, the independence between the two signals is higher, the randomness of the obtained true random number signal is improved, and the output sequence of the true random number signal can meet the independent and uniformly distributed random number characteristic.
Description
Technical Field
The embodiment of the application relates to the technical field of information security, in particular to a true random number generator and electronic equipment.
Background
With the widespread use of network technology, mobile payment has become more widespread, and electronic devices are increasingly used for storing, processing and transmitting data containing key information, such as mobile payment information, so that the importance of information security is increasing. To avoid information being stolen during the transmission process, the information generally needs to be encrypted by using a security key before being transmitted.
As an essential part of cryptographic systems, True Random Number Generators (TRNGs) are commonly used for generating high quality Random number sequences required in cryptographic systems, e.g. for generating security keys and the like.
Disclosure of Invention
Embodiments of the present invention provide a true random number generator and an electronic device, which overcome the drawbacks of the prior art.
A first aspect of embodiments of the present application provides a true random number generator, which includes a first up-sampling circuit, a first down-sampling circuit, a second up-sampling circuit, and a second down-sampling circuit;
the first up-sampling circuit receives a first high-frequency clock signal output by the first high-frequency oscillator and a low-frequency clock signal output by the low-frequency oscillator, and is used for performing rising edge sampling on the first high-frequency clock signal according to the low-frequency clock signal and outputting a first up-sampling signal;
the first down-sampling circuit receives a first high-frequency clock signal and a low-frequency clock signal, and is used for performing falling edge sampling on the first high-frequency clock signal according to the low-frequency clock signal and outputting a first down-sampling signal;
the second up-sampling circuit receives a second high-frequency clock signal and a low-frequency clock signal output by the second high-frequency oscillator, and is used for sampling the rising edge of the second high-frequency clock signal according to the low-frequency clock signal and outputting a second up-sampling signal;
the second down-sampling circuit receives a second high-frequency clock signal and a low-frequency clock signal, and is used for performing falling edge sampling on the second high-frequency clock signal according to the low-frequency clock signal and outputting a second down-sampling signal;
the post-processing circuit receives the first up-sampling signal, the first down-sampling signal, the second up-sampling signal and the second down-sampling signal, and the post-processing circuit is used for carrying out XOR operation on one of the first up-sampling signal and the first down-sampling signal and one of the second up-sampling signal and the second down-sampling signal so as to generate and output a true random number signal.
In the true random number generator provided in the embodiments of the present application, the first high frequency oscillator, the second high frequency oscillator, and the low frequency oscillator are different oscillators, and therefore the first high frequency clock signal, the second high frequency clock signal, and the low frequency clock signal are clock signals that are not correlated with each other, the first high frequency clock signal and the second high frequency clock signal are respectively subjected to rising edge sampling and falling edge sampling by the low frequency clock signal, and the obtained first up-sampling signal, first down-sampling signal, second up-sampling signal, and second down-sampling signal are not correlated with each other. And then, one of the first up-sampling signal and the first down-sampling signal and one of the second up-sampling signal and the second down-sampling signal are subjected to exclusive-or operation through the post-processing circuit, the two signals subjected to exclusive-or operation are not related to each other, the sampling modes can be set to be the same or different, and the two signals are obtained by sampling according to different high-frequency clock signals respectively, so that the independence between the two signals subjected to exclusive-or operation is higher, the randomness of a true random number signal obtained through exclusive-or operation is improved, and meanwhile, the output sequence of the true random number signal can meet the independent and uniformly distributed random number characteristics through exclusive-or operation.
Drawings
Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:
FIG. 1 is a schematic circuit block diagram of a true random number generator provided by an embodiment of the present application;
FIG. 2 is a schematic circuit block diagram of a true random number generator provided by an embodiment of the present application;
FIG. 3 is a schematic circuit block diagram of a true random number generator provided by an embodiment of the present application;
FIG. 4 is a schematic circuit block diagram of a true random number generator provided by an embodiment of the present application;
FIG. 5 is a schematic block diagram of an electronic device incorporating a true random number generator according to embodiments of the present application.
Detailed Description
The following further describes specific implementation of the embodiments of the present invention with reference to the drawings.
In the related art, random number generators are mainly classified into two types: pseudo-random number generators and true-random number generators. The random sequence obtained by calculation with a deterministic algorithm is called a pseudo-random number, and if an attacker has enough calculation capacity, the generation rule of the pseudo-random number can be completely predicted, so that the method is generally applied to occasions with lower security requirements. The true random number is generated by a physical method, the natural randomness of the real world is selected, and the true random number has the advantages of being unpredictable and irreproducible outside and the like, can better protect the transmission of information and is widely applied to the field of information safety.
The core of a true random number generator must be an essentially random physical process selected from natural randomness. There are many ways to implement true random number generators, such as discrete time chaos, direct noise amplification, oscillatory sampling, metastable sampling, etc. The oscillation sampling method is most widely applied due to the simple implementation method and good data randomness. However, the randomness of the random number signals generated by the true random number generator realized according to the oscillation sampling method is not high, the output sequence of the random number signals cannot meet the characteristics of independent and uniformly distributed random numbers, and the cracking rate of the random number signals is higher than that of the random number signals generated by the true random number generator realized according to a discrete time chaos method, a direct noise amplification method, an oscillation sampling method, a metastable state sampling method and the like, so that the probability of data leakage during transmission is improved, and the user experience is damaged.
In view of this, embodiments of the present application provide a true random number generator and an electronic device, so as to overcome the technical defects in the prior art that the randomness of a random number signal is not high, and the output sequence of the random number signal satisfies the characteristics of independent and uniformly distributed random numbers.
In the true random number generator provided in the embodiments of the present application, the first high frequency oscillator, the second high frequency oscillator, and the low frequency oscillator are different oscillators, and therefore the first high frequency clock signal, the second high frequency clock signal, and the low frequency clock signal are clock signals that are not correlated with each other, the first high frequency clock signal and the second high frequency clock signal are respectively subjected to rising edge sampling and falling edge sampling by the low frequency clock signal, and the obtained first up-sampling signal, first down-sampling signal, second up-sampling signal, and second down-sampling signal are not correlated with each other. And then, one of the first up-sampling signal and the first down-sampling signal and one of the second up-sampling signal and the second down-sampling signal are subjected to exclusive-or operation through the post-processing circuit, the two signals subjected to exclusive-or operation are not related to each other, the sampling modes can be set to be the same or different, and the two signals are obtained by sampling according to different high-frequency clock signals respectively, so that the independence between the two signals subjected to exclusive-or operation is higher, the randomness of a true random number signal obtained through exclusive-or operation is improved, and meanwhile, the output sequence of the true random number signal can meet the independent and uniformly distributed random number characteristics through exclusive-or operation.
The following further describes specific implementations of embodiments of the present application with reference to the drawings of the embodiments of the present application.
Example one
Fig. 1 is a schematic circuit structure diagram of a true random number generator according to an embodiment of the present application, and as shown in fig. 1, the true random number generator according to an embodiment of the present application includes: a first up-sampling circuit 101, a first down-sampling circuit 102, a second up-sampling circuit 103, and a second down-sampling circuit 104.
The first up-sampling circuit 101 receives a first high-frequency clock signal output by the first high-frequency oscillator 201 and a low-frequency clock signal output by the low-frequency oscillator 203, and the first up-sampling circuit 101 is configured to perform rising edge sampling on the first high-frequency clock signal according to the low-frequency clock signal and output a first up-sampling signal.
The first down-sampling circuit 102 receives a first high-frequency clock signal and a low-frequency clock signal, and the first down-sampling circuit 102 is configured to perform falling edge sampling on the first high-frequency clock signal according to the low-frequency clock signal and output a first down-sampling signal.
The second up-sampling circuit 103 receives the second high-frequency clock signal and the low-frequency clock signal output by the second high-frequency oscillator 202, and the second up-sampling circuit 103 is configured to perform rising edge sampling on the second high-frequency clock signal according to the low-frequency clock signal and output a second up-sampling signal;
the second downsampling circuit 104 receives the second high frequency clock signal and the low frequency clock signal, and the second downsampling circuit 104 is configured to perform falling edge sampling on the second high frequency clock signal according to the low frequency clock signal and output a second downsampled signal.
The post-processing circuit 105 receives a first up-sampled signal, a first down-sampled signal, a second up-sampled signal, and a second down-sampled signal. The post-processing circuit 105 is configured to perform an exclusive-or operation on one of the first up-sampled signal and the first down-sampled signal and one of the second up-sampled signal and the second down-sampled signal to generate and output a true random number signal.
Illustratively, as shown in fig. 1, a first input terminal 1011 of the first up-sampling circuit 101 is turned on with an output terminal 2011 of the first high-frequency oscillator 201, and the first input terminal 1011 of the first up-sampling circuit 101 receives the first high-frequency clock signal output by the first high-frequency oscillator 201; the second input terminal 1012 of the first up-sampling circuit 101 is connected to the output terminal 2031 of the low frequency oscillator 203, and the second input terminal 1012 of the first up-sampling circuit 101 receives the low frequency clock signal output by the low frequency oscillator 203. The output 1013 of the first upsampling circuit 101 is conducted to the first input 1051 of the post-processing circuit 105. A first input 1051 of the post-processing circuit 105 receives the first up-sampled signal output by the output 1013 of the first up-sampling circuit 101.
The first input end 1021 of the first down-sampling circuit 102 is conducted with the output end 2011 of the first high-frequency oscillator 201, the first input end 1021 of the first down-sampling circuit 102 receives the first high-frequency clock signal output by the first high-frequency oscillator 201, the second input end 1022 of the first down-sampling circuit 102 is conducted with the output end 2031 of the low-frequency oscillator 203, the second input end 1022 of the first down-sampling circuit 102 receives the low-frequency clock signal output by the low-frequency oscillator 203, and the output end 1023 of the first down-sampling circuit 102 is conducted with the second input end 1052 of the post-processing circuit 105. A second input 1052 of the post-processing circuit 105 receives the first down-sampled signal output by the output 1023 of the first down-sampling circuit 102.
The first input terminal 1031 of the second up-sampling circuit 103 is conducted with the output terminal 2021 of the second high-frequency oscillator 202, the first input terminal 1031 of the second up-sampling circuit 103 receives the second high-frequency clock signal output by the second high-frequency oscillator 202, the second input terminal 1032 of the second up-sampling circuit 103 is conducted with the output terminal 2031 of the low-frequency oscillator 203, the second input terminal 1032 of the second up-sampling circuit 103 receives the low-frequency clock signal output by the low-frequency oscillator 203, and the output terminal 1033 of the second up-sampling circuit 103 is conducted with the third input terminal 1053 of the post-processing circuit 105. A third input 1053 of the post-processing circuit 105 receives the second up-sampled signal output by the output 1033 of the second up-sampling circuit 103.
The first input terminal 1041 of the second downsampling circuit 104 is connected to the output terminal 2021 of the second high-frequency oscillator 202, the first input terminal 1041 of the second downsampling circuit 104 receives the second high-frequency clock signal output by the second high-frequency oscillator 202, the second input terminal 1042 of the second downsampling circuit 104 is connected to the output terminal 2031 of the low-frequency oscillator 203, the second input terminal 1042 of the second downsampling circuit 104 receives the low-frequency clock signal output by the low-frequency oscillator 203, and the output terminal 1043 of the second downsampling circuit 104 is connected to the fourth input terminal 1054 of the post-processing circuit 105. A fourth input 1054 of the post-processing circuit 105 receives the second down-sampled signal output by the output 1043 of the second down-sampling circuit 104.
The output 1055 of the post-processing circuit 105 outputs a true random number signal.
Specifically, phase jitter (jitter) is a random phenomenon in an oscillator caused by thermal noise, and is also a noise in nature, and is a random variable conforming to a gaussian distribution. Since the phase jitter of the first high-frequency oscillator, the second high-frequency oscillator, and the low-frequency oscillator is random, the output sequence of the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal generated by performing rising edge sampling and falling edge sampling on the first high-frequency clock signal generated by the first high-frequency oscillator and the second high-frequency clock signal generated by the second high-frequency oscillator, respectively, based on the low-frequency clock signal generated by the low-frequency oscillator is random, and the output sequence of the true number signal generated by performing exclusive-or operation on one of the first up-sampling signal and the first down-sampling signal and one of the second up-sampling signal and the second down-sampling signal is random.
The first up-sampling circuit 101 is configured to generate a first high-frequency clock signal by performing rising edge sampling on the first high-frequency clock signal according to the low-frequency clock signal, the frequency of the first up-sampling signal is the same as the frequency of the low-frequency clock signal, the first down-sampling circuit 103 is configured to generate a first low-frequency clock signal by performing falling edge sampling on the first high-frequency clock signal according to the low-frequency clock signal, and the frequency of the first down-sampling signal is the same as the frequency of the low-frequency clock signal. For the same reason, the frequency of the second up-sampled signal and the frequency of the second down-sampled signal are both the same as the frequency of the low-frequency clock signal. The frequency of the true random number signal generated by performing an exclusive or operation on one of the first up-sampled signal and the first down-sampled signal and one of the second up-sampled signal and the second down-sampled signal is the same as the frequency of the low frequency clock signal.
Illustratively, the frequency of the low frequency clock signal is 32 khz, the frequencies of the first high frequency clock signal and the second high frequency clock signal are greater than or equal to 80 mhz and less than or equal to 100 mhz, and the frequency of the true random number signal is 32 khz.
In the post-processing circuit, one bit of data is generated according to the two bits of data when the XOR operation is carried out, so that the correlation between the previous bit and the next bit in the output sequence of the true random number signal can be reduced, and the previous bit and the next bit in the output sequence of the true random number signal are mutually independent.
In the post-processing circuit, the output sequence of the true random number signal obtained by performing the exclusive or operation can satisfy the uniformly distributed random number characteristic. Illustratively, the following processing circuit performs an exclusive or operation on the first upsampled signal and the second downsampled signal, where probabilities of "0" and "1" appearing in an output sequence of any one of the first upsampled signal and the second downsampled signal are 0.5C and 0.5C, respectively, where C < 1, C is a parameter for balancing independence between the first upsampled signal and the second downsampled signal, and the smaller the value of C, the better the independence between the first upsampled signal and the second downsampled signal, and the less the first upsampled signal and the second downsampled signal are correlated. The first up-sampling signal and the second down-sampling signal are subjected to exclusive-or operation to generate a true random number signal, the probability of 0 appearing in the true random number signal is that the probability of 1 appearing in the true random number signal is that the probability is closer to 0.5 compared with 0.5C, and therefore the output sequences of 0 and 1 of the true random number signal generated after the exclusive-or operation are uniformly distributed.
The first high-frequency oscillator outputting the first high-frequency clock signal, the second high-frequency oscillator outputting the second high-frequency clock signal, and the low-frequency oscillator outputting the low-frequency clock signal are different oscillators, and can be regarded as a timing instrument physically existing in different entities, and the first high-frequency clock signal, the second high-frequency clock signal, and the low-frequency clock signal are not related to each other, that is, the first high-frequency clock signal, the second high-frequency clock signal, and the low-frequency clock signal are not related to each other, and another clock signal cannot be obtained according to one clock signal. The first up-sampling signal and the first down-sampling signal are obtained by sampling the first high-frequency clock signal according to the low-frequency clock signal, and the second up-sampling signal and the second down-sampling signal are obtained by sampling the second high-frequency clock signal according to the low-frequency clock signal, so that the first up-sampling signal, the first down-sampling signal, the second up-sampling signal and the second down-sampling signal are not correlated with each other. The post-processing circuit performs exclusive-or operation on one of the first up-sampling signal and the first down-sampling signal and one of the second up-sampling signal and the second down-sampling signal, wherein the two signals subjected to exclusive-or operation are not related to each other, and the sampling modes can be set to be the same or different and are signals obtained by sampling according to different high-frequency clock signals respectively. Compared with two signals obtained by sampling according to the same high-frequency clock signal, the signals obtained by sampling according to different high-frequency clock signals are higher in independence. The randomness of the true random number signal generated by the post-processing circuit through the exclusive-or operation is high.
In the true random number generator provided in the embodiments of the present application, the first high frequency oscillator, the second high frequency oscillator, and the low frequency oscillator are different oscillators, and therefore the first high frequency clock signal, the second high frequency clock signal, and the low frequency clock signal are clock signals that are not correlated with each other, the first high frequency clock signal and the second high frequency clock signal are respectively subjected to rising edge sampling and falling edge sampling by the low frequency clock signal, and the obtained first up-sampling signal, first down-sampling signal, second up-sampling signal, and second down-sampling signal are not correlated with each other. And then, one of the first up-sampling signal and the first down-sampling signal and one of the second up-sampling signal and the second down-sampling signal are subjected to exclusive-or operation through the post-processing circuit, the two signals subjected to exclusive-or operation are not related to each other, the sampling modes can be set to be the same or different, and the two signals are obtained by sampling according to different high-frequency clock signals respectively, so that the independence between the two signals subjected to exclusive-or operation is higher, the randomness of a true random number signal obtained through exclusive-or operation is improved, and meanwhile, the output sequence of the true random number signal can meet the independent and uniformly distributed random number characteristics through exclusive-or operation.
Optionally, in an embodiment of the present application, fig. 2 is a schematic circuit structure diagram of a true random number generator provided in the embodiment of the present application, as shown in fig. 2, the post-processing circuit 105 includes a first switch 301, a second switch 302, and an exclusive or gate 303, a first input terminal 3011 of the first switch 301 receives a first up-sampling signal, a second input terminal 3012 of the first switch 302 receives a first down-sampling signal, the first switch 301 is configured to output the first switch signal, and the first switch signal is the first up-sampling signal or the first down-sampling signal. The first input terminal 3021 of the second switch 302 receives a second up-sampled signal, the second input terminal 3022 of the second switch 302 receives a second down-sampled signal, and the second switch 302 is configured to output a second switch signal, where the second switch signal is a second up-sampled signal or a second down-sampled signal. The first input terminal 3031 of the xor gate 303 receives the first switching signal, the second input terminal 3032 of the xor gate 303 receives the second switching signal, and the xor gate 303 is configured to perform an xor operation on the first switching signal and the second switching signal to generate and output a true random number signal.
Illustratively, as shown in fig. 2, the first input terminal 3011 of the first switch 301 is conducted with the output terminal 1013 of the first upsampling circuit 101 through the first input terminal 1051 of the post-processing circuit 105, and the first input terminal 3011 of the first switch 301 receives the first upsampling signal. The second input 3012 of the first switch 301 is conducted to the output 1023 of the first down-sampling circuit 102 through the second input 1052 of the post-processing circuit 105, and the second input 3012 of the first switch 301 receives the first down-sampling signal.
The first input terminal 3021 of the second switch 302 is connected to the output terminal 1033 of the second upsampling circuit 103 via the third input terminal 1053 of the post-processing circuit 105, and the first input terminal 3021 of the second switch 302 receives the second upsampled signal. A second input port 3022 of the second switch 302 is connected to the output port 1043 of the second downsampling circuit 104 through a fourth input port 1054 of the post-processing circuit 105, and the second input port 3022 of the second switch 302 receives the second downsampled signal.
The first input terminal 3031 of the xor gate 303 is conducted with the output terminal 3013 of the first switch 301, the second input terminal 3032 of the xor gate 303 is conducted with the output terminal 3033 of the second switch 302, and the xor gate 303 outputs the true random number signal through the output terminal 3033.
Illustratively, the first switch 301 and the second switch 302 are single-pole double-throw switches. The first switching unit 301 is configured such that when the first input terminal 3011 of the first switching unit 301 and the output terminal 3033 of the first switching unit 301 are turned on, the first switching signal output by the output terminal 3013 of the first switching unit 301 is the first up-sampling signal, and at this time, the signal input to the first input terminal 3031 of the xor gate 303 is the first up-sampling signal.
The first switching unit 301 is configured such that when the second input terminal 3012 of the first switching unit 301 and the output terminal 3033 of the first switching unit 301 are turned on, the first switching signal output by the output terminal 3013 of the first switching unit 301 is the first down-sampling signal, and at this time, the signal input to the first input terminal 3031 of the xor gate 303 is the first down-sampling signal.
The second switch unit 302 is configured such that when the first input terminal 3021 of the second switch unit 302 and the output terminal 3023 of the second switch unit 302 are turned on, the second switch signal output by the output terminal 3023 of the second switch unit 302 is the second up-sampling signal, and at this time, the signal input to the second input terminal 3032 of the xor gate 303 is the second up-sampling signal.
The second switching unit 302 is configured such that when the second input terminal 3022 of the second switching unit 302 and the output terminal 3023 of the second switching unit 302 are turned on, the second switching signal output by the output terminal 3023 of the second switching unit 302 is the second down-sampling signal, and at this time, the signal input to the second input terminal 3032 of the xor gate 303 is the second down-sampling signal.
In the true random number generator provided by the embodiment of the application, the post-processing circuit includes a first switch, a second switch and an xor gate, and the first switch and the second switch can be configured to be in different on states, so that sampling modes of two signals input to the xor gate can be the same (both the two signals are up-sampling signals or both down-sampling signals) or different (one signal is up-sampling signal, and the other signal is down-sampling signal), and the sampling modes of the two signals subjected to xor operation can be conveniently selected.
Optionally, in an embodiment of the present application, the period value of the first high-frequency clock signal and the period value of the second high-frequency clock signal are high-frequency clock period values, and a ratio of a standard deviation value of a phase jitter of the low-frequency clock signal to the high-frequency clock period value is greater than or equal to 100 and less than or equal to 1000.
Specifically, when the first high-frequency clock signal and the second high-frequency clock signal are respectively subjected to rising edge sampling or falling edge sampling according to the low-frequency clock signal, the phase jitter of the low-frequency oscillator generating the low-frequency clock signal, the phase jitter of the first high-frequency oscillator generating the first high-frequency clock signal, and the phase jitter of the second high-frequency oscillator generating the second high-frequency clock signal are random, wherein the phase jitter of the first high-frequency oscillator and the second high-frequency oscillator is negligible relative to the phase jitter of the low-frequency oscillator, so that the randomness of the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal mainly depends on the standard variance value (namely root mean square value) of the phase jitter of the low-frequency oscillator relative to the period value of the first high-frequency oscillator and the second high-frequency oscillator. The period values of the first high-frequency clock signal and the second high-frequency clock signal are high-frequency clock period values, and when the ratio of the standard variance value of the phase jitter of the low-frequency clock signal to the high-frequency clock period value is greater than or equal to 100 and less than or equal to 1000, the output sequences of the first up-sampling signal, the first down-sampling signal, the second up-sampling signal and the second down-sampling signal are high in randomness.
Example two
On the basis of the first embodiment, as shown in fig. 3, fig. 3 is a schematic circuit structure diagram of the true random number generator provided in the second embodiment of the present application, the true random number generator further includes a difference circuit 106, an input end 1061 of the difference circuit 106 receives a true random number signal, a first output end 1062 of the difference circuit 106 outputs the true random number signal, a second output end 1063 of the difference circuit 106 outputs a difference output signal, and the difference output signal and the true random number signal form a pair of difference signals.
Illustratively, as shown in FIG. 3, the input 1061 of the differential circuit 106 is in conductive communication with the output 1055 of the post-processing circuit 105.
In the true random number generator provided by the embodiment of the application, the differential circuit 106 receives a true random number signal, outputs the true random number signal and forms a differential output signal of a pair of differential signals with the true random number signal, so that the anti-interference capability of the true random number signal and the differential output signal in the signal transmission process is enhanced, meanwhile, verification can be performed according to the true random number signal and the differential output signal, and errors caused by malicious attack on the true random number signal or tampering of signal routing are avoided.
Alternatively, in an embodiment of the present application, as shown in fig. 4, fig. 4 is a schematic circuit structure diagram of a true random number generator provided in the embodiment of the present application, the differential circuit 106 includes an inverter 107, an input end 1071 of the inverter 107 receives a true random number signal, and an output end 1072 of the inverter 107 outputs a differential output signal.
Illustratively, the input end 1071 of the inverter 107 is conducted to the output end 1055 of the post-processing circuit 105 through the input end 1061 of the differential circuit 106, so that the input end 1071 of the inverter 107 inputs the true random number signal, the output end 1072 of the inverter 107 is conducted to the second output end 1063 of the differential circuit 106, and the output end 1061 of the differential circuit 106 is conducted to the first output end 1062 of the differential circuit 106. The inverter 107 inverts the true random number signal input at the input 1071 of the inverter 107 so that the differential output signal output from the output of the inverter 107 has the same frequency and an opposite phase as the true random number signal, and the differential output signal and the true random number signal form a pair of differential signals.
In the true random number generator provided by the embodiment of the present application, the differential circuit 106 includes the inverter 107, the input end 1071 of the inverter 107 receives the true random number signal, the inverter 107 inverts the true random number signal, so that the differential output signal output by the output end 1072 of the inverter 107 is opposite in phase and same in frequency as the true random number signal, and the differential output signal and the true random number signal form a pair of differential signals.
EXAMPLE III
Fig. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application, and as shown in fig. 5, an electronic device 300 according to a third embodiment of the present application includes a low-frequency oscillator 203, a first high-frequency oscillator 201, a second high-frequency oscillator 202, and a true random number generator 301 according to any one of the embodiments of the present application, where the first high-frequency oscillator 201 is configured to output a first high-frequency clock signal, and the second high-frequency oscillator 202 is configured to output a second high-frequency clock signal.
Illustratively, as shown in fig. 5, the first input terminal 3011 of the true random number generator 301 is connected to the output terminal 2011 of the first high frequency oscillator 201, and the first input terminal 1011 of the first up-sampling circuit 101 is connected to the output terminal 2011 of the first high frequency oscillator 201 through the first input terminal 3011 of the true random number generator 301, so as to receive the first high frequency clock signal output by the first high frequency oscillator 201. A first input end 1021 of the first down-sampling circuit 102 is conducted to an output end 2011 of the first high-frequency oscillator 201 through a first input end 3011 of the true random number generator 301, and receives the first high-frequency clock signal output by the first high-frequency oscillator 201.
The second input terminal 3012 of the true random number generator 301 is electrically connected to the output terminal 2021 of the second high-frequency oscillator 202, and the first input terminal 1031 of the second up-sampling circuit 103 is electrically connected to the output terminal 2021 of the second high-frequency oscillator 202 via the second input terminal 3012 of the true random number generator 301, and receives the second high-frequency clock signal output from the second high-frequency oscillator 202. The first input terminal 1041 of the second downsampling circuit 104 is connected to the output terminal 2021 of the second high-frequency oscillator 202 through the second input terminal 3012 of the true random number generator 301, and receives the second high-frequency clock signal output by the second high-frequency oscillator 202.
The third input 3013 of the true random number generator 301 is conducted to the output 2031 of the low frequency oscillator 203, and the second input 1012 of the first up-sampling circuit 101, the second input 1022 of the first down-sampling circuit 102, the second input 1032 of the second up-sampling circuit 103, and the second input 1042 of the second down-sampling circuit 104 are conducted to the output 2031 of the low frequency oscillator 203 through the third input 3013 of the true random number generator 301, so as to receive the low frequency clock signal output by the low frequency oscillator 203.
Exemplarily, the electronic device 300 may be a mobile communication terminal, a tablet computer, an intelligent wearable device, or the like. The electronic device 300 comprises a secure chip comprising a low frequency oscillator 203, a first high frequency oscillator 201 and a second high frequency oscillator 202. The low frequency oscillator 203 is a wake-up clock source of the security chip, the first high frequency oscillator 201 is a system reference clock source of the security chip, and the second high frequency oscillator 202 is another system reference clock source of the security chip.
An electronic apparatus provided by an embodiment of the present application includes a low frequency oscillator 203, a first high frequency oscillator 201, a second high frequency oscillator 202, and a true random number generator 301, the first high frequency oscillator 201 being configured to output a first high frequency clock signal, the second high frequency oscillator 202 being configured to output a second high frequency clock signal. The two signals for performing the exclusive-or operation in the true random number generator 301 are not related to each other, the sampling mode may be set to be the same or different, and the two signals obtained by sampling according to different high-frequency clock signals are obtained respectively.
Alternatively, in one embodiment of the present application, the types of the first high-frequency oscillator 201 and the second high-frequency oscillator 202 include a crystal oscillator, a phase-locked loop, a voltage-controlled oscillator.
In the electronic apparatus provided in the embodiment of the present application, the oscillator types of the first high-frequency oscillator 201 and the second high-frequency oscillator 202 include a crystal oscillator, a phase-locked loop, a voltage-controlled oscillator, wherein the phase jitter of the crystal oscillator, the phase locked loop, the voltage controlled oscillator is low compared to other types of oscillators, the randomness of the output sequences of the first up-sampling signal, the first down-sampling signal, the second up-sampling signal and the second down-sampling signal generated by respectively performing rising edge sampling and falling edge sampling on the first high-frequency clock signal and the second high-frequency clock signal according to the low-frequency clock signal is high, the randomness of the output sequence of the true random number signal generated by performing an exclusive-or operation on one of the first up-sampled signal and the first down-sampled signal and one of the second up-sampled signal and the second down-sampled signal is high.
Optionally, in an embodiment of the present application, the low frequency oscillator 203, the first high frequency oscillator 201, and the second high frequency oscillator 202 are relaxation oscillators. Typical values for the average current of the low frequency oscillator 203 are less than 100 nanoamperes, typical values for the average current of the first high frequency oscillator 201 and typical values for the average current of the second high frequency oscillator 202 are both greater than 500 microamperes.
Optionally, in an embodiment of the present application, the oscillator types of the first high frequency oscillator 201 and the second high frequency oscillator 202 are different from the oscillator type of the low frequency oscillator 203.
Illustratively, the first high-frequency oscillator 201 and the second high-frequency oscillator 202 are relaxation oscillators, and the oscillator types of the low-frequency oscillator 203 include a voltage-controlled oscillator, a phase-locked loop, and a crystal oscillator; or, the first high-frequency oscillator 201 and the second high-frequency oscillator 202 are both phase-locked loops, and the oscillator types of the low-frequency oscillator 203 include relaxation oscillator, voltage-controlled oscillator, and crystal oscillator; or, the first high-frequency oscillator 201 and the second high-frequency oscillator 202 are both crystal oscillators, and the oscillator types of the low-frequency oscillator 203 include a relaxation oscillator, a voltage-controlled oscillator, and a phase-locked loop; alternatively, the first high-frequency oscillator 201 and the second high-frequency oscillator 202 are both voltage-controlled oscillators, and the oscillator types of the low-frequency oscillator 203 include a relaxation oscillator, a phase-locked loop, and a crystal oscillator.
In the electronic device according to the embodiment of the present application, compared to the case where the first high-frequency oscillator 201, the second high-frequency oscillator 202, and the low-frequency oscillator 203 are of the same oscillator type, when the type of the first high-frequency oscillator 201 or the second high-frequency oscillator 202 is different from the type of the low-frequency oscillator 203, the independence between the first high-frequency oscillator 201 or the second high-frequency oscillator 202 and the low-frequency oscillator 203 is better, the independence between the first high-frequency clock signal or the second high-frequency clock signal and the low-frequency clock signal is better, the randomness of the output sequence of the first up-sampling signal, the first down-sampling signal, the second up-sampling signal, and the second down-sampling signal generated by performing the up-edge sampling and the down-edge sampling on the first high-frequency clock signal and the second high-frequency clock signal, respectively, and the first up-sampling signal, the second down-sampling signal, and the second down-sampling signal is, And the randomness of a true random number signal generated by performing an exclusive-or operation on one of the first down-sampled signals and one of the second up-sampled signals and the second down-sampled signals.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
Claims (10)
1. A true random number generator is characterized by comprising a first up-sampling circuit, a first down-sampling circuit, a second up-sampling circuit and a second down-sampling circuit;
the first up-sampling circuit receives a first high-frequency clock signal output by a first high-frequency oscillator and a low-frequency clock signal output by a low-frequency oscillator, and is used for performing rising edge sampling on the first high-frequency clock signal according to the low-frequency clock signal and outputting a first up-sampling signal;
the first down-sampling circuit receives the first high-frequency clock signal and the low-frequency clock signal, and is configured to perform falling edge sampling on the first high-frequency clock signal according to the low-frequency clock signal and output a first down-sampling signal;
the second up-sampling circuit receives a second high-frequency clock signal output by a second high-frequency oscillator and the low-frequency clock signal, and is used for performing rising edge sampling on the second high-frequency clock signal according to the low-frequency clock signal and outputting a second up-sampling signal;
the second down-sampling circuit receives the second high-frequency clock signal and the low-frequency clock signal, and is used for performing falling edge sampling on the second high-frequency clock signal according to the low-frequency clock signal and outputting a second down-sampling signal;
the post-processing circuit receives the first up-sampling signal, the first down-sampling signal, the second up-sampling signal and the second down-sampling signal, the post-processing circuit is used for right one of the first up-sampling signal and the first down-sampling signal, and the second up-sampling signal and one of the second down-sampling signal are subjected to exclusive-or operation to generate a true random number signal and output the true random number signal.
2. The true random number generator of claim 1 wherein the post-processing circuit comprises a first switch, a second switch, and an exclusive or gate;
a first input terminal of the first switch receives the first up-sampling signal, a second input terminal of the first switch receives the first down-sampling signal, the first switch is configured to output a first switch signal, and the first switch signal is the first up-sampling signal or the first down-sampling signal;
a first input terminal of the second switch receives the second up-sampled signal, a second input terminal of the second switch receives the second down-sampled signal, the second switch is configured to output a second switch signal, and the second switch signal is the second up-sampled signal or the second down-sampled signal;
the first input end of the exclusive-OR gate receives the first switch signal, the second input end of the exclusive-OR gate receives the second switch signal, and the exclusive-OR gate is used for carrying out exclusive-OR operation on the first switch signal and the second switch signal so as to generate and output the true random number signal.
3. The true random number generator of claim 1, further comprising a differential circuit having an input receiving the true random number signal, a first output outputting the true random number signal, and a second output outputting a differential output signal, the differential output signal and the true random number signal forming a pair of differential signals.
4. The true random number generator of claim 3, wherein the differential circuit comprises an inverter, an input of the inverter receiving the true random number signal, and an output of the inverter outputting the differential output signal.
5. The true random number generator of any one of claims 1-4 wherein the period value of the first high frequency clock signal and the period value of the second high frequency clock signal are high frequency clock period values and the ratio of the standard deviation value of the phase jitter of the low frequency clock signal to the high frequency clock period value is greater than or equal to 100 and less than or equal to 1000.
6. The true random number generator of any one of claims 1-4 wherein the low frequency clock signal has a frequency of 32K hertz and the first and second high frequency clock signals have a frequency greater than or equal to 80M hertz and less than or equal to 100M hertz.
7. An electronic device, comprising a low frequency oscillator for outputting a first high frequency clock signal, a first high frequency oscillator for outputting a second high frequency clock signal, a second high frequency oscillator for outputting a first high frequency clock signal, and the true random number generator of any one of claims 1-6.
8. The electronic device according to claim 7, wherein the oscillator types of the first high-frequency oscillator and the second high-frequency oscillator include a crystal oscillator, a phase-locked loop, a voltage-controlled oscillator.
9. The electronic device of claim 7, wherein the low frequency oscillator, the first high frequency oscillator, and the second high frequency oscillator are relaxation oscillators, wherein a typical value of an average current of the low frequency oscillator is less than 100 nanoamperes, and wherein a typical value of an average current of the first high frequency oscillator and a typical value of an average current of the second high frequency oscillator are each greater than 500 microamperes.
10. The electronic device according to claim 7, wherein the first high frequency oscillator and the second high frequency oscillator are relaxation oscillators, and oscillator types of the low frequency oscillator include a voltage controlled oscillator, a phase locked loop, and a crystal oscillator;
or, the first high-frequency oscillator and the second high-frequency oscillator are both phase-locked loops, and the oscillator types of the low-frequency oscillator include a relaxation oscillator, a voltage-controlled oscillator and a crystal oscillator;
or, the first high-frequency oscillator and the second high-frequency oscillator are both crystal oscillators, and the oscillator types of the low-frequency oscillator include a relaxation oscillator, a voltage-controlled oscillator and a phase-locked loop;
or the first high-frequency oscillator and the second high-frequency oscillator are both voltage-controlled oscillators, and the oscillator types of the low-frequency oscillator comprise a relaxation oscillator, a phase-locked loop and a crystal oscillator.
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Application publication date: 20200626 |