CN106325814A - Real random number generator based on double-loop coupling oscillation circuit - Google Patents
Real random number generator based on double-loop coupling oscillation circuit Download PDFInfo
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Abstract
The invention discloses a real random number generator based on a double-loop coupling oscillation circuit, and mainly solves the problems of low output speed and low security of the real random number generator in the prior art. The real random number generator comprises an oscillation circuit and a sampling logic circuit, wherein the oscillation circuit comprises four exclusive-OR gates XOR and four exclusive nor gates XNOR; each exclusive-OR gate or exclusive nor gate is provided with three input ports and one output port, and are respectively provided with two left neighbors; the first input port of each exclusive-OR gate or exclusive nor gate is connected with the output port of one left neighbor; the second input port is connected with the output port of the other left neighbor; the third input port is connected with the self output port. The sampling logic circuit uses front and back four exclusive nor gates in the oscillation circuit for sampling by using D triggering at the clock ascending edge and the descending edge; the output speed is real random numbers at the output speed being higher than 100M. The real random number generator has the advantages of high security and simple structure, and can be applied to the field of information security.
Description
Technical field
The invention belongs to digital circuit technique field, particularly relate to a kind of True Random Number Generator, can be used for secure communication.
Background technology
Random number has vital effect for cryptography, the heaviest in the encryption technology of various protection data
Want.Existing many software algorithms can generate pseudo random number, but its unpredictability it is difficult to ensure that, want in some safeties
Asking in higher application program, pseudo random number can not meet it well and require that.In order to generate true random number, many is ground
Study carefully the noise source of simulation as random external source to construct True Random Number Generator.
Li Shen, Zhao Jianling, Wang Chao, Qu Guang outstanding person Wu make peace, Zhang Feng patent (patent publication No.: CN102637122B) based on
The parity of physical noise generates method and the system thereof of true random number, has invented a kind of signal producing physical noise and has carried out
Analog digital conversion, the parity further according to numeral generates random bit.
A kind of true random number of the patent (patent publication No.: CN102693119B) of Liu little Ling, Qiao Aiguo, Qi Fan, Xie Shaobo
Producing circuit and information security chip, by random noise signal being modulated generation mixed noise signal, then filtering wherein
DC component obtain high-frequency random noises component, generate corresponding true random number.
Japanese plum state, patent (patent publication No.: CN103049242A) the digital true random number of Wang Husen, Li Lijuan occur
Device, utilizes and is produced random number by the full-digital circuit of clock control, then random number is biased rectification obtains true random number.
A kind of true random number triangular wave of the patent (patent publication No.: CN103066956B) of Wang Qian, Zhang Donglai, Zhang Hua occurs
Method and device, the oscillator signal produced by multiple high frequency generators carries out synchronizing XOR, then controls triangle with the signal obtained
Wave producer generates true random number.
These methods above-mentioned owing to using the stochastic source of external environment condition and using the strongest oscillation rings signal of dependency, thus
All there is assailant and by affecting the problem that maker is manipulated by noise source, thus the safety of secret communication can be affected
And it is low to generate true random number speed.
Summary of the invention
Present invention aims to the deficiency of above-mentioned prior art, propose a kind of based on double-ring coupled vibration true with
Machine number maker, to protect the safety of positive secret communication, reduces oscillation rings signal correlation, improves the speed generating true random number
Rate.
For achieving the above object, the present invention includes:
Oscillating circuit and Sample Logic, this oscillating circuit, be made up of some digital logic gates, for generation have with
The Random Oscillation signal of machine phase offset；This Sample Logic, is carried out for the Random Oscillation signal producing oscillating circuit
Sampling, is converted into discrete random sequence by continuous print stochastic signal and exports, it is characterised in that:
All of digital logic gate, including M/2 XOR gate XOR and M/2 same or door XNOR, wherein M is not less than 6
Even number；These XOR gates XOR and with or door XNOR all have three input ports and an output port；
XOR gate that each two position is identical and with or Men Jun have the left neighbours of identical two, i.e. i-th XOR gate XORi
With i-th with or door XNORiThere is identical (i-1) mod (M/2) individual XOR gate XOR(i-1)mod(M/2)With (i-1) mod (M/2)
Individual with or door XNOR(i-1)mod(M/2), wherein i is the integer of 1 to M/2；
For each gate, its first input port is connected with the output port of the left neighbours of one, and second defeated
Inbound port is connected with another left neighbor output ports, and the 3rd input port is connected with the output port of self.
As preferably, described N XOR gate, utilize the basic programmable logic cells of FPGA to realize, this logical block by
XOR look-up table LUT and depositor composition, by look-up tables'implementation XOR gate pure digi-tal logic, preserve numeral shape by depositor
State.
As preferably, described N with or door, utilize the basic programmable logic cells of FPGA to realize, this logical block by
With or look-up table LUT and depositor composition, by look-up tables'implementation with or door pure digi-tal logic, by depositor preserve numeral shape
State.
The invention have the advantages that as follows:
1. the true random number stability generated is strong, output speed is high.
The double-ring coupled oscillating circuit of present invention structure is not owing to having random external source only in Circuits System
Thermal noise is amplified producing the strongest phase noise, so the true random number that stability is extremely strong can be produced；
Simultaneously because the output signal of double-ring coupled oscillating circuit has high frequency of oscillation and the widest frequency spectrum, it is adopted
The sample frequency of sample logic circuit is up to 100MHZ, can be by international random number industry examination criteria i.e. NIST statistic mixed-state bag
Detection, the true random number randomness of generation is strong.
2. due to the fact that whole randomizer is all realized by digital logic unit, the circuit resource pole used
Few, easily it is integrated in the chip being applied to security fields.
3. due to the fact that the Sample Logic using double sampled pattern, i.e. all carry out at rising edge clock and trailing edge
Its result XOR of sampling exports again, it is possible to decrease " 1 " bit and the output ratio deviation of " 0 " bit, improves the random number sequence of output
The quality of row, eliminates follow-up post-processing step.
Accompanying drawing explanation
Fig. 1 is the theory diagram of the present invention；
Fig. 2 is the circuit structure diagram of the present invention.
Detailed description of the invention
In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with embodiment, to the present invention
It is described in further detail.Should be appreciated that specific embodiment described herein is used only for explaining the present invention, be not used to limit
Determine the present invention.
With reference to Fig. 1, the present invention includes oscillating circuit, Sample Logic.Oscillating circuit R1 is used for producing stochastic signal；Adopt
Sample logic circuit is sampled for the stochastic signal producing oscillating circuit R1, and the outfan of this sample logic is as truly random
The outfan of number generator, exports true random number sequence.
With reference to Fig. 2, oscillating circuit and Sample Logic structure to the present invention are as follows:
Described oscillating circuit, including including M/2 XOR gate XOR and M/2 same or door XNOR, wherein M is not less than 6
Even number, this example takes M=8, i.e. four XOR gates respectively: the first XOR gate XOR1, the second XOR gate XOR2, the 3rd XOR gate
XOR3With the 4th XOR gate XOR4；Four with or door respectively: first with or door XNOR1, second with or door XNOR2, the 3rd with or
Door XNOR3With the 4th with or door XNOR4。
XOR gate that each two position is identical and with or Men Jun have the left neighbours of identical two, wherein:
First XOR gate XOR1Two left neighbours be respectively the 4th XOR gate XOR4With the 4th with or door XNOR4；
First same or door XNOR1Two left neighbours be respectively the 4th XOR gate XOR4With the 4th with or door XNOR4；
Second XOR gate XOR2Two left neighbours be respectively the first XOR gate XOR1With first with or door XNOR1；
Second same or door XNOR2Two left neighbours be respectively the first XOR gate XOR1With first with or door XNOR1；
3rd XOR gate XOR3Two left neighbours be respectively the second XOR gate XOR2With second with or door XNOR2；
3rd same or door XNOR3Two left neighbours be respectively the second XOR gate XOR2With second with or door XNOR2；
4th XOR gate XOR4Two left neighbours be respectively the 3rd XOR gate XOR3With the 3rd with or door XNOR3；
4th same or door XNOR4Two left neighbours be respectively the 3rd XOR gate XOR3With the 3rd with or door XNOR3；
Each XOR gate and each same or door, all have three input ports, i.e. first input port, second input
Mouth, the 3rd input port and an output port, first input port is connected with the output port of the left neighbours of one, the
Two another left neighbor output ports of input port and its are connected, and the 3rd input port is connected with the output port of self.
Wherein:
First XOR gate XOR1First input port and the 4th XOR gate XOR4Output port connect, second is defeated
Inbound port and the 4th same or door XNOR4Output port connect, the 3rd input port is connected with the output port of self；
First same or door XNOR1First input port and the 4th XOR gate XOR4Output port connect, second is defeated
Inbound port and the 4th same or door XNOR4Output port connect, the 3rd input port is connected with the output port of self；
Second XOR gate XOR2First input port and the first XOR gate XOR1Output port connect, second is defeated
Inbound port and the first same or door XNOR1Output port connect, the 3rd input port is connected with the output port of self；
Second same or door XNOR2First input port and the first XOR gate XOR1Output port connect, second is defeated
Inbound port and the first same or door XNOR1Output port connect, the 3rd input port is connected with the output port of self；
3rd XOR gate XOR3First input port and the second XOR gate XOR2Output port connect, second is defeated
Inbound port and the second same or door XNOR2Output port connect, the 3rd input port is connected with the output port of self；
3rd same or door XNOR3First input port and the second XOR gate XOR2Output port connect, second is defeated
Inbound port and the second same or door XNOR2Output port connect, the 3rd input port is connected with the output port of self；
4th XOR gate XOR3First input port and the 3rd XOR gate XOR3Output port connect, second is defeated
Inbound port and the 3rd same or door XNOR3Output port connect, the 3rd input port is connected with the output port of self；
4th same or door XNOR3First input port and the 3rd XOR gate XOR3Output port connect, second is defeated
Inbound port and the 3rd same or door XNOR3Output port connect, the 3rd input port is connected with the output port of self.
Described Sample Logic includes 8 trigger D1、D2、D3、D4、D5、D6、D7、D8With three XOR gate XOR5、
XOR6、XOR7, wherein:
Front four d type flip flop D1、D2、D3、D4Respectively with two XOR gates in oscillating circuit and with or door be connected, i.e. the
One trigger D1Input be the first XOR gate XOR1Output, the second trigger D2Input be second with or door XNOR2Defeated
Go out, the 3rd trigger D3Input be the 3rd XOR gate XOR3Output, the 4th trigger D4Input be the 4th with or door
XNOR4Output, these four d type flip flop D1、D2、D3、D4Output as the 5th XOR gate XOR5Input；
Rear four d type flip flop D5、D6、D7、D8Respectively with in oscillating circuit two XOR gates and with or door be connected, the i.e. the 5th
Trigger D5Input be first with or door XNOR1Output, the 6th trigger D6Input be the second XOR gate XOR2Defeated
Go out, the 7th trigger D7Input be the 3rd fellow disciple XOR3Output, the 8th trigger D8Input be the 4th XOR gate XOR4's
Output, these four d type flip flop D5、D6、D7、D8Output as the 6th XOR gate XOR6Input, the 5th XOR gate XOR5Defeated
Go out and the 6th XOR gate XOR5Output as the 7th XOR gate XOR7Input, the 7th XOR gate XOR7Output as sampling
The output of logic circuit.
Eight d type flip flop D1、D2、D3、D4、D5、D6、D7、D8With three XOR gate XOR5、XOR6、XOR7By time identical
Clock controls, and this clock is provided by external clock CLK, when external clock CLK is rising edge, controls front four d type flip flop D1、
D2、D3、D4Sampling, when external clock CLK be lower liter along time, control rear four d type flip flop D5、D6、D7、D8Sampling.
The effect of the present invention can be further illustrated by following testing result:
1, detection method:
Under the frequency that external clock is 100MHZ drives, produce the true random sequence of 1000 groups of 1M；
Use the SP800-22 random number examination criteria that American National Standard and technical research institute NIST provide to above-mentioned
The randomness of the true random sequence of 1000 groups of 1M detects, and this examination criteria comprises 15 detection contents, and each detection is produced
Raw testing result comprises a P-value value and a percent of pass Propotion value.When P-value value is not less than 0.001
And percent of pass value is not less than 0.9806, represent that this detection content is passed through.
2, testing result:
True random sequence to the 1000 groups of 1M produced by the present invention, carries with American National Standard and technical research institute NIST
The SP800-22 random number examination criteria of confession detects, result such as table 1:
Table 1 test result
| StatisticalTest | P-value | Propotion | Result |
| Frequence | 0.579579 | 0.9900 | Pass |
| BlockFrequence | 0.619506 | 0.9900 | Pass |
| CumulativeSums | 0.345678 | 0.9860 | Pass |
| Runs | 0.231816 | 0.9900 | Pass |
| LongestRun | 0.268716 | 0.9860 | Pass |
| Rank | 0.715034 | 0.9840 | Pass |
| FFT | 0.563178 | 0.9860 | Pass |
| OverlappingTemplate | 0.267932 | 0.9900 | Pass |
| Universal | 0.133111 | 0.9879 | Pass |
| LinearComplexity | 0.435453 | 0.9900 | Pass |
| ApproximateEntropy | 0.353447 | 0.9840 | Pass |
| Serial | 0.227951 | 0.9880 | Pass |
| NonOverlappingTemplate | 0.192880 | 0.9867 | Pass |
| RandomExcursions | 0.189459 | 0.9902 | Pass |
| RandomExcursionsVariant | 0.277424 | 0.9967 | Pass |
As seen from Table 1, each index of true random sequence that the present invention produces all has reached the requirement standard of random number, shows
The random number that the present invention produces has good randomness.
Above-described embodiment only with being embodied as illustrating the implementation method of the present invention, can have various deformation on this basis,
Within the change of this structure based on the present invention is all contained in protection scope of the present invention.
Claims (5)
1. True Random Number Generator based on double-ring coupled oscillating circuit, including: oscillating circuit and Sample Logic, this vibration
Circuit, is made up of some digital logic gates, for producing the Random Oscillation signal with random phase offset；This sample logic electricity
Road, samples for the Random Oscillation signal producing oscillating circuit, is converted into by continuous print stochastic signal discrete random
Sequence exports, it is characterised in that:
All of digital logic gate, including M/2 XOR gate XOR and M/2 same or door XNOR, wherein M is the idol not less than 6
Number；These XOR gates XOR and with or door XNOR all have three input ports and an output port；
XOR gate that each two position is identical and with or Men Jun have the left neighbours of identical two, i.e. i-th XOR gate XORiWith i-th
Individual with or door XNORiThere is identical (i-1) mod (M/2) individual XOR gate XOR(i-1)mod(M/2)Individual with (i-1) mod (M/2) same
Or door XNOR(i-1)mod(M/2), wherein i is the integer of 1 to M/2；
For each gate, its first input port is connected with the output port of the left neighbours of one, second input
Mouth is connected with another left neighbor output ports, and the 3rd input port is connected with the output port of self.
2. True Random Number Generator based on double-ring coupled agitator as claimed in claim 1, it is characterised in that:
Described XOR gate XOR, utilizes the basic programmable logic cells of FPGA to realize, this logical block by XOR look-up table
LUT and depositor composition, by XOR look-up tables'implementation XOR gate pure digi-tal logic, preserve digital state by depositor.
True Random Number Generator based on double-ring coupled agitator the most according to claim 1, it is characterised in that:
Described with or door XNOR, utilize the basic programmable logic cells of FPGA to realize, this logical block by together or look-up table
LUT and depositor composition, by with or look-up tables'implementation with or door pure digi-tal logic, preserve digital state by depositor.
True Random Number Generator based on double-ring coupled agitator the most according to claim 1, it is characterised in that:
Described Sample Logic includes 8 trigger D1、D2、D3、D4、D5、D6、D7、D8With three XOR gate XORM/2+1、
XORM/2+2、XORM/2+3, wherein:
Front four d type flip flop D1、D2、D3、D4Respectively with two XOR gates in oscillating circuit and with or door be connected, i.e. first triggering
Device D1Input be the first XOR gate XOR1Output, the second trigger D2Input be second with or door XNOR2Output,
Three trigger D3Input be the 3rd XOR gate XOR3Output, the 4th trigger D4Input be the 4th with or door XNOR4Defeated
Go out, these four d type flip flop D1、D2、D3、D4Output as M/2+1 XOR gate XORM/2+1Input；
Rear four d type flip flop D5、D6、D7、D8Respectively with in oscillating circuit two XOR gates and with or door be connected, the i.e. the 5th trigger
D5Input be first with or door XNOR1Output, the 6th trigger D6Input be the second XOR gate XOR2Output, the 7th
Trigger D7Input be the 3rd fellow disciple XOR3Output, the 8th trigger D8Input be the 4th XOR gate XOR4Output, should
Four d type flip flop D5、D6、D7、D8Output as M/2+2 XOR gate XORM/2+2Input, M/2+1 XOR gate XORM/2+1
Output and M/2+2 XOR gate XORM/2+2Output as M/2+3 XOR gate XORM/2+3Input, M/2+3 XOR gate
XORM/2+3Output as the output of Sample Logic.
True Random Number Generator based on double-ring coupled agitator the most according to claim 4, it is characterised in that: eight D
Trigger D1、D2、D3、D4、D5、D6、D7、D8With three XOR gate XORN+1、XORN+2、XORN+3Controlled by identical clock, should
Clock is provided by external clock CLK, when external clock CLK is rising edge, controls front four d type flip flop D1、D2、D3、D4Adopt
Sample, when external clock CLK be lower liter along time, control rear four d type flip flop D5、D6、D7、D8Sampling.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110336536A (en) * | 2019-07-29 | 2019-10-15 | 深圳大学 | The circuit and equipment of real random number generator |
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| US20040264233A1 (en) * | 2003-06-24 | 2004-12-30 | Renesas Technology Corp. | Random number generator with ring oscillation circuit |
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