CN103019648A - True random number generator with digital post-processing circuit - Google Patents
True random number generator with digital post-processing circuit Download PDFInfo
- Publication number
- CN103019648A CN103019648A CN2012104917576A CN201210491757A CN103019648A CN 103019648 A CN103019648 A CN 103019648A CN 2012104917576 A CN2012104917576 A CN 2012104917576A CN 201210491757 A CN201210491757 A CN 201210491757A CN 103019648 A CN103019648 A CN 103019648A
- Authority
- CN
- China
- Prior art keywords
- random number
- true random
- feedback shift
- linear feedback
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a true random number generator with a digital post-processing circuit, which comprises a true random number source and a true random number output register. The true random number generator is characterized in that the digital post-processing circuit is connected between the true random number source and the true random number output register, wherein the digital post-processing circuit comprises a Manchester encoder, a linear feedback shift register and a DES (data encryption standard) encryption unit which are connected from the true random number source to the true random number output register; the true random number output register is used for latching the ciphertext output by the DES encryption unit; and finally, the true random number is output to a chip by the true random number output register. The true random number generator improves the quality of random number sequences generated by the true random number source; the finally output random number sequences have the characteristics of good uniformity and high independence; the security for information storage of the cryptographic chip is improved; and the true random number generator has higher actual application value in the aspects of cryptographic chip, information security and the like.
Description
Technical field
The present invention relates to a kind of real random number generator, relate in particular to a kind of real random number generator with digital post processing circuitry.
Background technology
Random number occupies an important position in cryptography, it must be secret data concerning the assailant that nearly all cryptographic algorithm and agreement all will be used some, such as concerning a cryptographic algorithm, if secret is resided among the key, key is exactly secret so, the key that comprises the key of symmetric cryptographic algorithm (DES, AES etc.) and asymmetric cryptographic algorithm (RSA, DSA etc.) to etc., and these keys must be random numbers.For unique verified one-time pad system of Perfect Secrecy system, its security just depends on key, and its key must be random number.
Along with the development of encryption and decryption technology, the requirement of high quality random numbers is also grown with each passing day.The randomizer that software approach is realized is to utilize software algorithm to produce random number sequence.Yet this sequence is decided by the algorithm and the initial seed that adopt, and has certain periodicity.Owing to there being this characteristic, the randomizer that software is realized is commonly called pseudorandom number generator (Pseudo Random Number Generator, PRNG).If the assailant has enough computing powers, then can predict the generation rule of pseudo random number fully.For the security system of many use pseudo random numbers, pseudo random number is doomed to become the bottleneck that their performances improve.Even the miscellaneous part of a security system is safe enough all, use pseudo random number also can make whole system become very fragile, be vulnerable to attack.
And true random number sequence is uncertain, thereby also the periodically true random number sequence of repetition can not occur.It can only be produced by random physical process, such as the thermonoise of circuit, cosmic noise, radioactivity decay etc.Hardware approach realizes that real random number generator (True Random Number Generator, TRNG) mainly depends on the random character of physical component, for example noise of arc lamp, nuclear ray decay, resistance or diode.Real random number generator need to be set initial seed unlike pseudorandom number generator, the random number that produces derives from real random physical process, thereby eliminated up hill and dale the periodic problem of pseudo random number, only have real random number generator that real, unduplicated random number sequence forever just can be provided.In integrated circuit, most of real random number generator design proposals can be classified as three major types usually: amplifying circuit noise, chaos circuit, vibration sampling.At present, most popular method is the oscillator sampling method in the randomizer design, its fundamental design idea is to utilize two relativenesses between the high and low frequency oscillator that works alone to obtain non-definite noise source, with the LF oscillator high frequency oscillator of sampling, thereby produce true random number sequence.
Real random number generator is being brought into play extremely important effect as one of core component of modern password chip system, and the design effort of real random number generator also more and more obtains people's attention on the sheet.Although the true random number that produces based on the physical accidental source is compared pseudorandom number generator at aspects such as the length of random series, independence and obtained breakthrough, the randomness of the true random number sequence of its generation is stable not, random number of low quality.Generally speaking, the high quality true random number sequence has the characteristic such as be evenly distributed, the cycle is long, sequence is irrelevant.The checking sequence quality has the method for testings such as a series of test ratings such as followability, the distance of swimming, homogeneity, independence, correlativity and analysis of spectrum, ENT (a kind of random number Performance Detection program).Although the physical accidental source can provide true random number sequence truly, the true random number sequence that does not represent its generation has very high quality, also not necessarily can satisfy the requirement of above-mentioned test.If mathematical method and physical method can be combined, then may produce high quality true random number.From implementation method, have take software as main, take hardware as methods such as main and soft or hard combinations.
Summary of the invention
For above-mentioned prior art, the invention provides a kind of real random number generator with digital post processing circuitry, by traditional real random number generator structure is improved, increase digital post processing circuitry, improved the quality of the random number sequence of physical accidental source generation, the final random number sequence of exporting has good uniformity, independence high, has improved the security of the information storage of crypto chip, has higher actual application value at aspects such as crypto chip, information securities.
Among the present invention, a kind of technical scheme that realizes with the real random number generator of digital post processing circuitry is: comprise true random number source and true random number output register, it is characterized in that: be connected with digital post processing circuitry between described true random number source and the true random number output register, described digital post processing circuitry is by the manchester encoder, linear feedback shift register and the des encryption cell formation that are connected to described true random number output register from described true random number source; Described true random number output register is used for latching the ciphertext of described des encryption unit output, and final true random number exports chip to by described true random number output register.
Further, the present invention is with the real random number generator of digital post processing circuitry, wherein, described manchester encoder is comprised of an XOR gate, a not gate and a trigger, thereby realize the conversion from the NRZ code to Manchester code, and by the beginning of coding-control end control Manchester's cde with stop.
Described linear feedback shift register adopts 128 bit linear feedback shift registers, and its feedback function is
The sequence period length of the random number of its generation is 2
128-1; During described linear feedback shift register work, at first by the Manchester code sequence as the seed filling of linear feedback shift register to this 128 bit linear feedback shift register, at this moment, it is 0 that signal is used in linear feedback shift register output, and the Manchester code sequence enters in the linear feedback shift register by bit; Behind 128 whole end-of-fills of linear feedback shift register, the linear feedback shift register enable signal becomes 1, and at this moment, linear feedback shift register is started working, and the linear feedback shift register output terminal begins to export random number sequence.
Described des encryption unit is made of key and plaintext generation unit and DES arithmetic element; Described plaintext and key generation unit generate plaintext and the key of the required 64bits of DES computing by the random number of obtaining linear feedback shift register output, described plaintext and key generation unit are comprised of plaintext register and key register, are used for latching respectively the random number of 64bits; Described DES arithmetic element is finished the 16 des encryption computings of taking turns, thereby to described true random number output register output 64bits ciphertext.
Compared with prior art, the invention has the beneficial effects as follows:
Real random number generator is the significant element circuit in crypto chip and the safety chip, is used for producing the needed true random number sequence of chip operation.The present invention improves traditional real random number generator structure based on the physical accidental source, mathematical method and physical method are combined, can produce high quality true random number, the information privacy of crypto chip is promoted significantly, can reach the requirement of dependence test index and standard, again can the effective guarantee information security.By behind true random number source, adding digital post processing circuitry, make the true random number sequence of true random number source generation through after the aftertreatment of digital circuit, send into again other unit uses in the chip.Real random number generator of the present invention can effectively improve the randomness of true random number, improves the security performance of chip.
Description of drawings
Fig. 1 is the structural representation of real random number generator of the present invention;
Fig. 2 is the structural representation of true random number source among the present invention;
Fig. 3 is manchester encoder structural representation among the present invention;
Fig. 4 is neutral line feedback shift register structural representation of the present invention;
Fig. 5 is des encryption cellular construction schematic diagram among the present invention;
The workflow diagram of Fig. 6 real random number generator of the present invention.
Embodiment
Below in conjunction with embodiment the present invention is described in further detail.
As shown in Figure 1, a kind of real random number generator with digital post processing circuitry of the present invention, comprise true random number source and true random number output register, be connected with digital post processing circuitry between described true random number source and the true random number output register, described digital post processing circuitry is by the manchester encoder that is connected to described true random number output register from described true random number source, linear feedback shift register (LFSR) and des encryption cell formation; Described true random number output register is used for latching the ciphertext of DES arithmetic element output, and final true random number exports chip to by described true random number output register.The input signal of real random number generator comprises system clock and high frequency oscillator signal.
As shown in Figure 2, true random number source is realized based on the concussion sampling method, utilize the high and low frequency oscillator of two outs of phase that work alone to obtain non-definite noise source, wherein LF oscillator utilizes 2 frequency divisions of system clock to realize, as the high frequency oscillator signal of the sampling clock of true random number sampling input, thereby produce random number sequence.In the physical circuit that reality realizes, the sampling clock conduct of true random number is just along the clock signal that triggers d type flip flop, the high frequency oscillator input signal is then inputted as the D end data of trigger, and at the rising edge of sampling clock pulse it is sampled, what the Q end of trigger obtained is exactly a true random number bit stream.
Because the true random number bitstream quality of true random number source output is not high, may there be the length zero or long one sequence that are formed by continuous a plurality of " 0 " or a plurality of " 1 ", although such sequence belongs to true random number, but its randomness is poor, can not satisfy the requirement of chip operation, therefore at first data are sent into manchester encoder, eliminate long zero and reach long one sequence.As shown in Figure 3, described manchester encoder is comprised of an XOR gate, a not gate and a trigger, thereby realizes the conversion from the NRZ code to Manchester code, and by the beginning of coding-control end control Manchester's cde with stop.
In order to improve the randomness index of true random number, with the value discretize of true random number sequence, by after the manchester encoder, the Manchester code bit stream is sent into follow-up LFSR and the des encryption unit is processed.
As shown in Figure 4, described LFSR adopts 128 bit linear feedback shift registers to realize, its feedback function is
The sequence period length of the random number of its generation is 2
128-1; During described LFSR work, at first by the Manchester code bit stream as the seed filling of LFSR to these 128 LFSR, at this moment, LFSR output enable signal is 0, the Manchester code bit stream enters among the LFSR by bit; Behind 128 whole end-of-fills of LFSR, LFSR output enable signal becomes 1, and at this moment, LFSR starts working, and the LFSR output terminal begins to export random number sequence.
As shown in Figure 5, described des encryption unit is by key with expressly generation unit and DES arithmetic element consist of; Described plaintext and key generation unit generate plaintext and the key of the required 64bit of DES computing by the random number sequence of obtaining LFSR output, described plaintext and key generation unit are comprised of plaintext register and key register, are used for latching respectively the random number of 64bits; After plaintext and key generation, generation unit sends enable signal to the DES arithmetic element, finishes the 16 des encryption computings of taking turns by described DES arithmetic element, thereby to described true random number output register output 64bits ciphertext; The true random number output register is used for latching the 64bits ciphertext of DES arithmetic element output.
During Data Post circuit working in the real random number generator of the present invention, at first by manchester encoder the true random number that true random source produces is processed, the Manchester's cde bit stream of generation is as the input of LFSR; Plaintext and key register after LFSR processes in the Sequence Filling des encryption unit of output, fill the full rear des encryption computing that starts, the true random number output register that the 64bits ciphertext of final output is output to as the real random number generator output unit latchs, and the true random number that it latchs uses as other unit that final output offers chip.
As shown in Figure 6, the workflow of real random number generator of the present invention is: when chip needs random number sequence, at first open the input of high frequency oscillator and clock signal of system, thereby start true random number source, produce true random number sequence; Enable subsequently manchester encoder, output Manchester code bit stream; This bit stream is sent among the LFSR inserts register as seed, until 128 bit registers fill up, start LFSR, the random number sequence after output LFSR processes; Random number sequence after the LFSR processing is filled into plaintext and the key register of des encryption unit, all fill up rear startup DES computing, final output 64bits ciphertext is deposited into the true random number output register, for other unit of chip as the random number output of real random number generator; Close at last the input of high frequency oscillator and system clock, wait for next time working of real random number generator.
Although top invention has been described in conjunction with figure; but the present invention is not limited to above-mentioned embodiment; above-mentioned embodiment only is schematic; rather than restrictive; those of ordinary skill in the art is under enlightenment of the present invention; in the situation that do not break away from aim of the present invention, can also make a lot of distortion, these all belong within the protection of the present invention.
Claims (4)
1. real random number generator with digital post processing circuitry, comprise true random number source and true random number output register, it is characterized in that: be connected with digital post processing circuitry between described true random number source and the true random number output register, described digital post processing circuitry is by the manchester encoder, linear feedback shift register and the des encryption cell formation that are connected to described true random number output register from described true random number source; Described true random number output register is used for latching the ciphertext of described des encryption unit output, and final true random number exports chip to by described true random number output register.
2. described real random number generator with digital post processing circuitry according to claim 1, it is characterized in that: described manchester encoder is comprised of an XOR gate, a not gate and a trigger, thereby realize the conversion from the NRZ code to Manchester code, and by the beginning of coding-control end control Manchester's cde with stop.
3. described real random number generator with digital post processing circuitry according to claim 1, it is characterized in that: described linear feedback shift register adopts 128 bit linear feedback shift registers, and its feedback function is
The sequence period length of the random number of its generation is 2
128-1; During described linear feedback shift register work, at first by the Manchester code sequence as the seed filling of linear feedback shift register to this 128 bit linear feedback shift register, at this moment, it is 0 that signal is used in linear feedback shift register output, and the Manchester code sequence enters in the linear feedback shift register by bit; Behind 128 whole end-of-fills of linear feedback shift register, the linear feedback shift register enable signal becomes 1, and at this moment, linear feedback shift register is started working, and the linear feedback shift register output terminal begins to export random number sequence.
4. described real random number generator with digital post processing circuitry according to claim 1 is characterized in that: described des encryption unit is by key and expressly generation unit and DES arithmetic element consist of; Described plaintext and key generation unit generate plaintext and the key of the required 64bits of DES computing by the random number of obtaining linear feedback shift register output, described plaintext and key generation unit are comprised of plaintext register and key register, are used for latching respectively the random number of 64bits; Described DES arithmetic element is finished the 16 des encryption computings of taking turns, thereby to described true random number output register output 64bits ciphertext.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104917576A CN103019648A (en) | 2012-11-27 | 2012-11-27 | True random number generator with digital post-processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104917576A CN103019648A (en) | 2012-11-27 | 2012-11-27 | True random number generator with digital post-processing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103019648A true CN103019648A (en) | 2013-04-03 |
Family
ID=47968291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012104917576A Pending CN103019648A (en) | 2012-11-27 | 2012-11-27 | True random number generator with digital post-processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103019648A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104461453A (en) * | 2013-09-14 | 2015-03-25 | 安徽量子通信技术有限公司 | Method for generating true random numbers |
| CN104461454A (en) * | 2013-09-14 | 2015-03-25 | 安徽量子通信技术有限公司 | High-speed true random number generating device |
| CN104461452A (en) * | 2013-09-17 | 2015-03-25 | 航天信息股份有限公司 | Method and device for generating true random numbers in system on chip |
| CN105159653A (en) * | 2015-08-18 | 2015-12-16 | 珠海市一微半导体有限公司 | Random number post-processing circuit and method |
| CN103885748B (en) * | 2014-03-12 | 2017-01-04 | 浙江大学 | A kind of low-power consumption random number post-processing approach |
| CN106650474A (en) * | 2016-12-01 | 2017-05-10 | 惠州Tcl移动通信有限公司 | Pseudo register value feedback processing method and system based on mobile terminal |
| CN106921490A (en) * | 2015-12-28 | 2017-07-04 | 航天信息股份有限公司 | A kind of real random number generator and label chip |
| CN108694344A (en) * | 2018-08-03 | 2018-10-23 | 南方电网科学研究院有限责任公司 | A kind of cryptography electronic label |
| CN108733350A (en) * | 2017-04-13 | 2018-11-02 | 力旺电子股份有限公司 | Generating random number device and its control method |
| CN110221811A (en) * | 2019-06-13 | 2019-09-10 | 武汉星旗科技有限公司 | A kind of generation method of true random number, device, equipment and computer media |
| CN111596892A (en) * | 2020-05-11 | 2020-08-28 | 南京西觉硕信息科技有限公司 | Soft random number generation method and generator |
| CN111783078A (en) * | 2020-07-14 | 2020-10-16 | 大唐终端技术有限公司 | Android platform security chip control system |
| CN114384969A (en) * | 2020-12-31 | 2022-04-22 | 广东国腾量子科技有限公司 | High-speed true random number generation system |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101965552A (en) * | 2008-03-04 | 2011-02-02 | 桑迪士克以色列公司 | Digital random number generator based on digitally-controlled oscillators |
-
2012
- 2012-11-27 CN CN2012104917576A patent/CN103019648A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101965552A (en) * | 2008-03-04 | 2011-02-02 | 桑迪士克以色列公司 | Digital random number generator based on digitally-controlled oscillators |
Non-Patent Citations (3)
| Title |
|---|
| LIU CHANGLONG ET.AL: "A System-On-Chip Bus Architecture for Hardware Trojan Protection in Security Chips", 《2011 IEEE INTERNATIONAL CONFERENCE OF ELECTRON DEVICES AND SOLID-STATE CIRCUITS》, vol. 2011, 31 December 2011 (2011-12-31), pages 1 - 2 * |
| 刘岑 等: "一种高可靠性微控制器的设计与VLSI实现", 《计算机工程与应用》, vol. 48, no. 6, 27 April 2012 (2012-04-27), pages 53 - 56 * |
| 舒平平 等: "基于FPGA的曼彻斯特编码DSG的设计与实现", 《实验科学与技术》, vol. 10, no. 4, 31 August 2012 (2012-08-31) * |
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104461454A (en) * | 2013-09-14 | 2015-03-25 | 安徽量子通信技术有限公司 | High-speed true random number generating device |
| CN104461453A (en) * | 2013-09-14 | 2015-03-25 | 安徽量子通信技术有限公司 | Method for generating true random numbers |
| CN104461452A (en) * | 2013-09-17 | 2015-03-25 | 航天信息股份有限公司 | Method and device for generating true random numbers in system on chip |
| CN103885748B (en) * | 2014-03-12 | 2017-01-04 | 浙江大学 | A kind of low-power consumption random number post-processing approach |
| CN105159653B (en) * | 2015-08-18 | 2018-03-20 | 珠海市一微半导体有限公司 | Random number post processing circuitry and method |
| CN105159653A (en) * | 2015-08-18 | 2015-12-16 | 珠海市一微半导体有限公司 | Random number post-processing circuit and method |
| CN106921490B (en) * | 2015-12-28 | 2020-06-05 | 航天信息股份有限公司 | True random number generator and label chip |
| CN106921490A (en) * | 2015-12-28 | 2017-07-04 | 航天信息股份有限公司 | A kind of real random number generator and label chip |
| CN106650474B (en) * | 2016-12-01 | 2020-06-02 | 惠州Tcl移动通信有限公司 | Pseudo register value feedback processing method and system based on mobile terminal |
| CN106650474A (en) * | 2016-12-01 | 2017-05-10 | 惠州Tcl移动通信有限公司 | Pseudo register value feedback processing method and system based on mobile terminal |
| CN108733350A (en) * | 2017-04-13 | 2018-11-02 | 力旺电子股份有限公司 | Generating random number device and its control method |
| CN108733350B (en) * | 2017-04-13 | 2021-08-27 | 力旺电子股份有限公司 | Random number generation device and control method thereof |
| CN108694344A (en) * | 2018-08-03 | 2018-10-23 | 南方电网科学研究院有限责任公司 | A kind of cryptography electronic label |
| CN110221811A (en) * | 2019-06-13 | 2019-09-10 | 武汉星旗科技有限公司 | A kind of generation method of true random number, device, equipment and computer media |
| CN111596892A (en) * | 2020-05-11 | 2020-08-28 | 南京西觉硕信息科技有限公司 | Soft random number generation method and generator |
| CN111596892B (en) * | 2020-05-11 | 2023-06-23 | 南京西觉硕信息科技有限公司 | Soft random number generation method and generator |
| CN111783078A (en) * | 2020-07-14 | 2020-10-16 | 大唐终端技术有限公司 | Android platform security chip control system |
| CN114384969A (en) * | 2020-12-31 | 2022-04-22 | 广东国腾量子科技有限公司 | High-speed true random number generation system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103019648A (en) | True random number generator with digital post-processing circuit | |
| CN108964872B (en) | Encryption method and device based on AES | |
| US20120134490A1 (en) | Selective Data Encryption and Decryption Method and Apparatus | |
| US10326589B2 (en) | Message authenticator generating apparatus, message authenticator generating method, and computer readable recording medium | |
| EP3503463B1 (en) | Systems and methods implementing countermeasures to phase tracking attacks on ring oscillator based entropy sources | |
| CN105933108B (en) | A kind of pair of SM4 algorithm realizes the method cracked | |
| CN106027238A (en) | True random number generator applicable to wireless communication system | |
| CN112199696B (en) | Encryption and decryption method based on white-box block cipher | |
| CN107491317A (en) | A kind of symmetrical encryption and decryption method and systems of AES for accelerating platform based on isomery | |
| CN106375079A (en) | Chaotic encryption method for voice information | |
| Stefanov et al. | FastPRP: Fast pseudo-random permutations for small domains | |
| US20170365191A1 (en) | Iterative encryption and random generation and serialization of cryptographic functions | |
| CN109508174A (en) | A kind of single-stage real random number generator | |
| CN106358184A (en) | Point-to-point identity authentication method | |
| CN106383691A (en) | Random number generation method and random number generator | |
| Jothi et al. | Parallel RC4 Key Searching System Based on FPGA | |
| Liu et al. | A Fast New Cryptographic Hash Function Based on Integer Tent Mapping System. | |
| CN105391546A (en) | Lightweight block cipher technology VHF based on double pseudo random transformation and Feistel structure | |
| CN104461452A (en) | Method and device for generating true random numbers in system on chip | |
| Sava et al. | A new type of keystream generator based on chaotic maps: illustration on a Hénon generalized map | |
| CN109254617A (en) | Clock signal generation method and device | |
| CN103220128B (en) | A kind of chaos cipher production method based on taking out position quantification at random | |
| CN106230579A (en) | A kind of pseudo-random signal method for generation based on chaos and generator | |
| CN105553647A (en) | Light-weight stream cipher technology LSNR2 based on nonlinear ring shift register | |
| Brosas et al. | Analysis of the randomness performance of the proposed stream cipher based cryptographic algorithm |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20130403 |