CN202534008U - Isomorphic dual-core structure-based SoC applied to image processing - Google Patents
Isomorphic dual-core structure-based SoC applied to image processing Download PDFInfo
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- CN202534008U CN202534008U CN 201220125183 CN201220125183U CN202534008U CN 202534008 U CN202534008 U CN 202534008U CN 201220125183 CN201220125183 CN 201220125183 CN 201220125183 U CN201220125183 U CN 201220125183U CN 202534008 U CN202534008 U CN 202534008U
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Abstract
The utility model provides an isomorphic dual-core structure-based system on chip (SoC) applied to image processing. According to the SoC, two isomorphic DSP cores are connected together by an advanced microcontroller bus architecture (AMBA) bus of an ARM company, wherein one of the cores is used as a main program of running of a general processor and the other core is responsible for executing image processing operation work. In order to carry out processing on communication and data exchange between the two cores well, a dual-port random access memory (RAM) memory mode is employed and an interruption mode is also utilized to carry out communication. A static random access memory (SRAM) device and a read only memory (ROM) device are connected on the system bus and peripheral equipment like a USB 2.0, a universal asynchronous receiver/transmitter (UART), and an analog to digital converter (ADC) and the like are also configured. According to the utility model, the advantages of the SoC are as follows: the two cores work simultaneously, so that the processing capability and the computed speed are improved; and compared with a single-core processor, the dual-core SoC has high performances and can carry out high-definition image processing; besides, the power consumption of the system can be substantially reduced and the reliability and the reconfigurability of the system can be enhanced.
Description
Technical field
The utility model relates to the VLSI designs field, is a kind of SoC (System on Chip, SOC(system on a chip)) that is applied to the isomorphism dual-core architecture of Flame Image Process specifically.
Background technology
DSP is processing digital signal in real time, and powerful data-handling capacity is considerably beyond general processor, thereby in Digital Image Processing, has brought into play important effect.But at present, along with the raising of various image processing techniquess, the resolution of image is had higher requirement, the complexity of data processing improves greatly, and is also increasingly high to the performance requirement of DSP.Along with the limit of minimum feature is more and more nearer, at present simple dependence improved dominant frequency and improved the computing power of the processor more and more difficult that becomes, and heat radiation has become the monokaryon development key factor that restricts with power consumption.So when improving constantly dominant frequency, double-nuclear DSP constitution occurred, utilize the framework of optimizing to realize higher calculated performance, endorse with the parallel processing data for two, be equivalent to be doubled original processing power, improved efficient.According to the kind that includes processor core, can be divided into isomorphism processor and heterogeneous processor.Nuclear in the utility model is the on all four isomorphisms nuclear of two structures, has independently operation processing unit and buffer memory, between through 64 AHB program buss and 64 DSP that the AHB data bus links together.
Summary of the invention
The purpose of the utility model is to overcome the deficiency that exists in the existing monokaryon technology; A kind of SoC based on the isomorphism dual-core architecture that is applied to Flame Image Process is provided; Taken into account programmed control and data computation,, be particularly suitable for applying to image processing field having obtained reinforcement aspect calculating and the control.
The technical scheme that provides according to the utility model; Should comprise towards SoC of Flame Image Process based on isomorphism double-core framework: as the DSP nuclear of primary processor, as the 2nd DSP nuclear that calculates coprocessor, Flame Image Process interface module, image coprocessor, program storage block, data memory module, system control module, AES engine, two identical dma modules, ADC module, interrupt control module, serial interface module, and the system peripheral module; Said image coprocessor links to each other with the Flame Image Process interface module; Link to each other with 64 AHB data buss through 64 AHB program buss between said DSP nuclear and the 2nd DSP nuclear; Said DSP nuclear and the 2nd DSP nuclear are through 64 AHB program bus linker memory modules; Said DSP nuclear is connected data memory module, dma module, ADC module with the 2nd DSP nuclear through 64 AHB data buss; Said DSP nuclear is connected AES engine, image coprocessor with the 2nd DSP nuclear through 32 AHB peripheral bus, and said DSP nuclear is connected interrupt control module, serial interface module, system control module, system peripheral module with the 2nd DSP nuclear through 32 APB peripheral bus.Said system control module is included as phaselocked loop, power management module, GPIO and the jtag interface that the sheet upper module provides the clock input.
Said DSP nuclear is identical with the 2nd DSP nuclear structure, all includes interruptable controller.Said DSP nuclear and the 2nd DSP nuclear comprise: get finger unit, address arithmetic unit, data operation unit, multiplicaton addition unit and registers group; Said address arithmetic parts comprise interconnected address ALU and address generator; Said data operation parts comprise interconnected ALU and FPU Float Point Unit FPU; Instruction refers to get into address arithmetic unit, data operation unit and multiplicaton addition unit respectively after the unit is through decoding by getting, and accomplishes after the computing input register as a result.
Said 16 image coprocessor comprises interruptable controller.
Said 32 AHB peripheral bus connect 32 APB peripheral bus through bus bridge, connect interrupt control module, serial interface module, system control module, system peripheral module again.
Said system peripheral module comprises 4 timers and 8 pulse width regulator PWM.
Said serial interface module comprises: USB2.0 interface, serial bus interface IIC, serial digital audio bus interface IIS, synchronous serial interface SSI, UART interface.
The utility model has the advantages that: it is connected together two isomorphism DSP nuclears by the AMBA bus, and a nuclear moves master routine as general processor, and another nuclear is responsible for carries out image processing computing work.In order to handle communication and the exchanges data between double-core well, adopted shared bus and form of memory, and adopted interrupt mode to communicate by letter.And be furnished with the Flame Image Process interface and carry out the external data sampling, the image coprocessor carries out pre-processing image data.Be connected to SRAM device and ROM device on the system bus, and disposed multiple peripheral hardwares such as USB2.0, QDR, UART, ADC.Double-core is worked simultaneously, calculates and control parallel carrying out, and has improved processing power and speed, has more powerful efficient and performance with respect to single core processor.
Description of drawings
Fig. 1 is the fundamental block diagram of the utility model SoC.
Fig. 2 is the bus schematic diagram of the utility model SoC.
Fig. 3 is the basic structure block diagram of DSP nuclear in the utility model.
Embodiment
The utility model provides a kind of SoC that is applied to the isomorphism dual-core architecture of Flame Image Process.DSP has biases toward control; What have biases toward calculating, and in order to give full play to the dual-use function of computing and control, the utility model has overcome the defective of existing monokaryon DSP; A kind of SoC design of isomorphism double-core is provided; Taken into account programmed control and data computation,, be particularly suitable for applying to image processing field having obtained reinforcement aspect calculating and the control.Below in conjunction with accompanying drawing and embodiment the utility model is described further.
As shown in Figure 1; The utility model comprises: as a DSP of primary processor nuclear, as the 2nd DSP nuclear that calculates coprocessor, Flame Image Process interface module, image coprocessor, program storage block, data memory module, system control module, AES engine, two identical dma modules, ADC module, interrupt control module, serial interface module, and bus system, system peripheral module.Said image coprocessor links to each other with the Flame Image Process interface module; Link to each other with 64 AHB data buss through 64 AHB program buss between said DSP nuclear and the 2nd DSP nuclear; Said DSP nuclear and the 2nd DSP nuclear are through 64 AHB program bus linker memory modules; Said DSP nuclear is connected data memory module, dma module, ADC module with the 2nd DSP nuclear through 64 AHB data buss; Said DSP nuclear is connected AES engine, image coprocessor with the 2nd DSP nuclear through 32 AHB peripheral bus, and said DSP nuclear is connected interrupt control module, serial interface module, system control module, system peripheral module with the 2nd DSP nuclear through 32 APB buses.
DSP nuclear part adopts two identical 32 bit DSPs nuclears; Wherein comprise arithmetic unit and 16KB Instructions Cache, 4KB metadata cache, 24KB program RAM; The 124KB data RAM; Between link to each other shared bus with data bus through 64 AMBA (Advanced Microcontroller Bus Architecture) AHB (Advanced High-performance Bus, senior high performance bus) program bus.Two nuclears all have interruptable controller, can produce to interrupt and response is interrupted, and adopt interrupt mode to communicate between mutually.The one DSP nuclear is mainly done control usefulness, and the data that it handles needs are put among the SRAM, then the 2nd DSP are authorized interruption; Tell its data to deposit in; Can begin to calculate, the extraction data of having no progeny during the 2nd DSP nuclear is received begin to calculate the result, and the back is sent and interrupted back DSP nuclear; The one DSP nuclear is newly operated according to new data, has so just accomplished the communication of one whole.
The Flame Image Process interface module is used to import outside view data.
The image coprocessor receives and carries out pre-service the view data of Flame Image Process interface module sampling; Have interruptable controller, can produce and interrupt and the response interruption, and communicate with interrupt mode between the DSP nuclear.
System control module is made up of phase-locked loop pll (Phase Locked Loop) module, power management module, GPIO (general I/O) and JTAG (Joint Test Action Group, joint test behavior tissue) interface.The power management part links to each other with each module, for the nuclear and the peripheral hardware of chip are supplied power respectively, and the external crystal oscillator of phaselocked loop, for the sheet upper module provides the clock input, GPIO provides multiplexing external pin, and JTAG provides the standard testing interface.JTAG links to each other with 64 AHB program buss, and GPIO and PLL and 32 AMBA APB (Advanced Peripheral Bus, advanced peripheral bus) link to each other, and the power management part links to each other with each module.
Bus system is made up of 64 AHB data buss, 64 AHB program buss, 32 AHB peripheral bus, 32 APB peripheral bus.Bus portion links to each other with each module respectively.
Program storage block is connected mutually with two DSP nuclear through 64 AHB program buss, comprises the SRAM of 256KB on the sheet and BOOTROM and the outside FLASH interface of 16KB, can external FLASH extension storage space, be used for the memory image algorithm routine.
Data memory module; Be connected mutually with two DSP nuclears through 64 AHB data buss; The SRAM and 4 haplotype data multiplying power QDR (the Quad Data Rate) interface that comprise 256KB on the sheet can external high-speed SRAM extension storage spaces, are used for the data that memory image is calculated.
DES Cipher (Data Encryption Standard)/triple des (Triple DES) enciphering algorithm module links to each other with 32 AHB peripheral bus, is used for the data enciphering/deciphering; Guarantee the safety of SOC(system on a chip) communication data; Meet data encryption FIPS46-2 standard, possess the ahb bus slave interface of standard, support DES algorithm and triple des algorithm; Can select according to application demand; Optional 56bits, 112bits or 168bits key length satisfy different security intensity needs, and encryption and decryption speed reaches 1.6Gbits/s under the DES algorithm; Add, decipher speed under the triple des algorithm and reach 615Mbits/s, can satisfy most of system packet data processes demand.
Two identical dma modules link to each other with 64 AHB data buss, are used for moving of data between the storer.
14 analog/digital converter ADC (Analog to Digital Converter) module links to each other with 64 AHB data buss, for system provides simulating signal.
The interrupt control module links to each other with 32 AMBA APB (Advanced Peripheral Bus) peripheral bus, is used for arbitration process is carried out in the interruption of each module.
Serial interface module; Comprise USB2.0; Serial bus interface IIC (Inter-Integrated Circuit), serial digital audio bus interface IIS (Inter-IC Sound Bus), synchronous serial interface SSI (Synchronous Serial Interface); Universal asynchronous reception/dispensing device UART (Universal Asynchronous Receiver/Transmitter) interface; Wherein USB2.0 links to each other with 32 AHB peripheral bus, and all the other link to each other with 32 APB peripheral bus, is used for carrying out data communication outward with sheet.
System peripheral is made up of 4 timer TIMER and 8 pulse width regulator PWM, all links to each other with 32 APB peripheral bus.
The structure of bus system part is referring to Fig. 2; Two DSP are internuclear to be passed through 64 AHB program buss and links to each other with 64 AHB data buss and 32 AHB peripheral bus; Shared routing storer on the AHB program bus, shared data storer, dma module, ADC module on the AHB data bus.32 AHB peripheral bus link to each other with high-speed peripheral, and link to each other with 32 APB peripheral bus through bus bridge.32 APB peripheral bus link to each other with the low speed peripheral hardware.
As shown in Figure 3; Little No. 1 32 bit DSP processor cores in the utility model use; Adopt doubleclocking, three emitting structurals, comprise: get the multiplicaton addition unit MAC and the registers group that refer to unit, address arithmetic unit, data operation unit, adopt single-instruction multiple-data stream (SIMD) SIMD (Single Instruction Multiple Data); And link to each other with nuclear internal program storer, data-carrier store through 128 buses respectively.Whole nuclear links to each other with external bus through the ahb bus interface.Said address arithmetic parts comprise interconnected address ALU and address generator; Said data operation parts comprise interconnected ALU (ALU) and FPU Float Point Unit FPU; Instruction refers to get into address arithmetic unit, data operation unit and multiplicaton addition unit respectively after the unit is through decoding by getting, and accomplishes after the computing input register as a result.
Claims (7)
1. SoC towards Flame Image Process based on isomorphism double-core framework; It is characterized in that; Comprise: as a DSP of primary processor nuclear, as the 2nd DSP nuclear that calculates coprocessor, Flame Image Process interface module, image coprocessor, program storage block, data memory module, system control module, AES engine, two identical dma modules, ADC module, interrupt control module, serial interface module, and the system peripheral module; Said image coprocessor links to each other with the Flame Image Process interface module; Link to each other with 64 AHB data buss through 64 AHB program buss between said DSP nuclear and the 2nd DSP nuclear; Said DSP nuclear and the 2nd DSP nuclear are through 64 AHB program bus linker memory modules; Said DSP nuclear is connected data memory module, dma module, ADC module with the 2nd DSP nuclear through 64 AHB data buss; Said DSP nuclear is connected AES engine, image coprocessor with the 2nd DSP nuclear through 32 AHB peripheral bus, and said DSP nuclear is connected interrupt control module, serial interface module, system control module, system peripheral module with the 2nd DSP nuclear through 32 APB peripheral bus.
2. the SoC based on isomorphism double-core framework towards Flame Image Process as claimed in claim 1 is characterized in that, said DSP nuclear is identical with the 2nd DSP nuclear structure, all includes interruptable controller.
3. the SoC based on isomorphism double-core framework towards Flame Image Process as claimed in claim 2 is characterized in that, said DSP nuclear and the 2nd DSP nuclear comprise: get finger unit, address arithmetic unit, data operation unit, multiplicaton addition unit and registers group; Said address arithmetic parts comprise interconnected address ALU and address generator; Said data operation parts comprise interconnected ALU and FPU Float Point Unit FPU; Instruction refers to get into address arithmetic unit, data operation unit and multiplicaton addition unit respectively after the unit is through decoding by getting, and accomplishes after the computing input register as a result.
4. the SoC based on isomorphism double-core framework towards Flame Image Process as claimed in claim 1 is characterized in that said 16 image coprocessor comprises interruptable controller.
5. the SoC towards Flame Image Process as claimed in claim 1 based on isomorphism double-core framework; It is characterized in that; Said 32 AHB peripheral bus connect 32 APB peripheral bus through bus bridge, connect interrupt control module, serial interface module, system control module, system peripheral module again.
6. the SoC based on isomorphism double-core framework towards Flame Image Process as claimed in claim 5 is characterized in that, said system peripheral module comprises 4 timers and 8 pulse width regulator PWM.
7. the SoC towards Flame Image Process as claimed in claim 1 based on isomorphism double-core framework; It is characterized in that said serial interface module comprises: USB2.0 interface, serial bus interface IIC, serial digital audio bus interface IIS, synchronous serial interface SSI, UART interface.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103414854A (en) * | 2013-08-13 | 2013-11-27 | 三星半导体(中国)研究开发有限公司 | System-on-chip with image processing function and operation method thereof |
| CN104102553A (en) * | 2013-04-09 | 2014-10-15 | 纬创资通股份有限公司 | Operating system debugging device and operating system debugging method |
| CN105137864A (en) * | 2015-07-31 | 2015-12-09 | 上海卫星工程研究所 | Lower computer coordinative control SoC chip for spacecraft |
| CN105183432A (en) * | 2015-08-26 | 2015-12-23 | 中国航天科工集团第三研究院第八三五七研究所 | Health management oriented SOC system |
| CN108228525A (en) * | 2016-12-13 | 2018-06-29 | 北京迪文科技有限公司 | A kind of the application solutions device and method of 8051 processor SOC of multinuclear |
| CN108519953A (en) * | 2018-04-17 | 2018-09-11 | 长沙景美集成电路设计有限公司 | A kind of GPGPU debugging techniques realization based on JTAG |
| US10481957B2 (en) | 2015-09-28 | 2019-11-19 | Sanechips Technology Co., Ltd. | Processor and task processing method therefor, and storage medium |
| CN111983952A (en) * | 2020-08-11 | 2020-11-24 | 武汉瑞纳捷电子技术有限公司 | Design method and circuit of motor control MCU chip with dual-core structure |
| CN113961507A (en) * | 2021-10-20 | 2022-01-21 | 深圳市创成微电子有限公司 | Single-core DSP (digital Signal processor) framework and dual-core DSP framework |
| WO2022252715A1 (en) * | 2021-12-29 | 2022-12-08 | 杭州万高科技股份有限公司 | Dual-core heterogeneous soc chip |
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2012
- 2012-03-28 CN CN 201220125183 patent/CN202534008U/en not_active Expired - Lifetime
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104102553A (en) * | 2013-04-09 | 2014-10-15 | 纬创资通股份有限公司 | Operating system debugging device and operating system debugging method |
| CN103414854B (en) * | 2013-08-13 | 2017-04-19 | 三星半导体(中国)研究开发有限公司 | System-on-chip with image processing function and operation method thereof |
| CN103414854A (en) * | 2013-08-13 | 2013-11-27 | 三星半导体(中国)研究开发有限公司 | System-on-chip with image processing function and operation method thereof |
| CN105137864A (en) * | 2015-07-31 | 2015-12-09 | 上海卫星工程研究所 | Lower computer coordinative control SoC chip for spacecraft |
| CN105183432A (en) * | 2015-08-26 | 2015-12-23 | 中国航天科工集团第三研究院第八三五七研究所 | Health management oriented SOC system |
| CN105183432B (en) * | 2015-08-26 | 2018-02-27 | 中国航天科工集团第三研究院第八三五七研究所 | A kind of SoC systems towards health control |
| US10481957B2 (en) | 2015-09-28 | 2019-11-19 | Sanechips Technology Co., Ltd. | Processor and task processing method therefor, and storage medium |
| CN108228525A (en) * | 2016-12-13 | 2018-06-29 | 北京迪文科技有限公司 | A kind of the application solutions device and method of 8051 processor SOC of multinuclear |
| CN108228525B (en) * | 2016-12-13 | 2021-09-24 | 北京迪文科技有限公司 | Device and method for safely realizing SOC (system on chip) of multi-core 8051 processor |
| CN108519953A (en) * | 2018-04-17 | 2018-09-11 | 长沙景美集成电路设计有限公司 | A kind of GPGPU debugging techniques realization based on JTAG |
| CN111983952A (en) * | 2020-08-11 | 2020-11-24 | 武汉瑞纳捷电子技术有限公司 | Design method and circuit of motor control MCU chip with dual-core structure |
| CN113961507A (en) * | 2021-10-20 | 2022-01-21 | 深圳市创成微电子有限公司 | Single-core DSP (digital Signal processor) framework and dual-core DSP framework |
| WO2022252715A1 (en) * | 2021-12-29 | 2022-12-08 | 杭州万高科技股份有限公司 | Dual-core heterogeneous soc chip |
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