CN108228525A - A kind of the application solutions device and method of 8051 processor SOC of multinuclear - Google Patents
A kind of the application solutions device and method of 8051 processor SOC of multinuclear Download PDFInfo
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- CN108228525A CN108228525A CN201611145616.3A CN201611145616A CN108228525A CN 108228525 A CN108228525 A CN 108228525A CN 201611145616 A CN201611145616 A CN 201611145616A CN 108228525 A CN108228525 A CN 108228525A
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- modules
- data
- jtag
- soc
- spi flash
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/781—On-chip cache; Off-chip memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/606—Protecting data by securing the transmission between two devices or processes
Abstract
The present invention relates to the encryption methods and device of data exchange between FLASH outside 8051 processor SOC of multinuclear and piece.The application solutions apparatus system of the present invention includes multiple 8051 processors, JTAG Controller, Code＆Data SRAM and encrypting and decrypting processing module；Encrypting module includes MUX modules, Efuse modules, JTAG security modules, Spi flash controller modules.Carry out the read-write of external SPI FLASH between processor based on unique CODE that EFUSE is generated by Spi flash controller modules；The jtag interface of 8051 SOC of double-core is communicated by JTAG Controller with JTAG security modules, JTAG security modules carry out encryption and decryption processing by unique CODE that EFUSE modules generate, and the read-write for finally carrying out data with SPI FLASH again exchanges.
Description
Technical field
The present invention relates to processor security fields, and in particular to data between 8051 processor SOC of multinuclear and the outer FLASH of piece
The encryption method and device of exchange.
Background technology
8051 core processors do not have on piece mass data storage space usually, it is therefore desirable to external to store data
Chip, one of which be applicable in hyundai electronics industry very extensive cheap, superior performance chip storage be situated between-
SPI FLASH operate and give birth to.But since the SPI FLASH of standard itself do not have encrypted ability, SPI to data
The Information Security of FLASH is endured to the fullest extent always to denounce.
FLASH chip, Chinese entitled " flash memory " belong to one kind of memory devices.The physical characteristic of flash memory with it is common interior
There is the difference of essence, i.e., all kinds of DDR, SDRAM or RDRAM belong to volatile memory, as long as stopping in electric current supply
Data in depositing just cannot keep, therefore booting computer is required for a data to be loaded into memory again every time；And flash memory is then a kind of
Non-volatile (Non-Volatile) memory also can muchly keep data under conditions of the supply of no electric current, store
Characteristic is equivalent to hard disk, this characteristic is exactly the basis for the storage medium that flash memory is able to as all kinds of pocket digital devices.
NOR and NAND is two kinds of main nonvolatile flash memory technologies in the market.Intel developed NOR first in 1988
Flash technologies revolutionize the situation originally to be ruled all the land by EPROM and EEPROM.And then, 1989, Toshiba
NAND flash structures have been delivered, have emphasized to reduce the cost of every bit, higher performance, and can be by connecing as disk
Pine upgrading fond of food that is not salty.
SPI is the abbreviation of Serial Peripheral Interface (SPI) (Serial Peripheral Interface).SPI is a kind of high speed
, full duplex, synchronous communication bus, and four lines are only taken up on the pin of chip, the pin of chip is saved, simultaneously
To save space in the layout of PCB, provide conveniently, exactly for this characteristic easy to use, nowadays more and more chips
It is integrated with this communication protocol, such as the FLASH chip of included SPI interface.
The Principle of Communication of SPI is very simple, it is worked with master-slave mode, this pattern usually there are one main equipment and one or
Multiple slave devices need at least 4 lines, in fact 3 can also be (during one-way transmission).And all equipment based on SPI are total to
Have, they are SDI (data input), SDO (data output), SCLK (clock), CS (piece choosing).
Although the FLASH chip of SPI interface is propagated its belief on a large scale, the Information Security one that is stored in SPI FLASH
It is directly a big problem.By it increasingly it is widely used in 8051 processor of multinuclear, and data encryption is well-done very
It is few.
Invention content
The application solutions device and method of 8051 processor SOC of a kind of multinuclear provided by the invention to be saved in SPI
The data of FLASH can obtain safest protection.Enable in this way user data and core code safety operate in SOC
On.This safety device and Technical Design are simple, realization area and power consumption all very littles on SOC.
The technical solution that the present invention solves above-mentioned technical problem is as follows：Installation based on 8051 processor SOC of double-core is realized
Apparatus system, including 8,051 8051 System of System, CPU1 of CPU0, JTAG Controller, Code＆Data SRAM
And encrypting and decrypting processing module；
8051 System of CPU0 are one of composition core for 8051 SOC systems of double-core, for entire double-core
One of processor of 8051 processing data；
8051 System of CPU1 are one of composition core for 8051 SOC systems of double-core, for entire double-core
One of processor of 8051 processing data；
The JTAG Controller are external download and the emulation interface of 8051 SOC systems of double-core, for double-core
8051 program development and burning program；
The Code＆Data SRAM are the internal code of 8051 SOC systems of double-core and the high-speed buffer of data, are
Code and data provide reliable buffering section；
The encrypting and decrypting processing module, including MUX modules, Efuse modules, JTAG security modules, Spi
Flash controller modules.
The MUX modules, are to have the function of data selection logic, for determining and switching JTAG security modules
With Spi flash controller modules and the sequential of the data exchange of Spi flash；
The Efuse modules, are electronic fuses, and unique identifier can be made by Efuse modules, is mainly supplied to
The CODE that chip encryption and decryption needs, every SOC have corresponding unique CODE, and SOC algoritic modules can be generated according to the CODE
Corresponding encryption and decryption mark.All it is different and unique between can accomplishing each chip by unique encryption and decryption mark
's；
The JTAG security modules, predominantly JTAG access SPI FLASH and carry out encryption and decryption, by the module, allow
It is not transparent transmission that JTAG data access Spi flash by 8051 SOC of double-core, but further through encrypted transmission so that number
All it is by encrypted according to wherefrom reading or being written Spi flash；
The Spi flash controller modules, predominantly CPU access SPI FLASH and carry out encryption and decryption, either
CPU0 or CPU1, two CPU read and access Spi flash and will be ensured by the encryption and decryption of module progress data
The encryption of data transmission.The operand of CPU0 and CPU1 for data encrypting and deciphering can be mitigated again, do not need to complexity more
Encryption Algorithm aggravates the processing load of CPU0 and CPU1.
The beneficial effects of the invention are as follows：The read-write of SPI FLASH can be carried out completely by encryption and decryption processing module complete
Journey data encryption, and for CPU, completely may be used by independent encryption and decryption processing module to the reading and writing data of SPI FLASH
It is transparent can be regarded as.In this way, depth S PI FLASH and multinuclear are completed on the basis of extra power consumption and workload is not increased
The processing of data encrypting and deciphering between 8051 SOC.
Based on the above technical solution, the present invention can also be improved as follows：
Further, the MUX selects logic functional block present position in external SPI FLASH and JTAG security
Between module and Spi flash controller modules；
Further, logic module and SPI FLASH and JTAG security modules and Spi flash are selected by MUX
Effective cooperation between controller modules, being allowed to SPI FLASH and 8051 SOC of double-core can the smooth reading for carrying out data
Write operation.
Advantageous effect using above-mentioned further scheme is：By MUX select logic module, can to avoid jtag interface with
And there is the problem of fighting for SPI FLASH controls in two CPU of 8051 SOC of internal double-core.
Further, unique identification code is generated by EFUSE modules.
Further, unique identifier JTAG security and the Spi flash generated by EFUSE modules
Controller can generate encryption data by unique identifier by hardware logic.
Advantageous effect using above-mentioned further scheme is：8051 SOC systems of double-core for SPI FLASH data into
It is unidentical encryption method from each other that row read-write, which is to encrypt completely and is same model chip,.
Based on the method that 8051 SOC system application solutions device of double-core is realized, include the following steps:
Step 1, the CPU0 and CPU1 of 8051 SOC of double-core is based on EFUSE by Spi flash controller modules
The unique CODE generated carries out the read-write of external SPI FLASH；
Step 2, the jtag interface of 8051 SOC of double-core by JTAG Controller and JTAG security modules into
Row communication, JTAG security modules carry out encryption and decryption processing by unique CODE that EFUSE modules generate, finally again with SPI
The read-write that FLASH carries out data exchanges；
Step 3, JTAG security modules and Spi flash controller modules are selected by MUX hardware logics
The judgement of module carries out in time domain and judgement in logic, which module determine to communicate with SPI FLASH after ruling is.
The beneficial effects of the invention are as follows：The unique CODE generated by the EFUSE above 8051 processor SOC of double-core, and
It is handled by the encryption and decryption of JTAG security modules and Spi flash controller modules and obtains encryption and decryption data,
And then the data inside 8051 processor SOC of double-core and the data being stored in external SPI FLASH are separated, it is only logical
Crossing safety device could normally be communicated between the two, and be encrypted.In this way, it avoids at traditional multinuclear 8051
Simple question is not encrypted and encrypted to reason device SOC system externals data.
Based on the above technical solution, the present invention can also be improved as follows：
Further, when unique CODE digits that EFUSE modules generate are not presetting digit capacities, the Spi of the step 1
Flash controller modules will not carry out encryption and decryption read-write operation to data, prevent data and mistake is caused because of abnormal
Implementing result.
Further, when unique CODE digits that EFUSE modules generate are not presetting digit capacities, the JTAG of the step 2
Security modules will not carry out encryption and decryption read-write operation to data, prevent data and wrong execution knot is caused because of abnormal
Fruit.
Further, when JTAG security modules and Spi flash controller modules find to switch by MUX
The data read and write afterwards back find data exception by decryption, then JTAG security modules and Spi flash
Controller modules no longer will carry out encryption and decryption read-write operation to data, prevent data and wrong execution is caused because of abnormal
As a result.
Advantageous effect using above-mentioned further scheme is：Can avoid because chip by outside or inside damage or
The correctness of reading and writing data is destroyed and destroyed, is prevented because the data of mistake cause the CPU of 8051 processor of multinuclear to make mistake
Operation in turn result in mistake output, so as to fulfill the comprehensive high reliability of Information Security and chip.
Description of the drawings
Fig. 1 is 8051 SOC internal system configuration diagrams of double-core in the present invention；
Fig. 2 is the configuration diagram of safety device in the present invention；
Fig. 3 is safety device implementation method flow diagram in the present invention；
Specific embodiment
The principle and features of the present invention will be described below with reference to the accompanying drawings, and the given examples are served only to explain the present invention, and
It is non-to be used to limit the scope of the present invention.
As shown in Figure 1, realize system based on multinuclear 8051SOC erecting devices for the present invention is a kind of, including jtag interface 1,
CPU0 systems 2 in 8051 SOC of double-core, the CPU1 systems 3 in 8051 SOC of double-core, JTAG CONTROLLER 4, SPI
FLASH 5 and safety device system 6；
As shown in Fig. 2, the composition of safety device system by EFUSE electronic fuses 61, MUX Digital Logic selector 63,
JTAG SECURITY 64 and 62 control modules of SPI FLASH CONTROLLER composition.
The data that external SPIFLASH is accessed for JTAG first have to pretreatment by JTAG CONTROLLER 4,
The data that JTAG CONTROLLER analyze JTAG are to be sent by the either CPU1 systems 3 of CPU0 systems 2, concurrent data
To corresponding cpu system, finally by being sent to MUX mathematical logics selecting module 63 after 64 encryption and decryption of JTAG SECURITY modules
Afterwards final data read-write operation is carried out with SPI FLASH 5 again.
CPU0 systems 2 or CPU1 systems 3 for internal system will directly access SPI FLASH 5, then need to pass through
SPI FLASH CONTROLLER modules 62 carry out encryption and decryption, pass through the selection of MUX mathematical logics selector 63 again after encryption and decryption
Carry out the read-write operation of data with SPI FLASH 5 again afterwards.
As shown in Fig. 2, the encryption of JTAG SECURITY modules 64 and SPI FLASH CONTROLLER modules 62 is all
It is realized by unique CODE of the generation of DFUSE electronic fuses 61, the 8051 SOC systems of double-core of each same model
It with unique CODE, and does not duplicate, therefore the encryption and decryption data that cannot can not be made identically by the CODE.
As shown in figure 3, the method for the application solutions device based on 8051 processor SOC of multinuclear, includes the following steps：
Step 1, unique CODE is generated by EFUSE modules 61；
Step 2, JTAG SECUIRTY modules 64 and SPI FLASH CONTROLLER modules 62 according to the CODE into line number
According to encryption and decryption；
Step 3, the 63 pieces of adjustment of MUX logics selection mould and the data exchange logic of FLASH；
Step 4, finally realize that 8051 processor SOC of double-core exchanges read-write operation with the encryption data of SPI FLASH 5.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all the present invention spirit and
Within principle, any modification, equivalent replacement, improvement and so on should all be included in the protection scope of the present invention.
Claims (9)
1. a kind of the application solutions device and method of 8051 processor SOC of multinuclear, which is characterized in that handled based on double-core 8051
The installation realization device system of device SOC, including CPU0 8051 System, CPU1 8051 System, JTAG
Controller, Code＆Data SRAM and encrypting and decrypting processing module；
8051 System of CPU0 and 8051 System of CPU1 are one of composition core of 8051 SOC systems of double-core,
One of processor for entire double-core 8051 processing data；
The JTAG Controller are external download and the emulation interface of 8051 SOC systems of double-core, for double-core 8051
Program development and burning program；
The Code＆Data SRAM are the internal code of 8051 SOC systems of double-core and the high-speed buffer of data, are code
Reliable buffering section is provided with data；
The encrypting and decrypting processing module is used to implement the encryption and decryption of data transmission.
2. the application solutions device and method, feature of a kind of 8051 processor SOC of multinuclear as described in claim 1 exist
In encrypting module, including MUX modules, Efuse modules, JTAG security modules, Spi flash controller moulds
Block.
3. the application solutions device and method, feature of a kind of 8051 processor SOC of multinuclear as claimed in claim 2 exist
In the MUX modules, are to have the function of data selection logic, for determining and switching JTAG security modules and Spi
The sequential of flash controller modules and the data exchange of Spi flash；
The Efuse modules, are electronic fuses, and unique identifier can be made by Efuse modules, is mainly supplied to chip
The CODE that encryption and decryption needs, every SOC have corresponding unique CODE, and SOC algoritic modules can generate corresponding according to the CODE
Encryption and decryption mark.All it is different and unique between can accomplishing each chip by unique encryption and decryption mark；
The JTAG security modules, predominantly JTAG access SPI FLASH and carry out encryption and decryption, by the module, allow JTAG
It is not transparent transmission that data access Spi flash by 8051 SOC of double-core, but further through encrypted transmission so that data without
All it is by encrypted by wherefrom reading or being written Spi flash；
The Spi flash controller modules, predominantly CPU access SPI FLASH and carry out encryption and decryption, either CPU0
Or CPU1, two CPU, which read and access Spi flash, to ensure data by the encryption and decryption of module progress data
The encryption of transmission.The operand of CPU0 and CPU1 for data encrypting and deciphering can be mitigated again, do not need to complicated encryption more
Algorithm aggravates the processing load of CPU0 and CPU1.
4. the application solutions device and method, feature of a kind of 8051 processor SOC of multinuclear as claimed in claim 2 exist
In MUX selects logic functional block present position in external SPI FLASH and JTAG security modules and Spi flash
Between controller modules；Logic module and SPI FLASH and JTAG security modules and Spi are selected by MUX
Effective cooperation between flash controller modules, being allowed to SPI FLASH and 8051 SOC of double-core can be smooth into line number
According to read-write operation.
5. the application solutions device and method, feature of a kind of 8051 processor SOC of multinuclear as claimed in claim 2 exist
Generate unique identification code in, EFUSE modules, the unique identifier JTAG security generated by EFUSE modules with
And Spi flash controller can generate encryption data by unique identifier by hardware logic.
6. the application solutions device and method, feature of a kind of 8051 processor SOC of multinuclear as described in claim 1 exist
In mainly including the following steps that：
Step 1, the CPU0 and CPU1 of 8051 SOC of double-core are produced by Spi flash controller modules based on EFUSE
Raw unique CODE carries out the read-write of external SPI FLASH；
Step 2, the jtag interface of 8051 SOC of double-core are led to by JTAG Controller and JTAG security modules
Letter, JTAG security modules carry out encryption and decryption processing by unique CODE that EFUSE modules generate, finally again with SPI
The read-write that FLASH carries out data exchanges；
Step 3, JTAG security modules and Spi flash controller modules pass through MUX hardware logic selecting modules
Judgement carry out in time domain and judgement in logic, determine which module communicate with SPI FLASH is after ruling.
7. the application solutions device and method, feature of a kind of 8051 processor SOC of multinuclear as claimed in claim 6 exist
In, when unique CODE digits that EFUSE modules generate are not presetting digit capacities, the Spi flash of the step 1
Controller modules will not carry out encryption and decryption read-write operation to data, prevent data and wrong execution knot is caused because of abnormal
Fruit.
8. the application solutions device and method, feature of a kind of 8051 processor SOC of multinuclear as claimed in claim 6 exist
In when unique CODE digits that EFUSE modules generate are not presetting digit capacities, the JTAG security modules of the step 2 will
Encryption and decryption read-write operation is not carried out to data, prevent data and wrong implementing result is caused because of abnormal.
9. the application solutions device and method, feature of a kind of 8051 processor SOC of multinuclear as claimed in claim 6 exist
In, when JTAG security modules and Spi flash controller modules discovery switch by MUX after read and write return
Data find data exception by decryption, then JTAG security modules and Spi flash controller modules will not
Encryption and decryption read-write operation is carried out to data again, data is prevented and wrong implementing result is caused because of abnormal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611145616.3A CN108228525B (en) | 2016-12-13 | 2016-12-13 | Device and method for safely realizing SOC (system on chip) of multi-core 8051 processor |
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| CN201611145616.3A CN108228525B (en) | 2016-12-13 | 2016-12-13 | Device and method for safely realizing SOC (system on chip) of multi-core 8051 processor |
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| CN108228525B CN108228525B (en) | 2021-09-24 |
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Cited By (1)
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| CN109446021A (en) * | 2018-09-30 | 2019-03-08 | 中国气象局气象探测中心 | A kind of DDR monitoring method for aerostatics Occultation receiver double-core SOC |
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