CN113961507A - Single-core DSP (digital Signal processor) framework and dual-core DSP framework - Google Patents
Single-core DSP (digital Signal processor) framework and dual-core DSP framework Download PDFInfo
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Abstract
The invention discloses a single-core DSP processor architecture and a dual-core DSP processor architecture, wherein the single-core DSP processor architecture comprises a DSP core, a delay line bus, a delay line controller, a data bus, a program bus, a data memory, a program memory, a bus main interface and at least one algorithm module, wherein the DSP core is communicated with the program memory through the program bus; the DSP core is communicated with the delay line controller through the delay line bus; the DSP core is communicated with the data memory and the at least one algorithm module through the data bus; the DSP kernel is connected with the bus main interface and used for information interaction when the DSP processor is used as a main device to access external slave devices. The DSP processor architecture of the invention improves the system performance of the DSP processor.
Description
Technical Field
The invention relates to the technical field of DSP processors, in particular to a single-core DSP processor architecture and a dual-core DSP processor architecture.
Background
DSP has wide application in audio, video and motor control. As user demands increase, systems place higher demands on the performance of DSP processors. In the current DSP processor architecture, the DSP processor can only interact with an external device as a slave device, but not with an external slave device as a master device.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a single-core DSP processor architecture and a dual-core DSP processor architecture, so as to solve the defects in the prior art that a DSP processor cannot be used as a master device to access an external slave device and a DSP core interacts with a delay line controller through a data line, which results in the performance of the delay line controller being affected.
A first aspect of the present invention provides a single core DSP processor architecture, comprising: a DSP core, a delay line bus, a delay line controller, a data bus, a program bus, a data memory, a program memory, a bus master interface, and at least one algorithm module,
the DSP core is communicated with the program memory through the program bus;
the DSP core is communicated with the delay line controller through the delay line bus;
the DSP core is communicated with the data memory and the at least one algorithm module through the data bus;
the DSP kernel is connected with the bus main interface and used for information interaction when the DSP processor is used as a main device to access external slave devices.
Preferably, the single-core DSP processor architecture further comprises a trigger source for controlling a running time of the DSP processor.
Preferably, the delay line controller includes an internal delay line controller and an external delay line controller, the delay line bus includes an internal delay line bus and an external delay line bus, wherein the DSP core communicates with the internal delay line controller through the internal delay line bus, and the DSP core communicates with the external delay line controller through the external delay line bus.
Preferably, the single-core DSP processor architecture further comprises a bus slave interface, the bus slave interface being connected with the data bus.
Preferably, the data memory comprises an internal data memory and an external data memory, wherein the DSP core communicates with the internal data memory via the data bus and the DSP core communicates with the external data memory via the data bus.
A second aspect of the present invention provides a dual-core DSP processor architecture, comprising a master DSP processor, a slave DSP processor, a system bus, a first dual-end memory, a second dual-end memory, an arbiter, a second data bus, and a third data bus, the master DSP processor employing the single-core DSP processor architecture of claim 1, the slave DSP processor employing the single-core DSP processor architecture of claim 1, wherein,
the delay line controller of the master DSP processor is connected with the arbiter, and the delay line controller of the slave DSP processor is connected with the arbiter;
and the bus main interface of the master DSP processor is connected with the system bus, and the bus main interface of the slave DSP processor is connected with the system bus.
Preferably, the single-core DSP processor architecture further comprises a trigger source, wherein an input of the trigger source of the master DSP processor is connected with an input of the trigger source of the slave DSP processor.
Preferably, the delay line controller includes an internal delay line controller and an external delay line controller, the arbiter includes a first arbiter and a second arbiter, wherein,
the internal delay line controller of the master DSP processor is connected with the first arbiter, the internal delay line controller of the slave DSP processor is connected with the first arbiter, the external delay line controller of the master DSP processor is connected with the second arbiter, and the external delay line controller of the slave DSP processor is connected with the second arbiter.
Preferably, the single core DSP processor architecture further comprises a bus slave interface, wherein,
the bus slave interface of the master DSP processor communicates with the system bus, and the bus slave interface of the slave DSP processor communicates with the system bus.
Preferably, the dual core DSP processor architecture further comprises a first dual-end memory and a second dual-end memory, wherein,
the external data memory of the master DSP processor is in communication connection with the first dual-port memory and used for reading data from the first dual-port memory, the external data memory of the slave DSP processor is in communication connection with the first dual-port memory and used for writing data into the first dual-port memory, the external memory of the master DSP processor is also in communication connection with the second dual-port memory and used for writing data into the second dual-port memory, and the external data memory of the slave DSP processor is in communication connection with the second dual-port memory and used for reading data from the second dual-port memory
The embodiment of the invention has the following beneficial effects: the DSP processor architecture adopts a Harvard architecture, a program bus and a data bus are always separated, the data throughput of the bus is improved, the system performance is improved, the DSP processor can be used as a main device to actively access the bus by arranging a bus main interface module, and the highest reading efficiency of the audio data of a delay line can be realized by adopting an independent bus mounting delayer.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is within the scope of the present invention for those skilled in the art to obtain other drawings based on the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram illustrating a single-core DSP processor architecture according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram illustrating a dual-core DSP processor architecture according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings.
An embodiment of the present invention provides a single-core DSP processor architecture, as shown in fig. 1, which includes a DSP core, a delay line bus, a delay line controller, a first data bus, a program bus, a data memory, a program memory, a bus master interface, and at least one algorithm module, where the DSP core communicates with the program memory through the program bus, and the DSP core communicates with the delay line controller through the delay line bus; the DSP core is communicated with the data memory and the at least one algorithm module through the data bus, and the DSP core is connected with the bus main interface and used for interaction when the DSP processor is used as a main device to communicate with an external slave device.
In a specific embodiment, the at least one algorithm module may be a module implementing an audio processing algorithm, such as a fft (fourier transform) module, a filtering algorithm module, and the like.
In a specific embodiment, the architecture of the DSP processor further includes a trigger source, an output end of the trigger source is connected to an input end of the DSP core, and is configured to control a running time of the DSP processor. For example, in an audio system, the DSP may be triggered by a 48KHz interrupt generated by an I2S peripheral, so that the DSP may operate in synchronization with the audio stream.
In one embodiment, the delay line controller comprises an internal delay line controller and an external delay line controller, the delay line bus comprises an internal delay line bus and an external delay line bus, the DSP core communicates with the internal delay line controller via the internal delay line bus, and the DSP core communicates with the external delay line controller via the external delay line bus. In the DSP processor architecture, an internal delay controller and an external delay controller are mounted by adopting independent buses, so that the highest reading efficiency of the audio data of the delay line can be realized.
In one embodiment, the single-core DSP processor architecture further includes a bus slave interface, the DSP core communicating with the bus slave interface via a data bus for interaction when the DSP processor is in communication with an external master device as a slave device.
Specifically, the data memory comprises an internal data memory and an external data memory, the DSP core is communicated with the internal data memory through a data bus, the internal data memory is a data storage space in the DSP processor, the address space can be directly accessed by an LDR/STR instruction of the DSP processor, the DSP core is communicated with the external data memory through the data bus, and the external data memory has two functions, namely, on one hand, the data storage space is used for expanding the DSP, on the other hand, the data storage space of the algorithm module can be mounted on the address space, so that the DSP core can flexibly access the data of the algorithm.
The single-core DSP processor architecture of the embodiment of the invention adopts a Harvard architecture, a program bus and a data bus are always separated, the data throughput of the bus is improved, the system performance is improved, the DSP processor can be used as a main device to actively access the bus by arranging a bus main interface module, and the highest reading efficiency of the audio data of a delay line can be realized by adopting an independent bus mounting delayer.
Based on the first embodiment of the present invention, the second embodiment of the present invention provides a dual-core DSP processor architecture, as shown in fig. 2, the dual-core DSP processor architecture includes a master DSP processor, a slave DSP processor, a system bus, a first dual-port memory, a second dual-port memory, an arbiter, a second data bus, and a third data bus, wherein the master DSP processor adopts the single-core DSP processor architecture according to the first embodiment of the present invention, and the slave DSP processor adopts the single-core DSP processor architecture according to the first embodiment of the present invention, wherein a delay line controller of the master DSP processor is connected to the arbiter, and a delay line controller of the slave DSP processor is connected to the arbiter; and the bus main interface of the master DSP processor is connected with the system bus, and the bus main interface of the slave DSP processor is connected with the system bus.
The master DSP processor and the slave DSP processor both comprise trigger source input ends, wherein the trigger source input ends of the master DSP processor and the slave DSP processor are connected.
The arbiter comprises a first arbiter and a second arbiter, the internal delay line controller of the master DSP processor is connected to the first arbiter, the internal delay line controller of the slave DSP processor is connected to the first arbiter, the external delay line controller of the master DSP processor is connected to the second arbiter, and the external delay line controller of the slave DSP processor is connected to the second arbiter. In the dual-core DSP processor architecture, an internal delay line controller and an external delay line controller between the dual cores are added into an arbitration module, because two DSP systems can send out delay line control signals at the same time, at this time, the priority of a main DSP is highest.
The bus slave interface of the master DSP processor is communicated with the system bus, and the bus slave interface of the slave DSP processor is communicated with the system bus.
The dual-core DSP processor architecture further includes a first dual-end memory and a second dual-end memory, where an external data memory of the master DSP processor is communicatively connected to the first dual-end memory, and is configured to read data from the first dual-end memory, an external data memory of the slave DSP processor is communicatively connected to the first dual-end memory, and is configured to write data into the first dual-end memory, and the external data memory of the master DSP processor is communicatively connected to the second dual-end memory, and is configured to write data into the second dual-end memory, and the external data memory of the slave DSP processor is communicatively connected to the second dual-end memory, and is configured to read data from the second dual-end memory.
While the invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not to be limited to the disclosed embodiment, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (10)
1. A single core DSP processor architecture, comprising: a DSP core, a delay line bus, a delay line controller, a data bus, a program bus, a data memory, a program memory, a bus master interface, and at least one algorithm module,
the DSP core is communicated with the program memory through the program bus;
the DSP core is communicated with the delay line controller through the delay line bus;
the DSP core is communicated with the data memory and the at least one algorithm module through the data bus;
the DSP kernel is connected with the bus main interface and used for information interaction when the DSP processor is used as a main device to access external slave devices.
2. The DSP processor architecture of claim 1 wherein the single core DSP processor architecture further includes a trigger source for controlling a runtime of the DSP processor.
3. The DSP processor architecture of claim 2 wherein the delay line controller comprises an internal delay line controller and an external delay line controller, the delay line bus comprising an internal delay line bus and an external delay line bus, wherein the DSP core communicates with the internal delay line controller via the internal delay line bus and the DSP core communicates with the external delay line controller via the external delay line bus.
4. The DSP processor architecture of claim 3, wherein the single core DSP processor architecture further comprises a bus slave interface, the bus slave interface being connected with the data bus.
5. The DSP processor architecture of claim 4, wherein the data memory comprises an internal data memory and an external data memory, wherein the DSP core communicates with the internal data memory over the data bus and the DSP core communicates with the external data memory over the data bus.
6. A dual core DSP processor architecture comprising a master DSP processor employing the single core DSP processor architecture of claim 1, a slave DSP processor employing the single core DSP processor architecture of claim 1, a system bus, a first dual-port memory, a second dual-port memory, an arbiter, a second data bus, a third data bus, wherein,
the delay line controller of the master DSP processor is connected with the arbiter, and the delay line controller of the slave DSP processor is connected with the arbiter;
and the bus main interface of the master DSP processor is connected with the system bus, and the bus main interface of the slave DSP processor is connected with the system bus.
7. The dual core DSP processor architecture of claim 6, further comprising a trigger source, wherein an input of the trigger source of the master DSP processor is connected to an input of the trigger source of the slave DSP processor.
8. The dual core DSP processor architecture of claim 7, wherein the delay line controller comprises an internal delay line controller and an external delay line controller, the arbiters comprising a first arbiter and a second arbiter, wherein,
the internal delay line controller of the master DSP processor is connected with the first arbiter, the internal delay line controller of the slave DSP processor is connected with the first arbiter, the external delay line controller of the master DSP processor is connected with the second arbiter, and the external delay line controller of the slave DSP processor is connected with the second arbiter.
9. The dual core DSP processor architecture of claim 8, further comprising a bus slave interface, wherein,
the bus slave interface of the master DSP processor communicates with the system bus, and the bus slave interface of the slave DSP processor communicates with the system bus.
10. The dual core DSP processor architecture of claim 9, further comprising a first dual-end memory and a second dual-end memory, wherein,
the external data memory of the master DSP processor is communicatively connected to the first dual-port memory, and is configured to read data from the first dual-port memory, the external data memory of the slave DSP processor is communicatively connected to the first dual-port memory, and is configured to write data into the first dual-port memory, the external memory of the master DSP processor is further communicatively connected to the second dual-port memory, and is configured to write data into the second dual-port memory, and the external data memory of the slave DSP processor is communicatively connected to the second dual-port memory, and is configured to read data from the second dual-port memory.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN202534008U (en) * | 2012-03-28 | 2012-11-14 | 中国电子科技集团公司第五十八研究所 | Isomorphic dual-core structure-based SoC applied to image processing |
| CN103218338A (en) * | 2013-03-19 | 2013-07-24 | 中国科学院声学研究所 | Real-time multi-DSP (digital signal processor) debugging system for signal processor system |
| CN105262659A (en) * | 2015-11-02 | 2016-01-20 | 日立永济电气设备（西安）有限公司 | HDLC protocol controller based on FPGA chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN202534008U (en) * | 2012-03-28 | 2012-11-14 | 中国电子科技集团公司第五十八研究所 | Isomorphic dual-core structure-based SoC applied to image processing |
| CN103218338A (en) * | 2013-03-19 | 2013-07-24 | 中国科学院声学研究所 | Real-time multi-DSP (digital signal processor) debugging system for signal processor system |
| CN105262659A (en) * | 2015-11-02 | 2016-01-20 | 日立永济电气设备（西安）有限公司 | HDLC protocol controller based on FPGA chip |
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