CN202394891U - 一种中心布线双圈排列ic芯片堆叠封装件 - Google Patents

一种中心布线双圈排列ic芯片堆叠封装件 Download PDF

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CN202394891U
CN202394891U CN2011205682121U CN201120568212U CN202394891U CN 202394891 U CN202394891 U CN 202394891U CN 2011205682121 U CN2011205682121 U CN 2011205682121U CN 201120568212 U CN201120568212 U CN 201120568212U CN 202394891 U CN202394891 U CN 202394891U
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朱文辉
郭小伟
慕蔚
李习周
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Tianshui Huatian Technology Co Ltd
Huatian Technology Xian Co Ltd
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Huatian Technology Xian Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

一种中心布线双圈排列IC芯片堆叠封装件，是在引线框架载体上粘接、堆叠有二层IC芯片，第一IC芯片外侧设有中心布线环，中心布线环的外部设有两圈内引脚，中心布线环上设有内外两圈焊盘，所述内圈焊盘分别与第一IC芯片和第二IC芯片的焊盘打线，所述外圈焊盘分别与第一内引脚和第二内引脚打线。本实用新型把中心布线环和双圈排列凸点巧妙结合，中心布线环通过高强度胶与引线框架载体相接或镶嵌，增强了塑封料与框架的结合，减薄了框架厚度，防止分层，有利于提高产品的可靠性。中心布线环上2圈焊盘通过PCB设计线路相通，并作为IC芯片通过中心布线环内部线路的转换实现与内引脚间导通，减少焊线长度，节约焊线成本，尤其是金线的使用成本。

Description

一种中心布线双圈排列IC芯片堆叠封装件
技术领域
本实用新型涉及电子信息自动化元器件制造技术领域，尤其涉及一种中心布线双圈排列IC芯片堆叠封装件，本实用新型还包括该封装件的生产方法。
背景技术
长期以来，受蚀刻模板及蚀刻工艺技术的限制，QFN产品一直延续着90年代开发出来的单圈引线框架模式。QFN封装经过近几年的发展，特别是2006年以来，市场需求增加，推动了QFN封装技术的快速发展，材料配套技术、制造工艺技术和封装应用技术都有了突破性的进展，实现双圈QFN产品成为可能。QFN(Quad Flat No Lead Package) 型双圈排列封装的集成电路封装技术是近几年国外发展起来的一种新型微小形高密度封装技术，是最先进的表面贴装封装技术之一。目前，普通四边扁平无引脚封装（QFN）单面封装时引脚数少、焊线长、造成焊线成本高。
实用新型内容
本实用新型所要解决的技术问题是在已有的较为成熟的QFN集成电路封装技术和单圈扁平的无引脚封装技术的基础上，吸取BGA用中心布线环设计制作特点，提供一种把中心布线环和双圈排列凸点巧妙结合的中心布线双圈排列IC芯片堆叠封装件。
为解决上述技术问题采用如下技术方案：
一种中心布线双圈排列IC芯片堆叠封装件，包括引线框架载体、框架引线内引脚、IC芯片、键合线及塑封体，所述引线框架载体上粘接第一IC芯片，所述第一IC芯片上堆叠有第二IC芯片，所述第一IC芯片外侧设有中心布线环，所述中心布线环的外部设有两圈内引脚，分别为第一内引脚和第二内引脚，所述两圈内引脚之间正面腐蚀出深度为引线框架厚度的1/2的第一凹坑,第一内引脚和第二内引脚底部腐蚀出深度为引线框架厚度的1/2的第二凹坑，所述中心布线环上设有内圈焊盘和外圈焊盘两圈焊盘，所述内圈焊盘分别与第一IC芯片和第二IC芯片的焊盘打线，所述外圈焊盘分别与第一内引脚和第二内引脚打线。
所述第一IC芯片与第二IC芯片打线连接形成第五键合线，所述第一IC芯片与中心布线环的内圈焊盘打线连接形成第一键合线和第二键合线；所述第二IC芯片与中心布线环的内圈焊盘打线连接形成第六键合线和第七键合线；所述外圈焊盘打线后拉弧在第一内引脚上形成第三键合线和第八键合线，打线后拉弧在第二内引脚上形成第四键合线和第九键合线。
所述中心布线环镶嵌或粘贴在引线框架载体上，所述内圈焊盘和外圈焊盘之间通过中心布线环相通。
本实用新型的中心布线环通过高强度胶与引线框架载体相接或镶嵌，载体通过4个边筋分别与中筋和框架相连；同列内引脚通过连筋分别与中筋和相邻框架的引脚相连，通过中筋和边筋与框架相连；直线式第一内引脚和第二内引脚相连，并且第一内引脚和第二内引脚之间的上表面和底面都有凹坑，上表面凹坑（第一凹坑）减少了分离引脚厚度，底面凹坑（第二凹坑）塑封料嵌入，增强了塑封料与框架的结合，又减薄了框架厚度（框架厚度的1/2）方便引脚分离，防止分层有利于提高产品的可靠性。中心布线环上有2圈焊盘通过PCB设计线路相通，并作为IC芯片通过中心布线环内部线路的转换实现与内引脚间导通，减少焊线长度，节约焊线成本，主要是金线。
附图说明
图1为本实用新型框架局部图；
图2为本实用新型分离引脚前剖面图；
图3为本实用新型背面蚀刻减薄后剖面示意图；
图4为本实用新型磨削分离引脚后剖面图；
图5为本实用新型激光分离引脚后剖面图。
图中：1—引线框架载体 ；2—中心布线环； 3—第一粘片胶（导电胶）；4—第一IC芯片；5—第一键合线 ；6—第二键合线；7—第三键合线 ；8—第四键合线 ；9—第二粘片胶（绝缘胶）；10—第二IC芯片；11—第五键合线；12—第六键合线；13—第七键合线； 14—第八键合线；15—第九键合线；16—胶膜片；17—第一内引脚；18—第一凹坑；19—第二内引脚；20—塑封体；21—激光切口；22—内焊盘组；23—外焊盘组；24—连筋；25—中筋；26—高强度胶；27—第二凹坑；28—边筋。
具体实施方式
 下面结合附图对本实用新型做进一步的详细叙述：
 如图所示，一种中心布线双圈排列IC芯片堆叠封装件，包括引线框架载体1、框架引线内引脚、凹坑、中心布线环2及内、外焊盘组、IC芯片、键合线及塑封体20。IC芯片分为第一IC芯片4和第二IC芯片10，引线框架载体1上通过粘片胶3粘接有第一IC芯片4，第一IC芯片4上堆叠有第二IC芯片10。该引线框架的中心布线环2通过高强度胶26与引线框架载体1相接或镶嵌，引线框架载体1通过4个边筋28分别与中筋25和框架相连；同列内引脚通过连筋分别与中筋和相邻框架的引脚相连，通过中筋和边筋与框架相连。第一IC芯片4外侧设有中心布线环2，中心布线环2的外部设有两圈内引脚，第一内引脚17和第二内引脚19，两圈内引脚之间正面腐蚀出深度为引线框架厚度的1/2的第一凹坑18，减少了分离引脚厚度。第一内引脚17和第二内引脚19底面腐蚀出深度为引线框架厚度的1/2的第二凹坑27，第二凹坑27塑封料嵌入，增强了塑封料与框架的结合，又减薄了框架厚度（框架厚度的1/2）方便引脚分离，防止分层有利于提高产品的可靠性。所述中心布线环2上设有内圈焊盘22和外圈焊盘23两圈焊盘，内圈焊盘22分别与第一IC芯片4和第二IC芯片10的焊盘打线，外圈焊盘23分别与第一内引脚17和第二内引脚19打线。中心布线环上2圈焊盘通过PCB设计线路相通，并作为IC芯片通过中心布线环2内部线路的转换实现与内引脚间导通，减少焊线长度，节约焊线成本，主要是金线。第一IC芯片4与第二IC芯片10打线连接形成第五键合线11，第一IC芯片4与中心布线环2的内圈焊盘22打线连接形成第一键合线5和第二键合线6；所述第二IC芯片10与中心布线环2的内圈焊盘22打线连接形成第六键合线12和第七键合线13；所述外圈焊盘23打线后拉弧在第一内引脚17上形成第三键合线7和第八键合线14，外圈焊盘23打线后拉弧在第二内引脚19上形成第四键合线8和第九键合线15。
     虽然结合优选实施例已经示出并描述了本实用新型，本领域技术人员可以人理解，在不违背所附权利要求限定的本实用新型的精神和范围的前提下可以进行修改和变换。

Claims (3)

1.一种中心布线双圈排列IC芯片堆叠封装件，包括引线框架载体、框架引线内引脚、IC芯片、键合线及塑封体，其特征在于：所述引线框架载体（1）上粘接第一IC芯片（4），所述第一IC芯片（4）上堆叠有第二IC芯片（10），所述第一IC芯片（4）外侧设有中心布线环（2），所述中心布线环（2）的外部设有两圈内引脚，分别为第一内引脚（17）和第二内引脚（19），所述两圈内引脚之间正面腐蚀出深度为引线框架厚度的1/2的第一凹坑（18）,第一内引脚（17）和第二内引脚（19）底部腐蚀出深度为引线框架厚度的1/2的第二凹坑（27），所述中心布线环（2）上设有内圈焊盘（22）和外圈焊盘（23）两圈焊盘，所述内圈焊盘（22）分别与第一IC芯片（4）和第二IC芯片（10）的焊盘打线，所述外圈焊盘（23）分别与第一内引脚（17）和第二内引脚（19）打线。
2.根据权利要求1所述的一种中心布线双圈排列IC芯片堆叠封装件，其特征在于：所述第一IC芯片（4）与第二IC芯片（10）打线连接形成第五键合线（11），所述第一IC芯片（4）与中心布线环（2）的内圈焊盘（22）打线连接形成第一键合线（5）和第二键合线（6）；所述第二IC芯片（10）与中心布线环（2）的内圈焊盘（22）打线连接形成第六键合线（12）和第七键合线（13）；所述外圈焊盘（23）打线后拉弧在第一内引脚（17）上形成第三键合线（7）和第八键合线（14），打线后拉弧在第二内引脚（19）上形成第四键合线（8）和第九键合线（15）。
3.根据权利要求1或2所述的一种中心布线双圈排列IC芯片堆叠封装件，其特征在于：所述中心布线环（2）镶嵌或粘贴在引线框架载体（1）上，所述内圈焊盘（22）和外圈焊盘（23）之间通过中心布线环（2）相通。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102522383A (zh) * 2011-12-31 2012-06-27 天水华天科技股份有限公司 一种中心布线双圈排列ic芯片堆叠封装件及其生产方法
US10381281B2 (en) * 2016-01-22 2019-08-13 Kyocera Corporation Electronic component housing package, multi-piece wiring substrate, electronic apparatus, and electronic module having curved connection conductors

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102522383A (zh) * 2011-12-31 2012-06-27 天水华天科技股份有限公司 一种中心布线双圈排列ic芯片堆叠封装件及其生产方法
CN102522383B (zh) * 2011-12-31 2015-08-12 天水华天科技股份有限公司 一种中心布线双圈排列ic芯片堆叠封装件及其生产方法
US10381281B2 (en) * 2016-01-22 2019-08-13 Kyocera Corporation Electronic component housing package, multi-piece wiring substrate, electronic apparatus, and electronic module having curved connection conductors
US10832980B2 (en) 2016-01-22 2020-11-10 Kyocera Corporation Electronic component housing package, multi-piece wiring substrate, electronic apparatus, and electronic module

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