CN202364238U

CN202364238U - CSDB (commercial standard digital bus) decoding circuit

Info

Publication number: CN202364238U
Application number: CN 201120523151
Authority: CN
Inventors: 田军; 车飞峰
Original assignee: Shaanxi Qianshan Avionics Co Ltd
Current assignee: Shaanxi Qianshan Avionics Co Ltd
Priority date: 2011-12-14
Filing date: 2011-12-14
Publication date: 2012-08-01
Anticipated expiration: 2021-12-14

Abstract

The utility model relates to a CSDB (commercial standard digital bus) decoding circuit, belonging to the technical field of aviation electronics. The CSDB decoding circuit consists of an RS422A interface chip (1) and an FPGA (field programmable gate array) chip (2). The input end of the RS422A interface chip (1) is connected with a signal input device and the output end of the RS422A interface chip (1) is connected on the FPGA chip (2); the FPGA chip (2) consists of a 422 decoding module (21), a CSDB protocol processing module (22), a control register (23), a state register (24) and a data register (25). According to the utility model, the CSDB protocol decoding is realized by utilizing an RS422A driving chip and the FPGA chip, so that the load of the processor can be effectively reduced; and when the multi-channel CSDB is in use, a multi-channel decoding circuit can be integrated by utilizing the FPGA, so that the volume of the product is greatly reduced.

Description

A kind of CSDB bus encoding/decoding circuit

Technical field

The utility model belongs to the avionics class, relates to a kind of CSDB bus encoding/decoding circuit.

Background technology

CSDB (Commercial Standard Digital Bus) bus is a kind of air equipment interconnection.This bus standard is formulated by Collins company, is mainly used in the interconnected of the said firm's product.This bus electric interfaces adopts the RS422A standard, and data format is self-defined.Because the non-world of this standard or national standard; Therefore exist when interconnected at the airborne equipment of the product of design and Collins company; Do not have corresponding bus encoding/decoding chip to use, therefore need the decoding circuit of a kind of CSDB bus of design, accomplish the processing of CSDB agreement.

Summary of the invention

The utility model technical problem to be solved is: the CSDB bus standard that is directed against (the non-world or national standard), a kind of decoding circuit of CSDB bus is provided, and be used to accomplish the processing of CSDB agreement.

The technical scheme of the utility model: use FPGA to realize CSDB protocol-decoding method, adopt the mode of " RS422A chip for driving+FPGA " to realize CSDB bus encoding/decoding circuit.Wherein the RS422A chip for driving realizes the conversion of level, and FPGA realizes the CSDB protocol processes.Be specially: a kind of CSDB bus encoding/decoding circuit, form by RS422A interface chip 1 and fpga chip 2;

Said RS422A interface chip 1 input is connected with signal input device, and output is connected on the FPGA2;

Said fpga chip 2 is made up of 422 decoder modules 21, CSDB bus protocol processing module 22, control register 23, status register 24 and data register 25; Said CSDB bus protocol processing module 22 comprises synchronous identification module 221, Address Recognition module 222, data counts module 223; Said control register 23 comprises that rate controlled register 231, channel status are provided with that register 232, verification mode are provided with register 233, the information block length is provided with register 234, block of information address setting register 235;

Said 422 decoder modules 21 are used for serial data is decoded into data cell, and said CSDB bus protocol processing module 22 is used for the processing of CSDB bus protocol; Said control register 23 is used to control the decoding process of 422 decoder modules 21 and the processing mode of CSDB bus protocol processing module 22; Said status register 24 is used to export the state information of 422 decoder modules 21, CSDB bus protocol processing module 22; Said data register 25 is used to deposit the result of CSDB bus protocol processing module 22;

Said rate controlled register 231, channel status are provided with register 232, verification mode is provided with register 233 and is connected with 422 decoder modules 21 respectively; Said information block length is provided with register 234, the fast address setting register 235 of information and data register 25 and is connected with CSDB bus protocol processing module 22 respectively, and said CSDB bus protocol processing module 22 also is connected with 422 decoder modules 21;

All registers all are connected with ppu through parallel bus 3.

The beneficial effect of the utility model: the utility model adopts " RS422A chip for driving+FPGA " to realize the CSDB protocol-decoding; Can alleviate the burden of processor effectively; When multichannel CSDB bus is used; Use the FPGA can integrated multichannel decoding circuit, significantly reduce the volume of product.

Description of drawings

Fig. 1 is the utility model schematic block circuit diagram.

Fig. 2 is the workflow diagram of the utility model FPGA implementation part.

Wherein, 1-RS422A interface chip, 2-FPGA chip, 21-422 decoder module; 22-CSDB bus protocol processing module, the synchronous identification module of 221-, 222-Address Recognition module, 223-data counts module, 23-control register, 231-rate controlled register; The 232-channel status is provided with register, and the 233-verification mode is provided with register, and 234-information block length is provided with register, 235-block of information address setting register; The 24-status register, 25-data register, 3-parallel bus.

SpecificallyExecution mode

Through embodiment the utility model is done further to specify below:

Decoding circuit is made up of FPGA and RS422A chip for driving, selects the RS422A chip for driving according to CSDB bus baud rate.

As shown in Figure 1, a kind of CSDB bus encoding/decoding circuit is made up of RS422A interface chip 1 and fpga chip 2;

Said fpga chip 2 comprises that 422 decoder modules 21, CSDB bus protocol processing module 22, control register 23, status register 24 and data register 25 form, and said control register 23 comprises that rate controlled register 231, channel status are provided with that register 232, verification mode are provided with register 233, the information block length is provided with register 234, block of information address setting register 235;

All registers all are connected with ppu through parallel bus 3.

Through embodiment the utility model is done further to specify below, coding/decoding method is pressed Fig. 2 and is described, and in FPGA, adopts hardware description language to realize:

Realize that in FPGA 422 decoder modules, 21,422 decoder modules 21 possess baud rate setting, verification mode setting, the long-time free of data judgement of bus setting, (sequence number a) is exported a state pulse (sequence number b) synchronously in correct decoded data output;

In FPGA, realize synchronous identification module 221, after the positive pulse that detects sequence number 4, obtain data synchronously, whether judgment data is 0xA5, if then counter adds up, otherwise zero clearing.N (information block length register is provided with 234) is individual when above when receiving continuously, output synchronous reset pulse (sequence number c is reset to low level, otherwise is high level);

When sequence number c is low level; Close Address Recognition module 222 and data counts module 223; Sequence number c is after high level or a block of information reception finish; First data of receiving after at first being resetted by 222 pairs of Address Recognition modules are carried out Address Recognition, confirm the first address that the current information blocks of data is deposited according to the address that is provided with in the block address district among Fig. 1, and output block receives beginning pulse (sequence number d) simultaneously;

Data counts module 223 is according to the data block length n that is provided with; After receiving sequence number d pulse at every turn; The data of step 1 output are got n byte continuously be stored in the data field shown in Figure 1, sequence number e is the data of output, and sequence number f is a write pulse; After accomplishing the reception and storage of a block of information, wait for next block of information acceptance beginning pulse.

The module that constitutes is provided in the CSDB decoding, through parallel bus and outside processor interface.

Claims

1. a CSDB bus encoding/decoding circuit is characterized in that, is made up of RS422A interface chip [1] and fpga chip [2];

Said RS422A interface chip [1] input is connected with signal input device, and output is connected on the FPGA [2];

Said fpga chip [2] is made up of 422 decoder modules [21], CSDB bus protocol processing module [22], control register [23], status register [24] and data register [25];

Said CSDB bus protocol processing module [22] comprises synchronous identification module [221], Address Recognition module [222], data counts module [223]; Said control register [23] comprises that rate controlled register [231], channel status are provided with that register [232], verification mode are provided with register [233], the information block length is provided with register [234], block of information address setting register [235];

Said 422 decoder modules [21] are used for serial data is decoded into data cell, and said CSDB bus protocol processing module [22] is used for the processing of CSDB bus protocol; Said control register [23] is used to control the decoding process of 422 decoder modules [21] and the processing mode of CSDB bus protocol processing module [22]; Said status register [24] is used to export the state information of 422 decoder modules [21], CSDB bus protocol processing module [22]; Said data register [25] is used to deposit the result of CSDB bus protocol processing module [22];

Said rate controlled register [231], channel status are provided with register [232], verification mode is provided with register [233] and is connected with 422 decoder modules [21] respectively; Said information block length is provided with register [234], the fast address setting register of information [235] and data register [25] and is connected with CSDB bus protocol processing module [22] respectively, and said CSDB bus protocol processing module [22] also is connected with 422 decoder modules [21];

All registers all are connected with ppu through parallel bus [3].