CN104469375A - FC-AV protocol processing circuit structure - Google Patents
FC-AV protocol processing circuit structure Download PDFInfo
- Publication number
- CN104469375A CN104469375A CN201410752867.2A CN201410752867A CN104469375A CN 104469375 A CN104469375 A CN 104469375A CN 201410752867 A CN201410752867 A CN 201410752867A CN 104469375 A CN104469375 A CN 104469375A
- Authority
- CN
- China
- Prior art keywords
- asynchronous fifo
- core
- module
- ddr2
- control module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Communication Control (AREA)
Abstract
The invention provides an FC-AV protocol processing circuit structure. The structure comprises a DDR2 read control module, asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C, asynchronous FIFO D, a sending control module 0, a sending control model 1, a receiving control module, an FC core 0 and an FC core 1, wherein the FC core 0, the DDR2 read control module, the asynchronous FIFO A , the asynchronous FIFO B and the sending control module 0 form a sending passage 0, the FC core 1, the DDR2 read control module, the asynchronous FIFO C, the asynchronous FIFO D and the sending control module 1 form a sending passage 1, the FC core 0 and the receiving control module form a receiving passage 0, the FC core 1 and the receiving control module form a receiving passage 1, the sensing passage 0 and the sending passage 1 achieve the dual-redundancy sending function, and the receiving passage 0 and the receiving passage 1 achieve the dual-redundancy receiving function. According to the FC-AV protocol processing circuit structure, an FC-AV protocol circuit is obtained, and the dual-redundancy sending function and the dual-redundancy receiving function are achieved at the same time.
Description
Technical field
The invention belongs to computer hardware technology, relate to a kind of FC-AV protocol treatment circuit structure.
Background technology
The FC-AV protocol definition mapping way of audio, video data to FC (optical-fibre channel), the audio frequency and video meeting VESA standard be mapped to FC network and export from FC network restore audio, video data, but not yet realizing the circuit of this protocol processes in prior art.
Summary of the invention
The invention provides a kind of circuit structure realizing FC-AV agreement.
Technical solution of the present invention:
A kind of FC-AV protocol treatment circuit, comprises DDR2 read control module, asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C, asynchronous FIFO D, sends control 0 module, sends control 1 module, receives control module, FC core 0 and FC core 1, DDR2 read control module input connects outside transmission DDR2 memory through sending DDR2 controller, DDR2 read control module output and asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C is connected with asynchronous FIFO D input, asynchronous FIFO A is connected with transmission control 0 module input with asynchronous FIFO B output, asynchronous FIFO C is connected with the input sending control 1 module with asynchronous FIFO D output, the output sending control 0 module and transmission control 1 module is connected with the input of the transmission path of FC core 0 and FC core 1 respectively, the output receiving input and the FC core 0 of control module and the receiving path of FC core 1 is connected, the output receiving control module connects external reception DDR2 memory through receiving DDR2 controller.
Above-mentioned FC core 0 forms transmission path 0 together with DDR2 read control module, asynchronous FIFO A, asynchronous FIFO B, transmission control 0 module; Described FC core 1 forms transmission path 1 together with DDR2 read control module, asynchronous FIFO C, asynchronous FIFO D, transmission control 1 module; FC core 0 and reception control module composition receiving path 0; FC core 1 and reception control module composition receiving path 1; Transmission path 0 realizes sending two remaining function together with transmission path 1; Receiving path 0 realizes receiving two remaining function together with receiving path 1.
Above-mentioned DDR2 read control module judges there is a line video data in transmission DDR2 memory by sending DDR2 memory write pointer signal, judge that asynchronous FIFO A and asynchronous FIFO C is as empty by the spacing wave of asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C and asynchronous FIFO D simultaneously, or when asynchronous FIFO B and asynchronous FIFO D is empty, video data reads from transmission DDR2 memory by sending DDR2 controller by DDR2 read control module by row, and write FIFO A and asynchronous FIFO C, or write asynchronous FIFO B and asynchronous FIFO D simultaneously simultaneously.
Above-mentioned asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C and asynchronous FIFO D are that structure is identical, for separating the data buffer of clock zone by video line buffered video valid data, each FIFO size is the degree of depth 1024, width 64bit, buffer memory a line video effective data.
It is identical with transmission control 1 inside modules circuit that above-mentioned transmission controls 0 module, realizes together sending two remaining function; Send control 0 module the video data of higher level's asynchronous FIFO A and asynchronous FIFO B is alternately read and by FC-AV agreement composition FC-AV frame, is sent to FC core 0; During enable transmission remaining function, send control 1 module and the video data of higher level's asynchronous FIFO C and asynchronous FIFO D is alternately read and by FC-AV agreement composition FC-AV frame, is sent to FC core 1, otherwise transmission control 1 module does not work.
The pay(useful) load of the FC-AV frame from FC core 0 or FC core 1 extracts and passes through to receive the frame buffer zone that the write of DDR2 controller receives DDR2 memory by above-mentioned reception control module; During not enable reception remaining function, reception control module receives only the FC-AV frame from FC core 0, during enable reception remaining function, receives control module and between FC core 0 and FC core 1, switches reception FC-AV frame according to handover mechanism.
Above-mentioned FC core 0 is identical with FC core 1 internal circuit, realizes FC frame and sends and receive; During transmission, convert FC frame to high-speed serial data and be sent to FC network; During reception, change the converting high-speed serial on FC network into FC frame; Serial rate is 2Gbps.
DDR2 read control module is positioned at DDR2 clock zone, and transmission control 0 module, transmission control 1 module, reception control module, FC core 0 and FC core 1 are positioned at FC clock zone.
Transmission path and receiving path separate, be independent of each other, can work simultaneously, also can work independently.
Advantage of the present invention is:
A kind of FC-AV protocol treatment circuit structure provided by the invention by DDR2 read control module, asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C, asynchronous FIFO D, send control 0 module, send control 1 module, receive control module, FC core 0 and FC core 1 and achieve video data to the mapping of FC and FC to the conversion of video data, have simultaneously and send two remaining and receive two remaining function, whole circuit realiration FC-AV agreement circuit, the good stability of whole circuit, reliability is high, has milestone significance.
Accompanying drawing illustrates:
Fig. 1 is FC-AV protocol treatment circuit structure chart.
Embodiment
Below in conjunction with drawings and Examples, the present invention will be further described:
Refer to Fig. 1, FC-AV protocol treatment circuit structure of the present invention comprises DDR2 read control module, asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C, asynchronous FIFO D, sends control 0 module, sends control 1 module, receives control module, FC core 0 and FC core 1, DDR2 read control module input connects outside transmission DDR2 memory through sending DDR2 controller, DDR2 read control module output and asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C is connected with asynchronous FIFO D input, asynchronous FIFO A is connected with transmission control 0 module input with asynchronous FIFO B output, asynchronous FIFO C is connected with the input sending control 1 module with asynchronous FIFO D output, the output sending control 0 module and transmission control 1 module is connected with the input of the transmission path of FC core 0 and FC core 1 respectively, the output receiving input and the FC core 0 of control module and the receiving path of FC core 1 is connected, the output receiving control module connects external reception DDR2 memory through receiving DDR2 controller.
FC core 0 forms transmission path 0 together with DDR2 read control module, asynchronous FIFO A, asynchronous FIFO B, transmission control 0 module; Described FC core 1 forms transmission path 1 together with DDR2 read control module, asynchronous FIFO C, asynchronous FIFO D, transmission control 1 module; FC core 0 and reception control module composition receiving path 0; FC core 1 and reception control module composition receiving path 1; Transmission path 0 realizes sending two remaining function together with transmission path 1; Receiving path 0 realizes receiving two remaining function together with receiving path 1.During enable transmission remaining function, transmission path 0 and transmission path 1 work simultaneously, and during not enable transmission remaining function, only have transmission path 0 to work, transmission path 1 does not work; During not enable reception remaining function, receiving path 0 works, during enable reception remaining function, and receiving path 0 and receiving path 1 switch operating.
DDR2 read control module judges there is a line video data in transmission DDR2 memory by sending DDR2 memory write pointer signal, simultaneously, when not enable transmission remaining function, judge that asynchronous FIFO A or asynchronous FIFO B is as time empty by the spacing wave of asynchronous FIFO A and asynchronous FIFO B, video data reads from transmission DDR2 memory by sending DDR2 controller by DDR2 read control module by row, and alternately writes asynchronous FIFO A and asynchronous FIFO B; When enable transmission remaining function, by the spacing wave of asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C and asynchronous FIFO D judge asynchronous FIFO A and asynchronous FIFO C be all sky or asynchronous FIFO B and asynchronous FIFO D be all sky time, video data reads from transmission DDR2 memory by sending DDR2 controller by DDR2 read control module by row, and alternately writes FIFOA, asynchronous FIFO C and write asynchronous FIFO B, asynchronous FIFO D.
Asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C and asynchronous FIFO D are used for replacing buffered video valid data by video line, and each FIFO can buffer memory a line video effective data, have isolation clock zone function simultaneously.FIFO writes clock and DDR2 read control module clock belongs to DDR2 clock zone together.FIFO read clock and send control 0 module, send control 1 module, receive control module, FC core 0 and FC core 1 clock belong to FC clock zone together.FIFO size is the degree of depth 1024, width 64bit.During not enable transmission remaining function, asynchronous FIFO C and asynchronous FIFO D is in reset mode.During enable transmission remaining function, asynchronous FIFO A, asynchronous FIFO B alternately receive a line video data from DDR2 read control module, and Alternating Transportation gives transmission control 0 module; Asynchronous FIFO C, asynchronous FIFO D alternately receive a line video data from DDR2 read control module, and Alternating Transportation gives transmission control 1 module.
Send control 0 module identical with transmission control 1 inside modules circuit, realize together sending two remaining function; Send control 0 module the video data of higher level's asynchronous FIFO A and asynchronous FIFO B is alternately read and by FC-AV agreement composition FC-AV frame, is sent to FC core 0; During enable transmission remaining function, send control 1 module and the video data of higher level's asynchronous FIFO C and asynchronous FIFO D is alternately read and by FC-AV agreement composition FC-AV frame, is sent to FC core 1, otherwise transmission control 1 module does not work.Send control module judges video data line number by first double word of every row video data, when data are the first row, sending control module first organizes a frame to send to FC core according to FC-AV agreement, when data are not the first rows, sending control module is divided into 2 frame FC-AV frames to send to FC core little definition video data according to the resolution of video data, is divided into by large definition video data 4 frame FC-AV frames to send to FC core.
Receive control module the pay(useful) load of the FC-AV frame from FC core 0 or FC core 1 is extracted and passes through to receive the frame buffer zone that the write of DDR2 controller receives DDR2 memory.During not enable reception remaining function, reception control module receives only the FC-AV frame from FC core 0; During enable reception remaining function, receive control module and between FC core 0 and FC core 1, switch reception FC-AV frame according to handover mechanism, during electrification reset, acquiescence receives the FC-AV frame of FC core 0, when FC core 0 rolls off the production line and FC core 1 is reached the standard grade, or FC core 0 does not all have FC-AV frame in official hour, and FC core 1 has FC-AV frame, then be switched on FC core 1 and receive FC-AV frame, vice versa.
FC core 0 is identical with FC core 1 internal circuit, realizes FC frame and sends and receive; During transmission, convert FC frame to high-speed serial data and be sent to FC network; During reception, change the converting high-speed serial on FC network into FC frame; Wire rate is 2Gbps.Adopt analog circuit to realize high speed serial parallel exchange circuit, adopt digital circuit FC agreement and other functions; Simulation and numerical portion interface adopt self defined interface.
Transmission path and receiving path separate, be independent of each other, can work simultaneously, also can work independently.
A kind of FC-AV protocol treatment circuit structure provided by the invention by DDR2 read control module, asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C, asynchronous FIFO D, send control 0 module, send control 1 module, receive control module, FC core 0 and FC core 1 and achieve video data to the mapping of FC and FC to the conversion of video data, have simultaneously and send two remaining and receive two remaining function, whole circuit realiration FC-AV agreement circuit, break external monopolization, there is milestone significance.
Last it is noted that above embodiment is only in order to illustrate technical scheme of the present invention, be not intended to limit; Although explain invention has been with reference to previous embodiment, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein portion of techniques feature; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (9)
1. a FC-AV protocol treatment circuit, it is characterized in that, comprise DDR2 read control module, asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C, asynchronous FIFO D, send control 0 module, send control 1 module, receive control module, FC core 0 and FC core 1, DDR2 read control module input connects outside transmission DDR2 memory through sending DDR2 controller, DDR2 read control module output and asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C is connected with asynchronous FIFO D input, asynchronous FIFO A is connected with transmission control 0 module input with asynchronous FIFO B output, asynchronous FIFO C is connected with the input sending control 1 module with asynchronous FIFO D output, the output sending control 0 module and transmission control 1 module is connected with the input of the transmission path of FC core 0 and FC core 1 respectively, the output receiving input and the FC core 0 of control module and the receiving path of FC core 1 is connected, the output receiving control module connects external reception DDR2 memory through receiving DDR2 controller.
2. FC-AV protocol treatment circuit according to claim 1, is characterized in that, described FC core 0 forms transmission path 0 together with DDR2 read control module, asynchronous FIFO A, asynchronous FIFO B, transmission control 0 module; Described FC core 1 forms transmission path 1 together with DDR2 read control module, asynchronous FIFO C, asynchronous FIFO D, transmission control 1 module; FC core 0 and reception control module composition receiving path 0; FC core 1 and reception control module composition receiving path 1; Transmission path 0 realizes sending two remaining function together with transmission path 1; Receiving path 0 realizes receiving two remaining function together with receiving path 1.
3. FC-AV protocol treatment circuit according to claim 1 and 2, it is characterized in that, described DDR2 read control module judges there is a line video data in transmission DDR2 memory by sending DDR2 memory write pointer signal, simultaneously by asynchronous FIFO A, asynchronous FIFO B, the spacing wave of asynchronous FIFO C and asynchronous FIFO D judges that asynchronous FIFO A and asynchronous FIFO C is as empty, or when asynchronous FIFO B and asynchronous FIFO D is empty, video data reads from transmission DDR2 memory by sending DDR2 controller by DDR2 read control module by row, and write FIFO A and asynchronous FIFO C simultaneously, or write asynchronous FIFO B and asynchronous FIFO D simultaneously.
4. FC-AV protocol treatment circuit according to claim 3, it is characterized in that, described asynchronous FIFO A, asynchronous FIFO B, asynchronous FIFO C and asynchronous FIFO D are that structure is identical, for separating the data buffer of clock zone by video line buffered video valid data, each FIFO size is the degree of depth 1024, width 64bit, buffer memory a line video effective data.
5. FC-AV protocol treatment circuit according to claim 4, is characterized in that, described transmission control 0 module is identical with transmission control 1 inside modules circuit, realizes together sending two remaining function; Send control 0 module the video data of higher level's asynchronous FIFO A and asynchronous FIFO B is alternately read and by FC-AV agreement composition FC-AV frame, is sent to FC core 0; During enable transmission remaining function, send control 1 module and the video data of higher level's asynchronous FIFO C and asynchronous FIFO D is alternately read and by FC-AV agreement composition FC-AV frame, is sent to FC core 1, otherwise transmission control 1 module does not work.
6. FC-AV protocol treatment circuit according to claim 5, it is characterized in that, the pay(useful) load of the FC-AV frame from FC core 0 or FC core 1 extracts and passes through to receive the frame buffer zone that the write of DDR2 controller receives DDR2 memory by described reception control module; During not enable reception remaining function, reception control module receives only the FC-AV frame from FC core 0, during enable reception remaining function, receives control module and between FC core 0 and FC core 1, switches reception FC-AV frame according to handover mechanism.
7. FC-AV protocol treatment circuit according to claim 6, is characterized in that, described FC core 0 is identical with FC core 1 internal circuit, realizes FC frame and sends and receive; During transmission, convert FC frame to high-speed serial data and be sent to FC network; During reception, change the converting high-speed serial on FC network into FC frame; Serial rate is 2Gbps.
8. FC-AV protocol treatment circuit according to claim 7, is characterized in that: DDR2 read control module is positioned at DDR2 clock zone, and transmission control 0 module, transmission control 1 module, reception control module, FC core 0 and FC core 1 are positioned at FC clock zone.
9. FC-AV protocol treatment circuit according to claim 8, is characterized in that: described transmission path and receiving path separate, be independent of each other, can work simultaneously, also can work independently.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410752867.2A CN104469375A (en) | 2014-12-09 | 2014-12-09 | FC-AV protocol processing circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410752867.2A CN104469375A (en) | 2014-12-09 | 2014-12-09 | FC-AV protocol processing circuit structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104469375A true CN104469375A (en) | 2015-03-25 |
Family
ID=52914644
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410752867.2A Pending CN104469375A (en) | 2014-12-09 | 2014-12-09 | FC-AV protocol processing circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104469375A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105553765A (en) * | 2015-12-11 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | FC-AV protocol processing chip network communication robustness testing method |
| CN108307129A (en) * | 2017-12-12 | 2018-07-20 | 天津津航计算技术研究所 | A kind of multi-channel optical fibre video switching system based on FC-AV agreements |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070150683A1 (en) * | 2005-12-28 | 2007-06-28 | Intel Corporation | Dynamic memory buffer allocation method and system |
| CN202453864U (en) * | 2011-12-20 | 2012-09-26 | 四川九洲电器集团有限责任公司 | Large-capacity asynchronous first in first out (FIFO) buffer memory based on field programmable gate array (FPGA) and double data rate (DDR) 2 synchronous dynamic random access memory (SDRAM) |
| CN103136163A (en) * | 2011-11-29 | 2013-06-05 | 中国航空工业集团公司第六三一研究所 | Protocol processor chip capable of allocating and achieving FC-AE-ASM and FC-AV protocol |
-
2014
- 2014-12-09 CN CN201410752867.2A patent/CN104469375A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070150683A1 (en) * | 2005-12-28 | 2007-06-28 | Intel Corporation | Dynamic memory buffer allocation method and system |
| CN103136163A (en) * | 2011-11-29 | 2013-06-05 | 中国航空工业集团公司第六三一研究所 | Protocol processor chip capable of allocating and achieving FC-AE-ASM and FC-AV protocol |
| CN202453864U (en) * | 2011-12-20 | 2012-09-26 | 四川九洲电器集团有限责任公司 | Large-capacity asynchronous first in first out (FIFO) buffer memory based on field programmable gate array (FPGA) and double data rate (DDR) 2 synchronous dynamic random access memory (SDRAM) |
Non-Patent Citations (2)
| Title |
|---|
| 刘浩等: "FC－AV 协议及实现方法研究", 《计算机技术与发展》 * |
| 王红春: "基于FC的航电数字视频传输技术研究", 《计算机技术与发展》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105553765A (en) * | 2015-12-11 | 2016-05-04 | 中国航空工业集团公司西安航空计算技术研究所 | FC-AV protocol processing chip network communication robustness testing method |
| CN108307129A (en) * | 2017-12-12 | 2018-07-20 | 天津津航计算技术研究所 | A kind of multi-channel optical fibre video switching system based on FC-AV agreements |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104954096B (en) | A kind of high-speed synchronous serial communication data transmission method of one master and multiple slaves | |
| CN104980679B (en) | MIPI DSI/CSI-2 receiver systems based on pure differential signal | |
| CN205726099U (en) | The video matrix system that a kind of multi-format video signal is switched fast | |
| CN102591291B (en) | Industrial controller and human-machine interface bidirectional data transmission system and method | |
| CN103825696A (en) | Device for realizing high-speed real-time communication by optical fibers based on FPGA (Field Programmable Gate Array) | |
| CN105208034A (en) | SPI bus and CAN bus protocol converting circuit and method | |
| CN103065587B (en) | A kind of LED synchronous display controlling system without sending card | |
| CN104991880B (en) | A kind of FC AE ASM Communication Cards based on PCI E interfaces | |
| TW201839763A (en) | Managing parallel access to a plurality of flash memories | |
| CN206272746U (en) | A kind of digital video display interface module based on FPGA | |
| CN105446699A (en) | Data frame queue management method | |
| CN104469375A (en) | FC-AV protocol processing circuit structure | |
| CN105279123A (en) | Serial port conversion structure and method of dual-redundancy 1553B bus | |
| CN203708370U (en) | Multipath digital image processing system | |
| CN103412847B (en) | USB based on FPGA turns multichannel link interface circuit | |
| CN102158400B (en) | Communication interface of space-based route switching system and space-based route switching system | |
| CN104113933A (en) | Information transmission method and device and mobile terminal | |
| CN203217927U (en) | Low cost LED synchronous display control system without sending card | |
| CN103813125A (en) | Multi-branch digital image processing system | |
| CN104469405A (en) | FC-AV communication control method | |
| CN103347023B (en) | A kind of HDLC communication controller under industrial field environment | |
| CN202617284U (en) | VGA encoder for long-distance transmission | |
| CN106791550A (en) | The apparatus and method that a kind of low frame rate LVDS turns frame frequency DVI videos high | |
| CN101741727B (en) | Method for processing data via triple-buffering | |
| CN103888211A (en) | Method and device for data transmission between crossed chips |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150325 |