CN203984813U - A kind of ECT/EVT merge cells interface cabinet - Google Patents

Abstract

The utility model relates to a kind of ECT/EVT merge cells interface cabinet, belongs to electrical equipment technical field.This ECT/EVT merge cells interface is placed in cabinet with the interface of cabinet, cabinet is assembled by panel, cuboid support frame, upper and lower cover plates, left and right cover plate and back shroud, cabinet inside is embedded with guide rail and the electromagnetic shielding plate of plug optical fiber interface plate, it is characterized in that: in upper and lower cover plates, have mesh, and side embeds Air Filter therein, resistance screen touch-control display panel, communication serial ports and LED relay indicating light are installed on panel, on touch-control display panel, are connected with fpga chip.This ECT/EVT merge cells interface has good interference free performance with cabinet, and simple and easy interactive mode, saves many unnecessary peripheral hardwares.

Description

A kind of ECT/EVT merge cells interface cabinet

Technical field

The utility model relates to a kind of ECT/EVT merge cells interface cabinet, belongs to field of electrical equipment.

Background technology

As shown in Figure 1; being defined in IEC60044-7/8 of merge cells provides first; it is electronic current/voltage transformer (ECT/EVT) for Digital output and the new ideas introduced, and its major function is that the form specifying according to standard after the digital signal of synchronous acquisition multichannel ECT/EVT output sends to protection, measuring and controlling equipment.

Merge cells generally comprises synchronizing function module, Multichannel data acquisition module and serial ports sending function module.Synchronizing function module is after the synchronous pulse per second (PPS) clock signal (being generally the signal of GPS receiver output) of the outside input of correct identification, and merge cells Gei Ge road A/D converter sends synchronous switching signal.Multi-channel data acquisition and processing capacity module: be the main functional modules of carrying out interface with electronic mutual inductor; Send to multi-channel a/d converter at merge cells after synchronous switching signal, will receive the data of all passages simultaneously and it be carried out to verification; In addition, merge cells also needs these data correctly sort and export to serial ports sending function module.Serial port function sending module: carry out framing and send to protection measuring and controlling equipment for Jiang Ge road sampled value data.

Utility model content

The technical problems to be solved in the utility model is, for prior art deficiency, propose one and meet the requirement of modern electric automatic field with high integration degree, and there is good anti-interference with respect to other devices, the more affine ECT/EVT easily of human-computer interaction interface merge cells interface cabinet.

The utility model is that the technical scheme that solves the problems of the technologies described above proposition is: a kind of ECT/EVT merge cells interface cabinet, described interface is placed in cabinet, described cabinet is by panel, cuboid support frame, upper and lower cover plates, left and right cover plate and back shroud are assembled, cabinet inside is embedded with guide rail and the electromagnetic shielding plate of plug optical fiber interface plate, in described upper and lower cover plates, have mesh and the Air Filter of side embedding therein, resistance screen touch-control display panel is installed on described panel, communication serial ports and LED relay indicating light, on described resistance screen touch-control display panel, be connected with fpga chip.

The improvement of technical solutions of the utility model is: described fpga chip adopts the ACEX1K family chip with embedded Array.

The improvement of technical solutions of the utility model is: described panel, upper and lower cover plates, left and right cover plate, back shroud and cuboid support frame are panel, upper and lower cover plates, left and right cover plate, back shroud and the cuboid support frame that aluminum alloy materials is made.

The utility model adopts the beneficial effect of technique scheme to be: the casing that metal forms and inner electromagnetic shielding plate, realize inner good electrical magnetic screen simultaneously, outside also has good capability of electromagnetic shielding with respect to during other, and low-power consumption, reliability are high, more convenient operation, save unnecessary peripheral hardware as keyboard, mouse, writing pen and handwriting pad etc., convenience that human-computer interaction interface is more affine

Brief description of the drawings

Below in conjunction with accompanying drawing, the utility model is described in further detail:

Fig. 1 is the merge cells of existing IEC60044-7/8 definition.

Fig. 2 is the structural representation of the utility model embodiment cabinet.

Fig. 3 is initial time principle schematic.

Fig. 4 is the principle schematic of data reception module.

Fig. 5 is the circuit diagram of realizing function in Fig. 4.

Fig. 6 is the principle schematic of CRC-6 shift register.

Fig. 7 is several electronic circuit rough schematic views of CRC-6 shift register.

Embodiment

Embodiment

As shown in Figure 2, the utility model is used for arranging a kind of ECT/EVT merge cells interface cabinet, described cabinet is assembled by panel, cuboid support frame, upper and lower cover plates, left and right cover plate and back shroud, cabinet inside is embedded with guide rail and the electromagnetic shielding plate of plug optical fiber interface plate, in upper and lower cover plates, have mesh 1 and embed Air Filter in cover plate inner side, resistance screen touch-control display panel 3, communication serial ports 2 and LED relay indicating light are installed on panel, on resistance screen touch-control display panel, are connected with fpga chip.

Fpga chip of the present utility model adopts the ACEX1K family chip with embedded Array of low-power consumption, high reliability.

Described embedded Array is the flexible RAM piece with register on input/output port.

Panel of the present utility model, upper and lower cover plates, left and right cover plate, back shroud and cuboid support frame are panel, upper and lower cover plates, left and right cover plate, back shroud and the cuboid support frame that aluminum alloy materials is made.

Fpga chip bag of the present utility model expands 3 large modules: the embedded Array (mainly realizing FIFO function) that data reception module, CRC check module and ACEX1K family chip carry.As shown in Figure 3, data reception module comprises counter, BDB Bi-directional Data Bus, receive latch register, send latch register, receive shift register, send shift register and two logic controllers, described data reception module receives 12 circuit-switched data from outside A/D converter transmission by asynchronous serial mode, BDB Bi-directional Data Bus connects reception latch register and sends latch register, receiving latch register is connected with reception shift register, sending latch register is connected with transmission shift register, one of two logic controllers point are connected with reception shift register with reception latch register, two of two logic controllers are connected with transmission shift register with transmission latch register, each logic controller output is connected on and the control bit that receives latch and transmission latch, the clock signal of each logic controller is the carry signal of counter, sending latch register is connected with CRC check module, sending latch register is connected with the embedded Array that sends shift register and FPGA, described 12 circuit-switched data adopt UART communication interface.

As shown in Figure 5, Figure 6, CRC check module is 6 bit shift register, and each thinks that the relation VHDL language between register is described below: C (0) <=C (5) XOR DIN; C (1) <=C (0); C (2) <=C (1) XOR C (5); C (3) <=C (2); C (4) <=C (3); C (5) <=C (4) XOR C (5); Described C (0), C (1), C (2), C (3), C (4), C (5) refer to 6 shift registers, take to seal in and go out mode.

Transfer of data adopts Manchester's code, and first transmits MSB position, and meets FT3 frame format.

As shown in Figure 3, in the time that receiving terminal receives from 12 circuit-switched data of A/D converter, because transfer of data takes Manchester's code mode to carry out, therefore in data, there is MSB position, in order to detect the start bit of MSB specified data, the clock frequency of counter is 16 times of transfer of data frequency, therefore when counter recording occurring continuously 81 (high level), by self carry signal transmission logic controller, simultaneously by self zero clearing, the New count of laying equal stress on, while again receiving 81 (high level), self carry signal is sent to logic controller again, logic controller is received two carry signals from counter in (i.e. the clock cycle of 1/2nd transfer of data) at the appointed time, by the data conversion storage in BDB Bi-directional Data Bus to receiving on latch register and sending on latch register, after this gather data in a BDB Bi-directional Data Bus every the clock pulse (frequency 16MHZ) of 16 counters, its specific implementation will be realized according to connection shown in figure by XC18V01PC20_1 and XC2S50_3 as shown in Figure 4.

Data by unloading CRC check module after, 6 shift registers logic connecting relation as shown in Figure 5, realize the data that entered by DIN, totally 22 of data, according to FT3 coded, start bit (1)+voltage and/or current data information bit (16)+CRC generate position (6)+position of rest (1), wherein start bit and final value are that clock is high level (start bit) and low level (position of rest), therefore by 22 bit data, comprise that 16 bit data and 6 CRC generate position input CRC check module (CRC-6 shift register) as shown in Figure 5 or Figure 6, if the content of these 6 shift registers of C (5)～C (0) is 0 entirely, think transmission in without error code (CRC_OK=" 1 "), otherwise be judged to error code (CRC_WRONG=" 1 "), above-mentioned judgment mode if by and the result that goes out by realizing with gate (AND), therefore at Fig. 5, in Fig. 6, all omit, above-mentioned functions is by Fig. 5, in Fig. 6, circuit is realized.

Be aforementioned reception shift register and send shift register by the position of data storage by the embedded Array EAB carrying in fpga chip (EAB is the flexible RAM with register on input/output port, utilizes this EAB piece to realize first-in first-out FIFO function).

Through the above description of the embodiments, those skilled in the art can be well understood to the present invention and can circuit be write to the mode that chip adds essential common hardware by VHDL language and realize, can certainly pass through hardware, realize by some single-chip microcomputers, but the integrated level of single-chip microcomputer is too poor, and need to could realize the function in the utility model compared with multiple single chip microcomputer, therefore in a lot of situations, the former is better execution mode.Based on such understanding, the mode that the part that the technical solution of the utility model contributes to prior art in essence in other words can write programmable chip with VHDL language embodies, well-known VHDL language can be described hardware circuit function, signal annexation and timing relationship, simplify the exhibition method of programmable array, therefore in describing above, may provide and somely simplify understanding for describing the VHDL language of relation between circuit, avoid enclosing array of figure, cause describing and understand the difficulty of bringing, product of the present utility model can be integrated in programmable chip, realize aforementioned described logic array.

The utility model is not limited to above-described embodiment.All employings are equal to replaces the technical scheme forming, and all drops on the protection range of the utility model requirement.

Claims (3)

1. an ECT/EVT merge cells interface cabinet, described interface is placed in cabinet, described cabinet is assembled by panel, cuboid support frame, upper and lower cover plates, left and right cover plate and back shroud, it is characterized in that: cabinet inside is embedded with guide rail and the electromagnetic shielding plate of plug optical fiber interface plate, in described upper and lower cover plates, have mesh and the Air Filter of side embedding therein, resistance screen touch-control display panel, communication serial ports and LED relay indicating light are installed on described panel, on described resistance screen touch-control display panel, are connected with fpga chip.

2. a kind of ECT/EVT merge cells interface cabinet according to claim 1, is characterized in that: described fpga chip adopts the ACEX1K family chip with embedded Array.

3. a kind of ECT/EVT merge cells interface cabinet according to claim 2, is characterized in that: described panel, upper and lower cover plates, left and right cover plate, back shroud and cuboid support frame are panel, upper and lower cover plates, left and right cover plate, back shroud and the cuboid support frame that aluminum alloy materials is made.