CN202111067U - Improvement of semiconductor packaging die - Google Patents
Improvement of semiconductor packaging die Download PDFInfo
- Publication number
- CN202111067U CN202111067U CN2011201163879U CN201120116387U CN202111067U CN 202111067 U CN202111067 U CN 202111067U CN 2011201163879 U CN2011201163879 U CN 2011201163879U CN 201120116387 U CN201120116387 U CN 201120116387U CN 202111067 U CN202111067 U CN 202111067U
- Authority
- CN
- China
- Prior art keywords
- counterdie
- improvement
- lower die
- exhaust groove
- semiconductor packaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Moulds For Moulding Plastics Or The Like (AREA)
Abstract
The utility model relates to an improvement of a semiconductor packaging die. According to the technical scheme provided by the utility model: the improvement of a semiconductor packaging die comprises an upper die and a lower die; a channel of a lower die is opened on the lower die; and the channel of a lower die is opposite to a window on a substrate. The improvement of a semiconductor packaging die is characterized in that two sides of the channel of a lower die on the lower die are opened with a left exhaust groove and a right exhaust groove which are parallel with the channel of a lower die; and the left exhaust groove and the right exhaust groove are respectively communicated with the channel of a lower die through grooves. Through reasonable improvement in the structure of the conventional semiconductor packaging die, ie. the left exhaust groove and the right exhaust groove being opened on the two sides of the channel of a lower die and being communicated with the channel of a lower die, fluidity of packaging material is substantially reinforced; the qualified rate of a packaging product is increased; and performance of the packaging product is improved, because the percent defective of incomplete packaging reduces more than 80 percent than before.
Description
Technical field
The utility model relates to the semiconductor packaging field, specifically is a kind of improvement of semiconductor packaging mold.
Background technology
Along with improving constantly of semiconductor packaging level; The encapsulation components and parts develop to the direction of " light, thin, short, little "; Mould in the semiconductor packages moulding engineering has direct influence as core component to the qualification rate of product, and whether fully encapsulation also plays crucial effects to the self performance of product.
Semiconductor packaging mold generally comprises patrix 1 and counterdie 3, on counterdie 3, is provided with counterdie conduit 4 (as shown in Figure 1), and during encapsulation, encapsulating material 5 (like resin) gets into and is full of counterdie conduit 4, and cooling then realizes the encapsulation to product.The defective that this structure exists in practical application is: because the characteristic of material mechanics of encapsulating material 5 self; The not exclusively defective item of encapsulation appears easily; Small gap 6 (as shown in Figure 2) appears in edge part easily that be encapsulating material 5, thereby causes the qualification rate of encapsulating products low.
Summary of the invention
The purpose of the utility model is to overcome the deficiency that exists in the prior art, and the structure of conventional semiconductor packages mould has been carried out reasonable improvement, has improved the qualification rate of encapsulating products greatly, has improved the performance of encapsulating products.
The technical scheme that provides according to the utility model: the improvement of semiconductor packaging mold; Comprise upper die and lower die; On counterdie, offer the counterdie conduit; The window of counterdie conduit on the substrate, it is characterized in that: the counterdie conduit both sides on the said counterdie offer left bank gas groove and the right exhaust groove parallel with the counterdie conduit, and left bank gas groove and right exhaust groove are connected with the counterdie conduit through short slot respectively.
As the further improvement of the utility model, the degree of depth of said left bank gas groove and right exhaust groove is 3～5 μ m.
As the further improvement of the utility model, the degree of depth of said left bank gas groove and right exhaust groove is 5 μ m.
As the further improvement of the utility model, the cross section of said left bank gas groove and right exhaust groove is a triangle.
The utility model compared with prior art; Advantage is: through the structure of conventional semiconductor packages mould is rationally improved; Promptly offer left bank gas groove and the right exhaust groove that communicates with it, strengthened the flowability of encapsulating material greatly, improved the qualification rate of encapsulating products in the both sides of counterdie conduit; The cause not exclusively disqualification rate of encapsulation reduces more than 80% before comparing, and has improved the performance of encapsulating products.
Description of drawings
Fig. 1 is the partial sectional view of the counterdie conduit part of existing semiconductor packaging mold.
Fig. 2 is for having the structure cutaway view behind the encapsulated moulding in the semiconductor packaging mold now.
Fig. 3 is the partial sectional view of the counterdie conduit part of the utility model.
Fig. 4 is the structure cutaway view behind the encapsulated moulding in the utility model.
Embodiment
Below in conjunction with concrete accompanying drawing and embodiment the utility model is described further.
Like Fig. 3, shown in Figure 4, the utility model relates to the improvement of semiconductor packaging mold.Said semiconductor packaging mold comprises patrix 1 and counterdie 3, is substrate 2 to be packaged between patrix 1 and the counterdie 3, on counterdie 3, offers counterdie conduit 4, and counterdie conduit 4 is flow channels of encapsulating material 5, the window 2a of counterdie conduit 4 on the substrate 2; The improvement of the utility model is that counterdie conduit 4 both sides on counterdie 3 offer left bank gas groove parallel with counterdie conduit 47 and right exhaust groove 8, and left bank gas groove 7 is connected with counterdie conduit 4 through short slot 9 respectively with right exhaust groove 8.Through left bank gas groove 7 and right exhaust groove 8 are set, increased the venting quality of encapsulating mould, the flowability of encapsulating material 5 is able to strengthen greatly; Material flows more abundant; Reduce the generation of incomplete filling, improved the qualification rate of encapsulating products, improved the performance of encapsulating products.
As shown in Figure 3, in the utility model, the degree of depth of said left bank gas groove 7 and right exhaust groove 8 is 3～5 μ m, is preferably 5 μ m.The cross section of said left bank gas groove 7 and right exhaust groove 8 is a triangle.
Claims (4)
1. the improvement of semiconductor packaging mold; Comprise patrix (1) and counterdie (3); On counterdie (3), offer counterdie conduit (4); The window (2a) of counterdie conduit (4) on the substrate (2); It is characterized in that: counterdie conduit (4) both sides on the said counterdie (3) offer left bank gas groove (7) parallel with counterdie conduit (4) and right exhaust groove (8), and left bank gas groove (7) and right exhaust groove (8) are connected with counterdie conduit (4) through short slot (9) respectively.
2. the improvement of semiconductor packaging mold as claimed in claim 1 is characterized in that: the degree of depth of said left bank gas groove (7) and right exhaust groove (8) is 3 ~ 5 μ m.
3. the improvement of semiconductor packaging mold as claimed in claim 2 is characterized in that: the degree of depth of said left bank gas groove (7) and right exhaust groove (8) is 5 μ m.
4. the improvement of semiconductor packaging mold as claimed in claim 1 is characterized in that: the cross section of said left bank gas groove (7) and right exhaust groove (8) is a triangle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201163879U CN202111067U (en) | 2011-04-20 | 2011-04-20 | Improvement of semiconductor packaging die |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201163879U CN202111067U (en) | 2011-04-20 | 2011-04-20 | Improvement of semiconductor packaging die |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202111067U true CN202111067U (en) | 2012-01-11 |
Family
ID=45436521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011201163879U Expired - Fee Related CN202111067U (en) | 2011-04-20 | 2011-04-20 | Improvement of semiconductor packaging die |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202111067U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104030237A (en) * | 2013-03-08 | 2014-09-10 | 昌和生物医学科技(扬州)有限公司 | Microdevice and packaging mold for microdevice |
| CN104030232A (en) * | 2013-03-08 | 2014-09-10 | 昌微系统科技(上海)有限公司 | Microdevice, packaging mold for microdevice and packaging method |
| WO2015196518A1 (en) * | 2014-06-23 | 2015-12-30 | 深圳市华星光电技术有限公司 | Packaging method and packaging structure for substrate |
-
2011
- 2011-04-20 CN CN2011201163879U patent/CN202111067U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104030237A (en) * | 2013-03-08 | 2014-09-10 | 昌和生物医学科技(扬州)有限公司 | Microdevice and packaging mold for microdevice |
| CN104030232A (en) * | 2013-03-08 | 2014-09-10 | 昌微系统科技(上海)有限公司 | Microdevice, packaging mold for microdevice and packaging method |
| CN104030232B (en) * | 2013-03-08 | 2017-03-15 | 昌微系统科技(上海)有限公司 | A kind of microdevice, encapsulating mould and method for packing for the microdevice |
| CN104030237B (en) * | 2013-03-08 | 2017-05-24 | 昌和生物医学科技(扬州)有限公司 | Microdevice and packaging mold for microdevice |
| WO2015196518A1 (en) * | 2014-06-23 | 2015-12-30 | 深圳市华星光电技术有限公司 | Packaging method and packaging structure for substrate |
| CN104022145B (en) * | 2014-06-23 | 2017-01-25 | 深圳市华星光电技术有限公司 | Substrate packaging method and packaging structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120111 Termination date: 20180420 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |