CN201804856U - 表面贴装型半导体元件 - Google Patents

表面贴装型半导体元件 Download PDF

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CN201804856U
CN201804856U CN2010205207373U CN201020520737U CN201804856U CN 201804856 U CN201804856 U CN 201804856U CN 2010205207373 U CN2010205207373 U CN 2010205207373U CN 201020520737 U CN201020520737 U CN 201020520737U CN 201804856 U CN201804856 U CN 201804856U
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semiconductor element
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李升桦
王明连
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SICHUAN DAYAN ELECTRONICS CO Ltd
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Abstract

本实用新型公开了一种表面贴装型半导体元件，包括引线框架载体、粘片胶、内引线、芯片、塑封体，芯片通过粘片胶与引线框架载体相连，框架引脚由框架内引脚和框架外引脚组成，所述内引线的一端与芯片上的焊盘连接，另一端与框架内引脚连接；所述引线框架载体和框架外引脚与塑封体的下表面处于同一平面，塑封体将芯片、内引线、框架内引脚和引线框架外引脚的上表面包覆。本实用新型提供一种更轻、薄、小的表面贴装型半导体元件，通过将内引线和外引线短缩及封入塑封体内，降低封装所造成的寄生电阻及寄生电感，提高切换速度，并能提升封装可靠性及降低生产成本，工作安全可靠，适用范围广。

Description

表面贴装型半导体元件
技术领域
本实用新型涉及一种半导体元件，更具体的说涉及一种具有表面贴装型封装结构、特别适合搭载功率晶体管、功率二极管、电源管理集成电路、驱动集成电路等的半导体元件。
背景技术
表面贴装型半导体装置可以通过回流焊或流动焊等方法可靠且容易贴装在PCB电路基板上，可靠性高，应用十分广泛。
但是现有的半导体装置具有以下几项缺点：
1、内引线、内引脚及外引脚较长，造成的较大寄生电感，限制了功率晶体管的驱动电流上升速度及功率晶体管的切换速度；在功率晶体管导通时储存较大能量，截止时释放能量至外部线路，不仅降低效率更形成电压尖波的来源之一；并造成的较大寄生电阻，为导通电阻的一部份，在功率晶体管导通时消耗能量，降低系统效率。
2、外引脚较长，导致引线框架较宽，还需另外打弯成型，容易产生外引脚不共面问题，具有较高的生产成本。
3、引脚在一侧，中间引脚实际无使用价值，并导致引脚压线面积小，压线过程容易晃动，压线质量差，使耗材增加和制造成本高等问题。
4、塑封体较厚，使用塑封料较多，具有高的生产成本。
5、体积较大，占有PCB电路基板面积较大，不利于电路板缩小及降低成本。
发明内容
本实用新型主要解决的技术问题在于，提供一种更轻、薄、小的表面型半导体封装装置，降低封装所造成的寄生电阻及寄生电感，以降低导通电阻、提高切换速度，并能提升封装可靠性及降低生产成本。
本实用新型的技术方案为：一种表面贴装型半导体元件，包括引线框架载体、粘片胶、内引线、框架引脚、芯片、塑封体，芯片通过粘片胶与引线框架载体相连，框架引脚由框架内引脚和框架外引脚组成，所述内引线的一端与芯片上的焊盘连接，另一端与框架内引脚连接；所述引线框架载体和框架外引脚与塑封体的下表面处于同一平面，塑封体将芯片、内引线、框架内引脚和框架外引脚的上表面包覆。
所述框架引脚为2-5个。
所述内引线为金线、铜线、铝线、合金线中的一种或多种。
本实用新型与现有技术相比有如下优点：
1、降低封装所造成的寄生电阻及寄生电感，以降低导通电阻、提高切换速度，并能提升封装可靠性及降低生产成本。
2、本实用新型将引脚在框架制作时先行打弯和短缩，产品引脚外露长度由原来的2.5mm-2.9mm缩短为现在的0.1mm-0.4mm，从而引线框架变窄且减少基材的使用量约25％；切筋成型时只需切掉不需要的底筋部分，无需再打弯，不但避免了共面问题，而且切筋模具简易，从而降低生产成本。
3、本实用新型将原芯片封装的中间不使用的引脚取消，增加左右两侧引脚压线面积，引脚特别加大可适应功率晶体管的大电流要求，并解决压线过程容易晃动问题，提高压线质量。
4、本实用新型将框架内引脚高度降低，内引线可以短缩，并将塑封体厚度由原来的2.1mm-2.4mm降低为现在的1.4mm-1.7mm，减少树脂料使用量约30％，从而降低生产成本。
5、本实用新型将框架顶部减小，产品顶部框架外露长度由原来的0.8mm-1.3mm缩短为现在的0.1mm-0.4mm，从而减少基材的使用量，并进一步缩减产品体积，最终占有PCB电路基板面积缩小约30％，利于电路板缩小及降低成本。
附图说明
图1为与本实用新型实施形态有关的半导体元件的剖面结构示意图。
图2为图1的右视图。
图3为图1的后视图。
图4为本实施形态的半导体元件的剖面结构示意图。
图5为图4的右视图。
图6为图4的后视图。
图7为本实施形态的三引脚半导体元件的剖面结构示意图。
图8为图7的后视图。
图9为本实施形态的四引脚半导体元件的剖面结构示意图。
图10为图9的后视图。
图11为本实施形态的五引脚半导体元件的剖面结构示意图。
图12为图11的后视图。
图中标记为：1-引线框架载体、2-粘片胶、3-内引线、4-框架内引、5-芯片、6-塑封体、7-框架外引脚。
具体实施方式
下面结合附图对本实用新型做进一步详细叙述：
图1-图3为现有技术表面贴装型半导体元件的结构示意图，其引线框架载体载体1上自生中间引脚，而且内引线3、框架内引脚4和框架外引脚7较长，具有耗材耗能，体积大，功效差的缺点。
图4-图6为为本实用新型具有二引脚的表面型半导体元件，其包括：引线框架载体1、粘片胶2、半导体芯片5、引线框架内引脚4、引线框架外引脚7、塑封体6，芯片通过粘片胶2与引线框架载体1相连，芯片上的焊盘通过内引线3与框架内引脚4相接；所述引线框架载体1和框架外引脚7与塑封体6的下表面处于同一平面，芯片5、内引线3、引线框架内引脚4、引线框架外引脚7上表面被塑封体6包围成一整体。
以上的粘片胶3可以是软焊料、锡膏或芯片背覆软焊料，也可以是导电胶、不导电胶等。内引线可以是金线、铜线、铝线、铝带，也可以是各种合金线，可应用单一线材或多种线材混合应用。
举例说明，功率场效应晶体管应用本实用新型时，内引线3及外引线7短缩，芯片5通过软焊料2粘结于框架载体1，栅极(S极)可采用多条粗铝线或铝带与加大的内引脚4连接，与原有封装相比降低了封装所造成的寄生电阻及寄生电感，进一步降低导通电阻、提高切换速度。
图7-图8为本实施形态的三引脚半导体元件的结构示意图。关于上述附图，省略对与前面所述的图1-6的同一符号相同要素部分进行详细说明。
本实施形态的三引脚半导体装置中，在引线框架载体1上，放置芯片5，并设置三个内引脚与芯片5通过内引线3相接，三个外引脚7略凸出塑封体表面，便于贴装在PCB电路基板上。本变形例设置三个引脚，非常适合电源管理集成电路芯片的封装。
图9-图10为本实施形态的四引脚半导体装置的结构示意图。关于上述附图，省略对与前面所述的图1-8的同一符号相同要素部分进行详细说明。
本实施形态的四引脚半导体装置中，在引线框架载体1上，放置两个芯片5，并设置四个内引脚与芯片5通过内引线3相接，四个外引脚7略凸出塑封体表面，便于贴装在PCB电路基板上。本变形例设置四个引脚，非常适合双芯片的封装。
图11-图12为本实施形态的五引脚半导体元件的结构示意图。关于上述附图，省略对与前面所述的图1-10的同一符号相同要素部分进行详细说明。
本实施形态的五引脚半导体装置中，在引线框架载体1上，放置集成电路芯片5，并设置五个内引脚与芯片5通过内引线3相接，五个外引脚7略凸出塑封体表面，便于贴装在PCB电路基板上。本变形例设置五个引脚，非常适合电源驱动集成电路芯片的封装。
以上，参照具体例对本实用新型的实施形态进行说明。但是，本实用新型并不仅限于上述具体例。
例如，关于本实用新型中引线框架、半导体芯片、塑封体的具体形态或配置关系，业内人士对其进行适当设计变更的也属于本实用新型范围。
而且，半导体芯片也不仅限于具体举例说明的功率场效应晶体管或集成电路，使用其它各种半导体芯片也可以得到同样效果。

Claims (3)

1.一种表面贴装型半导体元件，包括引线框架载体(1)、粘片胶(2)、内引线(3)、框架引脚、芯片(5)、塑封体(6)，芯片(5)通过粘片胶(2)与引线框架载体(1)相连，框架引脚由框架内引脚(4)和框架外引脚(7)组成，其特征在于：所述内引线(3)的一端与芯片(5)上的焊盘连接，另一端与框架内引脚(4)连接；所述引线框架载体(1)和框架外引脚(7)与塑封体(6)的下表面处于同一平面，塑封体(6)将芯片(5)、内引线(3)、框架内引脚(4)和框架外引脚(7)的上表面包覆。
2.根据权利要求1所述的一种表面贴装型半导体元件，其特征在于：所述框架引脚为2-5个。
3.根据权利要求1所述的表面贴装型半导体元件，其特征在于：所述内引线(3)为金线、铜线、铝线、合金线中的一种或多种。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103378046A (zh) * 2012-04-26 2013-10-30 鸿富锦精密工业（深圳）有限公司 芯片组装结构及芯片组装方法
CN103500736A (zh) * 2013-08-22 2014-01-08 上海宏力半导体制造有限公司 芯片封装结构和芯片封装方法
CN106409805A (zh) * 2016-12-06 2017-02-15 四川富美达微电子有限公司 一种五引脚ic结构

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103378046A (zh) * 2012-04-26 2013-10-30 鸿富锦精密工业（深圳）有限公司 芯片组装结构及芯片组装方法
CN103500736A (zh) * 2013-08-22 2014-01-08 上海宏力半导体制造有限公司 芯片封装结构和芯片封装方法
CN103500736B (zh) * 2013-08-22 2017-04-26 上海华虹宏力半导体制造有限公司 芯片封装结构和芯片封装方法
CN106409805A (zh) * 2016-12-06 2017-02-15 四川富美达微电子有限公司 一种五引脚ic结构

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