CN201752003U - Lead frame structure for flip chip - Google Patents
Lead frame structure for flip chip Download PDFInfo
- Publication number
- CN201752003U CN201752003U CN2010201731459U CN201020173145U CN201752003U CN 201752003 U CN201752003 U CN 201752003U CN 2010201731459 U CN2010201731459 U CN 2010201731459U CN 201020173145 U CN201020173145 U CN 201020173145U CN 201752003 U CN201752003 U CN 201752003U
- Authority
- CN
- China
- Prior art keywords
- lead frame
- metal
- frame structure
- metal pins
- metal leg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to a lead frame structure for a flip chip, which comprises a plurality of metal pins (1); and the front surface and the back surface of each meal pin (1) are respectively provided with a first metal layer (3) and a second metal layer (4). The lead frame structure is characterized in that packless plastic packaged materials (2) are embedded at the peripheries of the metal pins (1) and the areas among the metal pins (1); the lower parts of the metal pins (1) are connected into a whole by the packless plastic packaged materials (2); and the size of the back surfaces of the metal pins (1) is less than that of the front surfaces of the metal pins (1), thus forming a metal pin (1) structure with large upper parts and small lower parts. The lead frame structure for the flip chip has the benefits that the package cost can be lowered, product categories for selection are wide, the quality of the flip chip and the reliability of a product have good stability, and plastic packaged bodies and the metal pins have large bonding capability.
Description
(1) technical field
The utility model relates to a kind of flip-chip lead frame structure.Belong to the semiconductor packaging field.
(2) background technology
Traditional flip-chip mainly contains two kinds with lead frame structure:
First kind of flip-chip lead frame structure:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 1) that to carry out encapsulation process.
Second kind of flip-chip lead frame structure:
After chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 2) of lead frame.Back etched is then carried out at the back side of lead frame again in encapsulation process.
And the not enough point of two kinds of above-mentioned lead frames below in encapsulation process, having existed:
First kind of flip-chip put following explanation with the lead frame deficiency of lead frame structure:
1) but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side.So directly increased high cost.
2) but also because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, so the load technology in encapsulation process can only be used conduction or nonconducting resin technology, and the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation.
3) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and in the flip-chip bonding technology in encapsulation process, because but the glued membrane of this high temperature resistance is a soft materials, so caused the instability of flip-chip bonding parameter, seriously influenced the stability of flip-chip quality and production reliability.
4) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and the plastic package process process in encapsulation process, because the high pressure of plastic packaging relation is easy to cause between lead frame and the glued membrane and infiltrates plastic packaging material, be that the kenel of conduction has become insulation pin (as shown in Figure 3) on the contrary because of having infiltrated plastic packaging material and will formerly should belong to metal leg.
Second kind of flip-chip put following explanation with the lead frame deficiency of lead frame structure:
The lead frame structure of this kind has carried out etching partially technology in the metal substrate front, though can solve the problem of first kind of lead frame, but because only carried out the work that etches partially in the metal substrate front, and plastic packaging material only envelopes the height of half pin in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg has just diminished, when if the plastic-sealed body paster is not fine to pcb board, does over again again and heavily paste, with regard to the problem (as shown in Figure 4) that is easy to generate pin.
Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provides a kind of and reduces that packaging cost, selectable product category are wide, the big flip-chip lead frame structure of constraint ability of good stability, plastic-sealed body and the metal leg of flip-chip quality and production reliability.
The purpose of this utility model is achieved in that a kind of flip-chip lead frame structure, comprise the number of metal pin, front and back at described metal leg is respectively arranged with the first metal layer and second metal level, zone between described metal leg periphery and metal leg and metal leg is equipped with packless plastic packaging material, described packless plastic packaging material links into an integrated entity the bottom of metal leg, and make described metal leg back side size less than the positive size of metal leg, form up big and down small metal leg structure.
The beneficial effects of the utility model are:
1) but the glued membrane of one deck costliness high temperature resistance need not sticked in the back side of the lead frame of this kind.So directly reduced high cost.
2) but because the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind yet, so the load technology in encapsulation process is except using conduction or nonconducting resin technology, can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable product category is just wide.
3) but again because the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind, guaranteed the stability of flip-chip bonding parameter, guaranteed the stability of flip-chip quality and production reliability.
4) but again because the lead frame of this kind need not stick the glued membrane of one deck high temperature resistance, and the plastic package process process in encapsulation process can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material.
5) because the zone between described metal leg and metal leg is equipped with packless soft gap filler, this packless soft gap filler has the filler plastic packaging material to envelope the height of whole metal leg with the routine in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg just becomes big, do not have the problem that produces pin again.
(4) description of drawings
Fig. 1 is the utility model flip-chip lead frame structure schematic diagram.
Fig. 2 was for sticked the resistant to elevated temperatures glued membrane flow diagram of one deck in the past at the back side of metal substrate.
Fig. 3 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Fig. 4 was for formed insulation pin schematic diagram in the past.
Fig. 5 pin figure for what formed in the past.
Reference numeral among the figure:
Metal leg 1, packless plastic packaging material 2, the first metal layer 3, second metal level 4.
(5) embodiment
As seen from Figure 1, Fig. 1 is the utility model flip-chip lead frame structure schematic diagram.The utility model flip-chip lead frame structure, comprise number of metal pin 1, front and back at described metal leg 1 is respectively arranged with the first metal layer 3 and second metal level 4, zone between described metal leg 1 periphery and metal leg 1 and metal leg 1 is equipped with packless plastic packaging material 2, and described packless plastic packaging material 2 links into an integrated entity the bottom of metal leg 1.
Claims (1)
1. flip-chip lead frame structure, comprise number of metal pin (1), front and back at described metal leg (1) is respectively arranged with the first metal layer (3) and second metal level (4), it is characterized in that: the zone between described metal leg (1) periphery and metal leg (1) and metal leg (1) is equipped with packless plastic packaging material (2), described packless plastic packaging material (2) links into an integrated entity the bottom of metal leg (1), and make described metal leg (1) back side size less than the positive size of metal leg (1), form up big and down small metal leg (1) structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201731459U CN201752003U (en) | 2010-04-21 | 2010-04-21 | Lead frame structure for flip chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201731459U CN201752003U (en) | 2010-04-21 | 2010-04-21 | Lead frame structure for flip chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201752003U true CN201752003U (en) | 2011-02-23 |
Family
ID=43602413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010201731459U Expired - Lifetime CN201752003U (en) | 2010-04-21 | 2010-04-21 | Lead frame structure for flip chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201752003U (en) |
-
2010
- 2010-04-21 CN CN2010201731459U patent/CN201752003U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20110223 |
|
| CX01 | Expiry of patent term |