CN201681877U - Sinking base island exposed encapsulation structure - Google Patents
Sinking base island exposed encapsulation structure Download PDFInfo
- Publication number
- CN201681877U CN201681877U CN2010201784649U CN201020178464U CN201681877U CN 201681877 U CN201681877 U CN 201681877U CN 2010201784649 U CN2010201784649 U CN 2010201784649U CN 201020178464 U CN201020178464 U CN 201020178464U CN 201681877 U CN201681877 U CN 201681877U
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- Prior art keywords
- pin
- base island
- dao
- chip
- metal
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Abstract
The utility model relates to a sinking base island exposed encapsulation structure, which comprises a base island (1), a pin (2), electrically conducting or non-conducting adhesive materials (6), a chip (7), a metal wire (8) and plastic encapsulation materials (9) with fillings. The central area on the front surface of the base island (1) is sunk; a first metal layer (4) is arranged on the front surface of the pin (2); second metal layers (5) are arranged on the back surfaces of the base island (1) and the pin (2); the chip (7) is arranged in the central sunk area on the front surface of the base island (1) by the aid of the electrically conducting or non-conducting adhesive materials (6); the front surface of the chip (7) is connected with the first metal layer (4) on the front surface of the pin (2) by the aid of the metal wire (8); the plastic encapsulation materials (9) with fillings are covered on the upper portions of the base island (1) and the pin (2) and outside the chip (7) and the metal wire (8) in a sealing manner; encapsulation materials (3) without fillings are embedded into areas on the outer periphery of the pin (2) and between the base island (1) and the pin (2); and the sizes of the back surfaces of the base island (1) and the pin (2) are smaller than those of the front surfaces of the base island (1) and the pin (2), so that a base island and pin structure with a large upper portion and a small lower portion is formed. The sinking base island exposed encapsulation structure has the advantage of large bound capacity of a plastic encapsulation body and a metal pin.
Description
(1) technical field
The utility model relates to the base island exposed type encapsulating structure of a kind of sinking.Belong to the semiconductor packaging field.
(2) background technology
Traditional encapsulating structure mainly contains two kinds:
First kind: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 3) that to carry out encapsulation process;
Second kind: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 4) of lead frame.Back etched is then carried out at the back side of lead frame again in encapsulation process.
And the not enough point of two kinds of above-mentioned lead frames below in encapsulation process, having existed:
First kind:
1) but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side.So directly increased high cost.
2) but also because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, so the load technology in encapsulation process can only be used conduction or nonconducting resin technology, and the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation.
3) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and in the ball bonding bonding technology in encapsulation process, because but the glued membrane of this high temperature resistance is a soft materials, so caused the instability of ball bonding bonding parameter, seriously influenced the quality of ball bonding and the stability of production reliability.
4) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and the plastic package process process in encapsulation process, because the high pressure of plastic packaging relation is easy to cause between lead frame and the glued membrane and infiltrates plastic packaging material, be that the kenel of conduction has become insulation pin (as shown in Figure 5) on the contrary because of having infiltrated plastic packaging material and will formerly should belong to metal leg.
Second kind:
The lead frame structure of this kind has carried out etching partially technology in the metal substrate front, though can solve the problem of first kind of lead frame, but because only carried out the work that etches partially in the metal substrate front, and plastic packaging material only envelopes the height of half pin in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg has just diminished, when if the plastic-sealed body paster is not fine to pcb board, does over again again and heavily paste, with regard to the problem (as shown in Figure 6) that is easy to generate pin.
Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provides a kind of and reduces that packaging cost, selectable product category are wide, the big base island exposed type encapsulating structure of sinking of constraint ability of good stability, plastic-sealed body and the metal leg of the quality of ball bonding and production reliability.
The purpose of this utility model is achieved in that the base island exposed type encapsulating structure of a kind of sinking, comprise Ji Dao, pin, conduction or non-conductive bonding material, chip, metal wire and the filler plastic packaging material arranged, described basic island 1 front middle section sinks, front at described pin is provided with the first metal layer, be provided with second metal level at the back side of Ji Dao and pin, positive central sunken regions is provided with chip by conduction or non-conductive bonding material on basic island, be connected with metal wire between chip front side and the pin front the first metal layer, outside the top of described Ji Dao and pin and chip and metal wire, be encapsulated with the filler plastic packaging material, no filler plastic packaging material is set in zone between described pin periphery and Ji Dao and pin, described no filler plastic packaging material links into an integrated entity the bottom of periphery, pin bottom and Ji Dao and pin, and make described Ji Dao and pin back side size less than Ji Dao and the positive size of pin, form up big and down small Ji Dao and pin configuration.
The beneficial effects of the utility model are:
1) but the glued membrane of one deck costliness high temperature resistance need not sticked in the back side of the lead frame of this kind.So directly reduced high cost.
2) but because the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind yet, so the load technology in encapsulation process is except using conduction or nonconducting resin technology, can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable product category is just wide.
3) but again because the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind, guaranteed the stability of ball bonding bonding parameter, guaranteed the quality of ball bonding and the stability of production reliability.
4) but again because the lead frame of this kind need not stick the glued membrane of one deck high temperature resistance, and the plastic package process process in encapsulation process can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material.
5) because packless soft gap filler is set in the zone between described metal leg (pin) and metal leg, this packless soft gap filler has the filler plastic packaging material to envelope the height of whole metal leg with the routine in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg just becomes big, do not have the problem that produces pin again.
6) owing to adopted positive method of separating the etching operation with the back side, so in the etching operation, can form the slightly little and big slightly structure of positive basic island size of the size of back side Ji Dao, and with the size that varies in size up and down of a Ji Dao by tighter more difficult generation slip that no filler plastic packaging material coated and fall pin.
(4) description of drawings
Fig. 1 is base island exposed type encapsulating structure schematic diagram for the utility model sinks.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was for sticked the resistant to elevated temperatures glued membrane figure of one deck operation in the past at the back side of metal substrate.
Fig. 4 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Fig. 5 was for formed insulation pin schematic diagram in the past.
Fig. 6 pin figure for what formed in the past.
Reference numeral among the figure:
The base island 1, pin 2, no filler plastic packaging material 3, the first metal layer 4, second metal level 5, conduction or non-conductive bonding material 6, chip 7, metal wire 8, filler plastic packaging material 9 is arranged.
(5) embodiment
Referring to Fig. 1～2, Fig. 1 is base island exposed type encapsulating structure schematic diagram for the utility model sinks.Fig. 2 is the vertical view of Fig. 1.By Fig. 1 and Fig. 2 as can be seen, the utility model base island exposed type encapsulating structure that sinks, comprise basic island 1, pin 2, conduction or non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material 9 is arranged, described basic island 1 front middle section sinks, be provided with the first metal layer 4 in the front of described pin 2, be provided with second metal level 5 at the back side of basic island 1 and pin 2, be provided with chip 7 in basic island 1 positive central sunken regions by conduction or non-conductive bonding material 6, chip 7 positive with pin 2 front the first metal layers 4 between be connected with metal wire 8, outside the top of described basic island 1 and pin 2 and chip 7 and metal wire 8, be encapsulated with filler plastic packaging material 9, no filler plastic packaging material 3 is set in zone between described pin 2 peripheries and basic island 1 and pin 2, described no filler plastic packaging material 3 links into an integrated entity the bottom of peripheral and basic island 1, pin 2 bottoms with pin 2, and make described basic island 1 and pin 2 back side sizes less than basic island 1 and pin 2 positive sizes, form up big and down small Ji Dao and pin configuration.
Claims (1)
1. base island exposed type encapsulating structure that sinks, comprise Ji Dao (1), pin (2), conduction or non-conductive bonding material (6), chip (7), metal wire (8) and filler plastic packaging material (9) is arranged, described Ji Dao (1) front middle section sinks, be provided with the first metal layer (4) in the front of described pin (2), the back side at Ji Dao (1) and pin (2) is provided with second metal level (5), be provided with chip (7) in the positive central sunken regions of Ji Dao (1) by conduction or non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between be connected with metal wire (8), outside the top of described Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9), it is characterized in that: no filler plastic packaging material (3) is set in the zone between described pin (2) periphery and Ji Dao (1) and pin (2), described no filler plastic packaging material (3) links into an integrated entity the bottom of pin (2) periphery, bottom and Ji Dao (1) and pin (2), and make described Ji Dao (1) and pin (2) back side size less than Ji Dao (1) and the positive size of pin (2), form up big and down small Ji Dao and pin configuration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201784649U CN201681877U (en) | 2010-04-26 | 2010-04-26 | Sinking base island exposed encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201784649U CN201681877U (en) | 2010-04-26 | 2010-04-26 | Sinking base island exposed encapsulation structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201681877U true CN201681877U (en) | 2010-12-22 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010201784649U Expired - Lifetime CN201681877U (en) | 2010-04-26 | 2010-04-26 | Sinking base island exposed encapsulation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201681877U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681579A (en) * | 2013-12-05 | 2014-03-26 | 江苏长电科技股份有限公司 | Secondary first-corrosion-then-plating metal frame subtraction burying chip obverse-mounting flat foot structure and technology method |
-
2010
- 2010-04-26 CN CN2010201784649U patent/CN201681877U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681579A (en) * | 2013-12-05 | 2014-03-26 | 江苏长电科技股份有限公司 | Secondary first-corrosion-then-plating metal frame subtraction burying chip obverse-mounting flat foot structure and technology method |
| CN103681579B (en) * | 2013-12-05 | 2016-03-30 | 江苏长电科技股份有限公司 | Secondary etching-prior-to-plametal metal frame subtraction buries the flat leg structure of chip formal dress and process |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101222 |