CN201681900U - Exposing type and embedded type base-island packaging structure - Google Patents
Exposing type and embedded type base-island packaging structure Download PDFInfo
- Publication number
- CN201681900U CN201681900U CN2010201847309U CN201020184730U CN201681900U CN 201681900 U CN201681900 U CN 201681900U CN 2010201847309 U CN2010201847309 U CN 2010201847309U CN 201020184730 U CN201020184730 U CN 201020184730U CN 201681900 U CN201681900 U CN 201681900U
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- China
- Prior art keywords
- dao
- pin
- base island
- island
- back side
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to an exposing-type and embedded type base-island packaging structure, which comprises base islands (1), lead pins (2), conductive or nonconductive binding materials (6), a chip (7), a metal wire (8) and packing plastic materials (9). Two sets of base islands (1) are provided, wherein one set is a first base island (1.1) and the other set is a second base island (1.2); a metal layer (4) is arranged on the front surface of the first base island (1.1), the second base island (1.2) and the lead pins (2); a second metal layer (5) is arranged on the back surface of the first base island (1.1) and the lead pins (2); packing-free plastic materials (3) are embedded in the periphery of the lead pins (2), in the area between the lead pins (2) and the first base island (1.1), in the back surface of the second base island (1.2), in the area between the second base island (1.2) and the first base island (1.2), and in the area between the second base island (1.2) and the lead pins (2); and the size of the back surface of the first base island (1.1) and the lead pins (2) is smaller than the size of the front surface of the first base island (1.1) and the lead pins (2). The binding capacity of the plastic-sealed body and the metal pins is large.
Description
(1) technical field
The utility model relates to a kind of base island exposed type and baried type base island encapsulating structure.Belong to the semiconductor packaging field.
(2) background technology
Traditional encapsulating structure mainly contains two kinds:
First kind: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 3) that to carry out encapsulation process;
Second kind: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 4) of lead frame.Back etched is then carried out at the back side of lead frame again in encapsulation process.
And the not enough point of two kinds of above-mentioned lead frames below in encapsulation process, having existed:
First kind:
1) but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side.So directly increased high cost.
2) but also because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, so the load technology in encapsulation process can only be used conduction or nonconducting resin technology, and the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation.
3) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and in the ball bonding bonding technology in encapsulation process, because but the glued membrane of this high temperature resistance is a soft materials, so caused the instability of ball bonding bonding parameter, seriously influenced the quality of ball bonding and the stability of production reliability.
4) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and the plastic package process process in encapsulation process, because the high pressure of plastic packaging relation is easy to cause between lead frame and the glued membrane and infiltrates plastic packaging material, be that the kenel of conduction has become insulation pin (as shown in Figure 5) on the contrary because of having infiltrated plastic packaging material and will formerly should belong to metal leg.
Second kind:
The lead frame structure of this kind has carried out etching partially technology in the metal substrate front, though can solve the problem of first kind of lead frame, but because only carried out the work that etches partially in the metal substrate front, and plastic packaging material only envelopes the height of half pin in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg has just diminished, when if the plastic-sealed body paster is not fine to pcb board, does over again again and heavily paste, with regard to the problem (as shown in Figure 6) that is easy to generate pin.
Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provides a kind of and reduces that packaging cost, selectable product category are wide, the big base island exposed type and the baried type base island encapsulating structure of constraint ability of good stability, plastic-sealed body and the metal leg of the quality of ball bonding and production reliability.
The purpose of this utility model is achieved in that a kind of base island exposed type and baried type base island encapsulating structure, comprise Ji Dao, pin, conduction or non-conductive bonding material, chip, metal wire and the filler plastic packaging material arranged, described Ji Dao has two groups, one group is first Ji Dao, another group is second Ji Dao, at described first Ji Dao, the front of second Ji Dao and pin is provided with the first metal layer, the back side at described first Ji Dao and pin is provided with second metal level, be provided with chip in front, basic island by conduction or non-conductive bonding material, all be connected between chip front side and the pin front the first metal layer and between chip and the chip with metal wire, outside the top of described Ji Dao and pin and chip and metal wire, be encapsulated with the filler plastic packaging material, zone in described pin periphery, zone between the pin and the first basic island, the second Ji Dao back side, no filler plastic packaging material is set in zone between second Ji Dao and the first basic island and the zone between second Ji Dao and the pin, described no filler plastic packaging material is with periphery, pin bottom, the pin and the first Ji Dao bottom, the second Ji Dao back side, the second Ji Dao back side and the first Ji Dao bottom and the second Ji Dao back side and pin bottom link into an integrated entity, and make described first Ji Dao and pin back side size less than first Ji Dao and the positive size of pin, form up big and down small first Ji Dao and pin configuration.
The beneficial effects of the utility model are:
1) but the glued membrane of one deck costliness high temperature resistance need not sticked in the back side of the lead frame of this kind.So directly reduced high cost.
2) but because the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind yet, so the load technology in encapsulation process is except using conduction or nonconducting resin technology, can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable product category is just wide.
3) but again because the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind, guaranteed the stability of ball bonding bonding parameter, guaranteed the quality of ball bonding and the stability of production reliability.
4) but again because the lead frame of this kind need not stick the glued membrane of one deck high temperature resistance, and the plastic package process process in encapsulation process can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material.
5) because the soft gap filler of no filler is set in the zone between described metal leg (pin) and metal leg, this packless soft gap filler has the filler plastic packaging material to envelope the height of whole metal leg with the routine in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg just becomes big, do not have the problem that produces pin again.
6) owing to adopted positive method of separating the etching operation with the back side, so in the etching operation, can form the slightly little and big slightly structure of positive basic island size of the size of back side Ji Dao, and with the size that varies in size up and down of a Ji Dao by tighter more difficult generation slip that no filler plastic packaging material coated and fall pin.
(4) description of drawings
Fig. 1 is base island exposed type of the utility model and baried type base island encapsulating structure schematic diagram.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was for sticked the resistant to elevated temperatures glued membrane figure of one deck operation in the past at the back side of metal substrate.
Fig. 4 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Fig. 5 was for formed insulation pin schematic diagram in the past.
Fig. 6 pin figure for what formed in the past.
Reference numeral among the figure:
Base island 1.1, the second basic island 1.2,1, the first basic island, pin 2, no filler plastic packaging material 3, the first metal layer 4, second metal level 5, conduction or non-conductive bonding material 6, chip 7, metal wire 8, filler plastic packaging material 9 is arranged.
(5) embodiment
Referring to Fig. 1~2, Fig. 1 is base island exposed type of the utility model and baried type base island encapsulating structure schematic diagram.Fig. 2 is the vertical view of Fig. 1.By Fig. 1 and Fig. 2 as can be seen, base island exposed type of the utility model and baried type base island encapsulating structure, comprise basic island 1, pin 2, conduction or non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material 9 is arranged, described basic island 1 has two groups, one group is the first basic island 1.1, another group is the second basic island 1.2, on the described first basic island 1.1, the front of the second basic island 1.2 and pin 2 is provided with the first metal layer 4, the back side at the described first basic island 1.1 and pin 2 is provided with second metal level 5, be provided with chip 7 in 1 front, basic island by conduction or non-conductive bonding material 6, chip 7 positive with pin 2 front the first metal layers 4 between and all be connected between chip 7 and the chip 7 with metal wire 8, outside the top of described basic island 1 and pin 2 and chip 7 and metal wire 8, be encapsulated with filler plastic packaging material 9, zone in described pin 2 peripheries, zone between the pin 2 and the first basic island 1.1,1.2 back sides, the second basic island, no filler plastic packaging material 3 is set in zone between the second basic island 1.2 and the first basic island 1.1 and the zone between the second basic island 1.2 and the pin 2, described no filler plastic packaging material 3 is with periphery, pin bottom, pin 2 and 1.1 bottoms, the first basic island, 1.2 back sides, the second basic island, second 1.2 back sides, basic island and first 1.1 bottoms, basic island and second 1.2 back sides, basic island and pin 2 bottoms link into an integrated entity, and make the described first basic island 1.1 and pin 2 back side sizes less than the first basic island 1.1 and pin 2 positive sizes, form up big and down small first Ji Dao and pin configuration.
Claims (1)
1. base island exposed type and baried type base island encapsulating structure, comprise Ji Dao (1), pin (2), conduction or non-conductive bonding material (6), chip (7), metal wire (8) and filler plastic packaging material (9) is arranged, described Ji Dao (1) has two groups, one group is first Ji Dao (1.1), another group is second Ji Dao (1.2), at described first Ji Dao (1.1), the front of second Ji Dao (1.2) and pin (2) is provided with the first metal layer (4), the back side at described first Ji Dao (1.1) and pin (2) is provided with second metal level (5), be provided with chip (7) in Ji Dao (1) front by conduction or non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between and all use metal wire (8) to be connected between chip (7) and the chip (7), outside the top of described Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9), it is characterized in that: in the peripheral zone of described pin (2), zone between pin (2) and first Ji Dao (1.1), second Ji Dao (1.2) back side, no filler plastic packaging material (3) is set in zone between second Ji Dao (1.2) and first Ji Dao (1.1) and the zone between second Ji Dao (1.2) and the pin (2), described no filler plastic packaging material (3) is with periphery, pin bottom, pin (2) and first Ji Dao (1.1) bottom, second Ji Dao (1.2) back side, second Ji Dao (1.2) back side and first Ji Dao (1.1) bottom and second Ji Dao (1.2) back side and pin (2) bottom link into an integrated entity, and make described first Ji Dao (1.1) and pin (2) back side size less than first Ji Dao (1.1) and the positive size of pin (2), form up big and down small first Ji Dao and pin configuration.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2010201847309U CN201681900U (en) | 2010-05-05 | 2010-05-05 | Exposing type and embedded type base-island packaging structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN2010201847309U CN201681900U (en) | 2010-05-05 | 2010-05-05 | Exposing type and embedded type base-island packaging structure |
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CN201681900U true CN201681900U (en) | 2010-12-22 |
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CN2010201847309U Expired - Lifetime CN201681900U (en) | 2010-05-05 | 2010-05-05 | Exposing type and embedded type base-island packaging structure |
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CN (1) | CN201681900U (en) |
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2010
- 2010-05-05 CN CN2010201847309U patent/CN201681900U/en not_active Expired - Lifetime
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Granted publication date: 20101222 |
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