CN201681872U - Encapsulation structure for multiple base-island exposure type multi-turn pins - Google Patents
Encapsulation structure for multiple base-island exposure type multi-turn pins Download PDFInfo
- Publication number
- CN201681872U CN201681872U CN2010201777700U CN201020177770U CN201681872U CN 201681872 U CN201681872 U CN 201681872U CN 2010201777700 U CN2010201777700 U CN 2010201777700U CN 201020177770 U CN201020177770 U CN 201020177770U CN 201681872 U CN201681872 U CN 201681872U
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- Prior art keywords
- pin
- dao
- pins
- base
- metal
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- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model relates to an encapsulation structure for multiple base-island exposure type multi-turn pins, comprising base islands (1), pins (2), conductive or nonconductive coherent substances (6), chips (7), metal wires (8) and packed plastic sealing materials (9), wherein the front surface and the back surface of each base island (1) and each pin (2) are respectively provided with a first metal layer (4) and a second metal layer (5); the front surface of each base island (1) is provided with chips (7) by the conductive or nonconductive coherent substances (6); the first metal layer (4) on the front surface of each chip (7) and the first metal layer (4) on the front surface of each pin (2) are connected with each other by the metal wire (8); the quantity of the base islands (1) is more than one; the pins (2) have multiple turns; packless plastic sealing materials (3) are embedded at the peripheries of the pins (2), in the region among the pins (2), in the region among the pins (2) and the base islands (1) and in the region among the base islands (1); and furthermore, the dimensions of the back surfaces of the base islands (1) and the pins (2) are less than those of the front surfaces of the base islands (1) and the pins (2), thus forming an base island and pin structure with a large top and a small bottom. The encapsulation structure has the benefit that the bonding capability of plastic sealing bodies and the metal pins is great.
Description
(1) technical field
The utility model relates to a kind of a plurality of base island exposed type multi-turn leaded package.Belong to the semiconductor packaging field.
(2) background technology
Traditional encapsulating structure mainly contains two kinds:
First kind: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, stick the resistant to elevated temperatures glued membrane of one deck at the back side of metal substrate and form the leadframe carrier (as shown in Figure 3) that to carry out encapsulation process;
Second kind: after chemical etching and surface electrical coating are carried out in the front of employing metal substrate, promptly finish the making (as shown in Figure 4) of lead frame.Back etched is then carried out at the back side of lead frame again in encapsulation process.
And the not enough point of two kinds of above-mentioned lead frames below in encapsulation process, having existed:
First kind:
1) but the lead frame of this kind must stick the glued membrane of one deck costliness high temperature resistance because of the back side.So directly increased high cost.
2) but also because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, so the load technology in encapsulation process can only be used conduction or nonconducting resin technology, and the technology that can not adopt eutectic technology and slicken solder is fully carried out load, so selectable product category just has bigger limitation.
3) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and in the ball bonding bonding technology in encapsulation process, because but the glued membrane of this high temperature resistance is a soft materials, so caused the instability of ball bonding bonding parameter, seriously influenced the quality of ball bonding and the stability of production reliability.
4) but again because the glued membrane of one deck high temperature resistance must be sticked in the back side of the lead frame of this kind, and the plastic package process process in encapsulation process, because the high pressure of plastic packaging relation is easy to cause between lead frame and the glued membrane and infiltrates plastic packaging material, be that the kenel of conduction has become insulation pin (as shown in Figure 5) on the contrary because of having infiltrated plastic packaging material and will formerly should belong to metal leg.
Second kind:
The lead frame structure of this kind has carried out etching partially technology in the metal substrate front, though can solve the problem of first kind of lead frame, but because only carried out the work that etches partially in the metal substrate front, and plastic packaging material only envelopes the height of half pin in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg has just diminished, when if the plastic-sealed body paster is not fine to pcb board, does over again again and heavily paste, with regard to the problem (as shown in Figure 6) that is easy to generate pin.
Especially the kind of plastic packaging material is to adopt when filler is arranged, because material is at the environment and the follow-up surface-pasted stress changing relation of production process, can cause metal and plastic packaging material to produce the crack of vertical-type, its characteristic is the high more then hard more crisp more crack that is easy to generate more of proportion of filler.
(3) summary of the invention
The purpose of this utility model is to overcome above-mentioned deficiency, provides a kind of and reduces that packaging cost, selectable product category are wide, the big a plurality of base island exposed type multi-turn leaded package of constraint ability of good stability, plastic-sealed body and the metal leg of the quality of ball bonding and production reliability.
The purpose of this utility model is achieved in that a kind of a plurality of base island exposed type multi-turn leaded package, comprise Ji Dao, pin, conduction or non-conductive bonding material, chip, metal wire and the filler plastic packaging material arranged, front and back at described Ji Dao and pin is respectively arranged with the first metal layer and second metal level, be provided with chip in front, basic island by conduction or non-conductive bonding material, be connected with metal wire between chip front side and the pin front the first metal layer, outside the top of described Ji Dao and pin and chip and metal wire, be encapsulated with the filler plastic packaging material, described Ji Dao is provided with a plurality of, pin is provided with multi-turn, in described pin periphery, zone between pin and the pin, no filler plastic packaging material is set in zone between zone between pin and the basic island and Ji Dao and the basic island, described packless plastic packaging material is with periphery, pin bottom, pin and pin bottom, the bottom of pin and Ji Dao bottom and Ji Dao and Ji Dao links into an integrated entity, and make described Ji Dao and pin back side size less than Ji Dao and the positive size of pin, form up big and down small Ji Dao and pin configuration.
The beneficial effects of the utility model are:
1) but the glued membrane of one deck costliness high temperature resistance need not sticked in the back side of the lead frame of this kind.So directly reduced high cost.
2) but because the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind yet, so the load technology in encapsulation process is except using conduction or nonconducting resin technology, can also adopt the technology of eutectic technology and slicken solder to carry out load, so selectable product category is just wide.
3) but again because the glued membrane of one deck high temperature resistance need not sticked in the back side of the lead frame of this kind, guaranteed the stability of ball bonding bonding parameter, guaranteed the quality of ball bonding and the stability of production reliability.
4) but again because the lead frame of this kind need not stick the glued membrane of one deck high temperature resistance, and the plastic package process process in encapsulation process can not cause between lead frame and the glued membrane fully and infiltrate plastic packaging material.
5) because the soft gap filler of no filler is set in the zone between described metal leg (pin) and metal leg, this packless soft gap filler has the filler plastic packaging material to envelope the height of whole metal leg with the routine in the plastic packaging process, so the constraint ability of plastic-sealed body and metal leg just becomes big, do not have the problem that produces pin again.
6) owing to adopted positive method of separating the etching operation with the back side, so in the etching operation, can form the slightly little and big slightly structure of positive basic island size of the size of back side Ji Dao, and slided by the tighter more difficult generation that packless plastic packaging material coated and falling pin with the size that varies in size up and down of a Ji Dao.
(4) description of drawings
Fig. 1 is a plurality of base island exposed type multi-turn leaded package schematic diagrames of the utility model.
Fig. 2 is the vertical view of Fig. 1.
Fig. 3 was for sticked the resistant to elevated temperatures glued membrane figure of one deck operation in the past at the back side of metal substrate.
Fig. 4 was for to adopt the front of metal substrate to carry out chemical etching and surface electrical coating flow diagram in the past.
Fig. 5 was for formed insulation pin schematic diagram in the past.
Fig. 6 pin figure for what formed in the past.
Reference numeral among the figure:
The base island 1, pin 2, packless plastic packaging material 3, the first metal layer 4, second metal level 5, conduction or non-conductive bonding material 6, chip 7, metal wire 8, filler plastic packaging material 9 is arranged.
(5) embodiment
Referring to Fig. 1～2, Fig. 1 is a plurality of base island exposed type multi-turn leaded package schematic diagrames of the utility model.Fig. 2 is the vertical view of Fig. 1.By Fig. 1 and Fig. 2 as can be seen, the a plurality of base island exposed type multi-turn leaded packages of the utility model, comprise basic island 1, pin 2, conduction or non-conductive bonding material 6, chip 7, metal wire 8 and filler plastic packaging material 9 is arranged, front and back at described basic island 1 and pin 2 is respectively arranged with the first metal layer 4 and second metal level 5, be provided with chip 7 in 1 front, basic island by conduction or non-conductive bonding material 6, chip 7 positive with pin 2 front the first metal layers 4 between be connected with metal wire 8, outside the top of described Ji Dao and pin and chip and metal wire, be encapsulated with filler plastic packaging material 9, described basic island 1 is provided with a plurality of, pin 2 is provided with multi-turn, in described pin 2 peripheries, zone between pin 2 and the pin 2, no filler plastic packaging material 3 is set in zone between pin 2 and the basic island 1 and the zone between basic island 1 and the basic island 1, described packless plastic packaging material 3 is with periphery, pin 2 bottom, pin 2 and pin 2 bottoms, pin 2 links into an integrated entity with the bottom on 1 bottom, basic island and basic island 1 and basic island 1, and make described basic island 1 and pin 2 back side sizes less than basic island 1 and pin 2 positive sizes, form up big and down small Ji Dao and pin configuration.
Claims (1)
1. a plurality of base island exposed type multi-turn leaded package, comprise Ji Dao (1), pin (2), conduction or non-conductive bonding material (6), chip (7), metal wire (8) and filler plastic packaging material (9) is arranged, front and back at described Ji Dao (1) and pin (2) is respectively arranged with the first metal layer (4) and second metal level (5), be provided with chip (7) in Ji Dao (1) front by conduction or non-conductive bonding material (6), chip (7) positive with pin (2) front the first metal layer (4) between be connected with metal wire (8), outside the top of described Ji Dao (1) and pin (2) and chip (7) and metal wire (8), be encapsulated with filler plastic packaging material (9), it is characterized in that: described Ji Dao (1) is provided with a plurality of, pin (2) is provided with multi-turn, in described pin (2) periphery, zone between pin (2) and the pin (2), no filler plastic packaging material (3) is set in zone between zone between pin (2) and the Ji Dao (1) and Ji Dao (1) and the Ji Dao (1), described packless plastic packaging material (3) is with pin (2) periphery, bottom, pin (2) and pin (2) bottom, pin (2) links into an integrated entity with the bottom of Ji Dao (1) bottom and Ji Dao (1) and Ji Dao (1), and make described Ji Dao (1) and pin (2) back side size less than Ji Dao (1) and the positive size of pin (2), form up big and down small Ji Dao and pin configuration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201777700U CN201681872U (en) | 2010-04-26 | 2010-04-26 | Encapsulation structure for multiple base-island exposure type multi-turn pins |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010201777700U CN201681872U (en) | 2010-04-26 | 2010-04-26 | Encapsulation structure for multiple base-island exposure type multi-turn pins |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201681872U true CN201681872U (en) | 2010-12-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010201777700U Expired - Lifetime CN201681872U (en) | 2010-04-26 | 2010-04-26 | Encapsulation structure for multiple base-island exposure type multi-turn pins |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201681872U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117712079A (en) * | 2024-02-02 | 2024-03-15 | 合肥中航天成电子科技有限公司 | Be used for SOP encapsulation and package production facility |
-
2010
- 2010-04-26 CN CN2010201777700U patent/CN201681872U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117712079A (en) * | 2024-02-02 | 2024-03-15 | 合肥中航天成电子科技有限公司 | Be used for SOP encapsulation and package production facility |
| CN117712079B (en) * | 2024-02-02 | 2024-04-16 | 合肥中航天成电子科技有限公司 | Be used for SOP encapsulation and package production facility |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20101222 |